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U350
Hybrid Quad Silicon Junction Field-Effect Transistor Array
Absolute maximum ratings at TA= 25¡C.
Reverse Gate Source & Reverse Gate Drain Voltage – 25 V
Gate Current 25 mA
Continuous Device Power Dissipation 400 mW
Power Derating 3.2 mW/°C
TOÐ78 Package
Dimensions in Inches (mm)
Pin Configuration
1 Gate 1 & 3, 2 Drain 1 & 4,
3 Source 1 & 2, 4 Ground & Case,
5 Source 3 & 4, 6 Drain 2 & 3,
7 Gate 2 & 4, 8 Omitted
At 25°C free air temperature: U350 Four Matched Process NJ72L
Static Electrical Characteristics Min Typ Max Unit Test Conditions
Gate Source Breakdown Voltage V
(BR)GSS
– 25 V IG= – 1 µA, VDS= ØV
Gate Reverse Current I
GSS
– 1 nA VGS= – 15V, VDS= ØV
– 1 µA VGS= – 15V, VDS= ØV TA= 125°C
Gate Source Cutoff Voltage V
GS(OFF)
– 2 – 6 V VDS= 10V, ID= 1 nA
Gate Source Forward Voltage V
GS(F)
1VVDS= ØV, IG= 1 mA
Drain Saturation Current (Pulsed) I
DSS
24 60 mA VDS= 15V, VGS= ØV
Dynamic Electrical Characteristics
Drain Source ON Resistance r
ds(on)
50 90 Ω VGS= ØV, ID= mA f = 1 kHz
Common Source
g
fs
10 18 mS VDS= 10V, ID= 10 mA f = 1 kHz
Forward Transconductance
Common Source Output Conductance g
os
150 µS VDS= 10V, ID= 10 mA f = 1 kHz
Drain Gate Capacitance C
dgo
2.5 pF VGD= – 10V, IS= ØV f = 1 MHz
Gate Source Capacitance C
sgo
5pFVGS= – 10V, ID= ØV f = 1 MHz
(Conversion Gain) G
c
4dB
VDS= 20V, VGS= 1/2 V
GS(OFF)
f = 100 MHz
RD= 1,700 Ω
Noise Figure NF 7 dB
VDS= 20V, VGS= 1/2 V
GS(OFF)
f = 100 MHz
RD= 1,700 Ω
Saturation Drain Current Ratio I
DSS
/ I
DSS
0.9 1 VDS= 15V, VDS= ØV
Gate Source Cutoff Voltage Ratio V
GS(OFF)
/ V
GS(OFF)
0.9 1 VDS= 15V, ID= 1 nA
Common Source
g
fs
/ g
fs
0.9 1 VDS= 15V, ID= 10 mA f = 1 kHz
Forward Transconductance
Differential Output Conductance Y
os
/ Y
os
0.9 1 VDS= 15V, ID= 10 mA f = 1 kHz
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1000 N. Shiloh Road, Garland, TX 75042
(972) 487-1287 FAX (972) 276-3375
www.interfet.com
Databook.fxp 1/13/99 2:09 PM Page B-69
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