Datasheet tza3034 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TZA3034

SDH/SONET STM1/OC3
postamplifier

Product specification
Supersedes data of 1999 Mar 16
File under Integrated Circuits, IC19

1999 Nov 03

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

FEATURES

• PincompatiblewiththeNE/SA5224andNE/SA5225but
with extended power supply range and less external
component count

• Wideband operation from 1.0 kHz to 150 MHz typical

• Applicable in 155 Mbits/s SDH/SONET receivers

• Single supply voltage from 3.0 to 5.5 V

• Positive Emitter Coupled Logic (PECL) compatible data

outputs

• Programmable input signal level detection which can be
adjusted using a single external resistor

• On-chip DC offset compensation without external
capacitor.

ORDERING INFORMATION

TYPE

NUMBER

TZA3034T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
TZA3034TT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
TZA3034U − bare die in waffle pack carriers; die dimensions 1.55 × 1.55 mm −

NAME DESCRIPTION VERSION

APPLICATIONS

• Digital fibre optic receiver in short, medium and long
haul optical telecommunications transmission systems
or in high speed data networks

• Wideband RF gain block.

GENERAL DESCRIPTION

The TZA3034 is a high gain limiting amplifier that is
designed to process signals from fibre optic preamplifiers
like the TZA3033. It is pin compatible with the NE/SA5224
and NE/SA5225 but with extended power supply range,
and needs less external components. Capable of
operating at 155 Mbits/s, the chip has input signal level
detection with a user-programmable threshold. The data
and level detection status outputs are differential outputs
for optimum noise margin and ease of use.

PACKAGE

1999 Nov 03 2

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

BLOCK DIAGRAM

ref

TEST

2
(2, 10, 15, 21, 26)

4 (7)
5 (8)

16 (30)

15 (29)

AGND V

A1 A2 A3

1 kΩ

(3, 4, 6, 9)
3

BAND GAP

REFERENCE

(1, 14)
1

SUB

DC-OFFSET

COMPENSATION

RECTIFIER

CCA

handbook, full pagewidth

DIN

DINQ

RSET

V

The numbers in brackets refer to the pad numbers of the bare die version.

Fig.1 Block diagram.

(11, 12)
6

25 kΩ

(19, 20, 22, 25)11(27, 28)

(13)
7

CF

DGND V

TZA3034

A4

CCD

(24) 13
(23) 12

(16) 8

(18) 10

(17) 9

14

DOUT
DOUTQ

JAM

ST
STQ

MGR281

handbook, halfpage

SUB

TEST

AGND

DIN

DINQ

V

CCA

CF

JAM

1
2
3
4

TZA3034T

5
6
7
8

MGR282

16
15
14
13
12
11
10

9

RSET
V

ref

V

CCD

DOUT
DOUTQ
DGND
ST
STQ

Fig.2 Pin configuration of TZA3034T.

1999 Nov 03 3

handbook, halfpage

Fig.3 Pin configuration of TZA3034TT.

SUB

TEST

AGND

DIN

DINQ

V

CCA

CF

JAM

1
2
3
4

TZA3034TT

5
6
7
8

MBK997

16
15
14
13
12
11
10

9

RSET
V

ref

V

CCD

DOUT
DOUTQ
DGND
ST
STQ

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

PINNING

SYMBOL

PIN

TZA3034T

TZA3034TT

PAD

TZA3034U

TYPE

(1)

DESCRIPTION

SUB 1 1, 14 S substrate pin; must be at the same potential as pin AGND
TEST 2 2, 10, 15,

− for test purpose only; to be left open in the application

21, 26
AGND 3 3, 4, 6, 9 S analog ground; must be at the same potential as pin DGND
DIN 4 7 I differential input; complementary to pin DINQ; DC bias level is set

internally at approximately 2.1 V

DINQ 5 8 I differential input; complementary to pin DIN; DC bias level is set

internally at approximately 2.1 V

V

CCA

6 11, 12 S analog supply voltage; must be at the same potential as pin V

CCD

CF 7 13 A input for connection of capacitor to set time constant of leveldetector

input filter (optional); the capacitor should be connected between
V

and pin CF

CCA

JAM 8 16 I PECL-compatible input; controls the output buffers,

pins DOUTand DOUTQ; when a LOW signal is applied, the output
bufferswill follow the input signal; when a HIGH signal is applied, the
output buffers will latch into LOW and HIGH states respectively;
when not connected, pin JAM is actively pulled LOW

STQ 9 17 O PECL-compatible status output of the input signal level detector;

when the input signal is below the user-programmed threshold level,
this output is HIGH; complementary to pin ST

ST 10 18 O PECL-compatible status output of the input signal level detector;

when the input signal is below the user-programmed threshold level,
this output is LOW; complementary to pin STQ

DGND 11 19, 20, 22,

S digital ground; must be at the same potential as pin AGND

25

DOUTQ 12 23 O PECL-compatible differential output; this pin will be forced into a

HIGH condition when pin JAM is HIGH; complementary to pin DOUT

DOUT 13 24 O PECL-compatible differential output; this pin will be forced into a

LOW condition when pin JAM is HIGH; complementary to

pin DOUTQ
V
V

CCD
ref

14 27, 28 S digital supply voltage; must be at the same potential as V

CCA

15 29 O band gap reference voltage; typical value is 1.2 V; internal series

resistor of 1 kΩ
RSET 16 30 A input signal level detector threshold setting; nominal DC voltage is

V

− 1.5 V;threshold level is set by connecting an external resistor

CCA

between V

and pin RSET or by forcing a current into pin RSET;

CCA

default value for this resistor is 180 kΩ which corresponds with

approximately 4 mV (p-p) differential input signal
n.c. − 5, 31, 32 − not connected

Note

1. Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.

1999 Nov 03 4

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

FUNCTIONAL DESCRIPTION

The TZA3034 accepts up to 155 Mbits/s SDH/SONET
data streams, with amplitudes from2 mV up to 1.5 V (p-p)
single-ended. The input signal will be amplified andlimited
to differential PECL output levels (see Fig.1).

The input buffer A1 presents an impedance of
approximately 4.5 kΩ to the data stream on the inputs
pin DIN and pin DINQ. The input can be used both
single-ended and differential, but differential operation is
preferred for better performance.

Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3034, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.

An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL outputs,
pins ST and STQ. This flag can also be used to prevent
the PECL outputs pins DOUT and DOUTQ from reacting
to noise in the absence of a valid input signal, by
connecting pin STQ to pin JAM. This guarantees that data
willonly be transmitted when the input signal-to-noise ratio
is sufficient for low bit error rate system operation.

PECL logic

The logic level symbol definitions for PECL are shown in
Fig.4.

Input biasing

The inputs, pins DIN and DINQ, are DC biased at
approximately 2.1 V by an internal reference generator
(see Fig.5). The TZA3034 can be DC coupled, but
AC coupling is preferred. In case of DC coupling, the
driving source must operate within the allowable input
signal range (1.3 V to V

). Also a DC offset voltage of

CCA

more than a few millivolts should be avoided, since the
internal DC offset compensation circuit has a limited
correction range.

If AC coupling is used to remove any DC compatibility
requirement, the coupling capacitors must be large
enough to pass the lowest input frequency of interest.
For example, 1 nF coupling capacitors react with the
internal 4.5 kΩ input bias resistors to yield a lower −3dB
frequency of 35 kHz. This then sets a limit on the
maximum number of consecutive pulses that can be
sensed accurately at the system data rate. Capacitor
tolerance and resistor variation must be included for an
accurate calculation.

DC-offset compensation

A control loop connected between the inputs of buffer A3
andamplifier A1 (see Fig.1) will keep theinputof buffer A3
at its toggle point in the absence of any input signal.
Because of the active offset compensation which is
integrated in the TZA3034, no external capacitor is
required. The loop time constant determines the lower
cut-off frequency of the amplifier chain, which is set at
approximately 850 Hz.

Input signal level detection

The TZA3034 allows for user-programmable input signal
leveldetectionand can automatically disable the switching
of the PECL outputs if the input signal is below a set
threshold. This prevents the outputs from reacting to noise
in the absence of avalid input signal, and insures that data
will only be transmitted when the signal-to-noise ratio of
the input signal is sufficient for low bit-error-rate system
operation.ComplementaryPECLflags(pins ST and STQ)
indicate whether the input signal is above or below the
programmed threshold level.

The input signal is amplified and rectified before being
compared to a programmable threshold reference. A filter
isincluded to prevent noise spikes from triggeringthe level
detector. This filter has a nominal 1 µs time constant and
additional filtering can be achieved by using an external
capacitor between V

and pin CF (the internal driving

CCA

impedance nominally is 25 kΩ). The resultant signal is
then compared to a threshold current through pin RSET.
This current can be set by connecting an external resistor
between V

and pin RSET, or by forcing a current into

CCA

pin RSET (see Fig.6).

1999 Nov 03 5

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

The relationship between the threshold current and the
detected input voltage is approximately:

I

RSET

0.0018 V

–()A[]×=

DINVDINQ

(1)

In the formulas (1) and (3), the voltage on pin DIN and
pin DINQ is measured as peak-to-peak value.

Since the voltage on pin RSET is held constant at 1.5 V
below V

I

RSET

, the current flowing into this pin will be:

CCA

1.5
A[]=

------------­R

ADJ

(2)

Combining these two formulas results in a generalformula
to calculate R

R

ADJ

--------------------------------------- -

for a given input signal level detection:

ADJ

830

V

–()

DINVDINQ

Ω[]=

(3)

Example: Detection should occur if the differential voltage
of the input signals drops below 4 mV (p-p). In this case, a
reference current of 0.0018 × 0.004 = 7.2 µA should flow
into pin RSET. This can be set using a current source or
simply by connecting a resistor of the appropriate value.
The resistor must be connected between V

CCA

and

pin RSET. In this example the value would be:

R

ADJ

830

-------------- -

0.004

207.5 kΩ==

The hysteresis is fixed internally at 3 dB electrical. In the
example of above, a differential level below 4 mV (p-p) of
the input signal will drive pin ST to LOW, and an input
signal level above 5.7 mV (p-p) will drive pin ST to HIGH.

Dissipation

Since the thermal resistance from junction to ambient

of the TSSOP package is higher than the thermal

R

th(j-a)

resistance of the SO package (see Chapter “Thermal
characteristics”), the dissipation should be considered
when using the TZA3034TT version.

The formula to calculate the worst case die temperature is:

T

T

j

ambRth j a–()

+=

P×

max

(4)

where

T

= junction temperature

j

T

= ambient temperature

amb

R

= thermal resistance from junction to ambient

th(j-a)

P

= maximum power dissipation.

max

For the TZA3034T (SO package), the worst case die
temperatureTj=85+115×0.3 = 119.5 °Cwhichis below
the maximum operating temperature.

For the TZA3034TT (TSSOP package), the worst casedie
temperature Tj=85+150×0.3 = 130 °C which is higher
than the maximum operating temperature, and therefore
strongly discouraged. It is recommended to lower the
thermalresistancefromjunctiontoambient, e.g. by means
of a dedicated board layout.

However, if the ambient temperature is limited to 75 °Cor
the power supply is limited to 3.3 ±0.3 V, the junction
temperature will stay below the maximum value without
further precautions.

A function is provided to automatically disable the signal
transmission when the chip senses that the input signal is
below the programmed threshold level. This function can
be put into operation by connecting pin JAM with pin STQ.
When the input signal is below the programmed threshold
level, the data outputs are then forced to a predetermined
state (pin DOUT = LOW and pin DOUTQ = HIGH).

Response time of the input signal level detection circuit is
determined by the time constant of the input capacitors,
together with the filter time constant (1 µs internal plus the
additional capacitor at pin CF). For SDH/SONET
applications, couple capacitors of 1.5 nF are
recommended, leading to a high-pass frequency of
approximately 30 kHz and a maximum assert time of
30 µs.

1999 Nov 03 6

PECL output circuits

The output circuit of ST and STQ is given in Fig.7.
The output circuit of DOUT and DOUTQ is given in Fig.8.
Some PECL termination schemes are given in Fig.9.

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

handbook, halfpage

(1)

(2)

(1) Output signal on pins DOUT or ST; complementary to output signal (2).
(2) Output signal on pins DOUTQ or STQ; complementary to output signal (1)

Fig.4 Logic level symbol definitions for PECL outputs.

V
V

V
V

MGS812

V

CC
OH(max)
OH(min)

OL(max)
OL(min)

GND

DIN

V

4.5 kΩ

CC

2.1 V

handbook, halfpage

Fig.5 Data input circuit DIN and DINQ.

1999 Nov 03 7

DINQ

4.5 kΩ

1 mA

MGR958

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

V

RSET=VCCA

− 1.5 V.

handbook, halfpage

Fig.6 level detect input circuit RSET.

handbook, halfpage

V

LOW

V

RSET

V

CCA

V

HIGH

R

ADJ

RSET

I

RSET

V

TZA3034

MGS813

CC

ST

10 kΩ

Output STQ is complementary to output ST.

Fig.7 PECL output circuit ST and STQ.

V

handbook, halfpage

CC

105 Ω 105 Ω

9 mA

Fig.8 PECL output circuit DOUT and DOUTQ.

1999 Nov 03 8

MGS814

DOUT
DOUTQ

0.5 mA

0.5 mA

MGR247

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

handbook, full pagewidth

handbook, full pagewidth

VCC − 2 V

R1 = 50 Ω R1 = 50 Ω

V

V

I

V

IQ

V

I

V

IQ

O

Zo = 50 Ω

V

OQ

VCC = 3.3 V

R1 = 127 Ω

V

O

Zo = 50 Ω

V

OQ

R2 = 82.5 Ω

GND

MGR248

R1 = 127 Ω

R2 = 82.5 Ω

MGR249

handbook, full pagewidth

V

V

I

V

IQ

O

Zo = 50 Ω

V

OQ

Fig.9 PECL output termination schemes.

1999 Nov 03 9

VCC = 5.0 V

R1 = 83.3 Ω

R2 = 125 Ω

GND

R1 = 83.3 Ω

R2 = 125 Ω

MGR250

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134.

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

V

n

I

n

P

tot

T

stg

T

j

T

amb

supply voltage −0.5 +6 V
DC voltage

pins DIN, DINQ, CF, JAM and RSET −0.5 V
pins STQ, ST, DOUTQ and DOUT V
pin V

ref

− 2VCC+ 0.5 V

CC

−0.5 +3.2 V

+ 0.5 V

CC

DC current

pins DIN, DINQ, CF and JAM −1+1mA
pins STQ, ST, DOUTQ and DOUT −25 +10 mA
pin V

ref

−2 +2.5 mA

pin RSET −2+2mA
total power dissipation − 300 mW
storage temperature −65 +150 °C
junction temperature − 150 °C
ambient temperature −40 +85 °C

HANDLING

This device is ESD sensitive and should be handled with care. Precautions should be taken to avoid damage through
electrostatic discharge. This is particularly important during assembly and handling of the bare die. Additional safety can
be obtained by bonding the V

and GND pads first, the remaining pads may then be bonded to their external

CC

connections in any order.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITION VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient note 1

SO16 package 115 K/W

TSSOP16 package 150 K/W

Note

1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single-sided
57 × 57 × 1.6 mmFR4 epoxy printed-circuit board with 35 µm thickcoppertraces. The measurements are performed
in still air.

1999 Nov 03 10

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

CHARACTERISTICS

For typical values T
temperature range and supply voltage range; all voltages are measured with respect to ground; unless otherwise
specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V
I

CCD

I

CCA

P
T
T

CC

tot
j
amb

supply voltage 3 3.3 5.5 V
digital supply current notes 1 and 2 − 18 31 mA
analog supply current note 2 − 15 24 mA
total power dissipation notes 1 and 2 − 110 300 mW
junction temperature −40 − +125 °C
ambient temperature −40 +25 +85 °C

Input signal pins DIN and DINQ

V

i(se)(p-p)

single-ended input signal
voltage (peak-to-peak)

V

i(dif)(p-p)

differential input signal voltage
(peak-to-peak)

V

 absolute input signal voltage 1.3 2.1 V

I

V

IO(eq)

equivalent input signal offset
voltage

V

IO(cor)

R

i

C

i

V

n(i)(rms)

input offset voltage correction note 4; positive −3−mV

input resistance single-ended 2.9 4.5 7.6 kΩ
input capacitance single-ended; note 5 −−2.5 pF
equivalent input RMS noise

voltage

Input signal level detect pin RSET

I

RSET

V

RSET

V

th(p-p)

reference current notes 5 and 7 5 − 60 µA
reference voltage referred to V
threshold adjusting range

(single-ended and

peak-to-peak)
hys hysteresis electrically measured 236dB
R

F

t

F

filter resistance 14 25 41 kΩ

filter time constant CF = 0; note 5 0.5 1.0 2.0 µs

PECL output pins DOUT and DOUTQ

V

OL

V

OH

t

r

t

f

t

PWD

f

−3dB(l)

f

−3dB(h)

LOW-level output voltage note 8 VCC− 1.84 − VCC− 1.6 V

HIGH-level output voltage note 8 VCC− 1.1 − VCC− 0.9 V

rise time 20% to 80%; note 5 − 1.5 2.2 ns

fall time 80% to 20%; note 5 − 1.5 2.2 ns

pulse width distortion note 5 −−0.3 ns

low frequency −3 dB point − 0.85 1.5 kHz

high frequency −3 dB point − 150 − MHz

=25°C and VCC= 3.3 V; minimum and maximum values are valid over the entire ambient

amb

note 3 0.002 − 1.5 V

note 3 0.004 − 3.0 V

CCA

−−50 µV

note 4; negative −−3−mV

notes 5 and 6 − 40 60 µV

CCA

Vi= 155 Mbit/s PRBS

− 1.65 V

CCA

2 − 12 mV

CCA

− 1.5 V

CCA

V

27− 1 sequence;
note 5

V

− 1.4 V

1999 Nov 03 11

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

PECL output pins ST and STQ

V

OL

V

OH

C

L

PECL input pin JAM

V

IL

V

IH

I

I(JAM)

Reference voltage output pin V

V

ref

Notes

1. PECL outputs (pins DOUT, DOUTQ, ST and STQ) are not connected.

2. Maximum currents are specified at Tj= 125 °C, VCC= 5.5 V and worst case processing.

3. 2 mV (p-p) single-ended is the minimum input signal to achieve full clipping of the output signal. Typical an input
signal of 0.5 mV (p-p) single-ended results in a Bit Error Rate (BER) of less than 10

4. If the input is DC coupled, the preceding amplifier’s output offset voltage should not exceed these limits, in order to
avoid malfunctioning of the DC offset compensation circuit.

5. Specifications guaranteed by design and characterisation. Each device is tested at full operating speed to guarantee
RF functionality.

LOW-level output voltage note 8 VCC− 1.84 − VCC− 1.6 V
HIGH-level output voltage note 8 VCC− 1.1 − VCC− 0.9 V
load capacitance RL= ∞−−20 pF

=1kΩ−−100 pF

R

L

R

=50Ω−−1000 pF

L

LOW-level input voltage −−V

− 1.49 V

CC

HIGH-level input voltage VCC− 1.165 −−V
JAM input current note 9 −20 − +20 µA

ref

reference voltage note 10 1.165 1.20 1.235 V

−10

.

Input RMS noise

6.

7. The reference current can be set by connecting a resistor between V

total output RMS noise

=

-------------------------------------------------------------- ­low frequency gain

and pin RSET. The corresponding input

CCA

signallevel detect range isfrom 2 to 12 mV (p-p) single-ended. SeeSection “Input signal level detection” for detailed
information.

8. RL=50Ω connected to a level of VCC− 2 V (see Fig.9).

9. Internal pull-down resistor of 500 kΩ to DGND.

10. Internal series resistor of 1 kΩ.

1999 Nov 03 12

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

TYPICAL PERFORMANCE CHARACTERISTICS

80

MGR944

Tj (°C)

50

handbook, halfpage

I

CC

(mA)

40

30

20

10

−40 0 40 120

PECL outputs not connected.
(1) VCC= 5.5 V.
(2) VCC= 3.0 V.

(1)

(2)

Fig.10 Total power supply current as function of

junction temperature.

1.5

handbook, halfpage

V

o(dif)
(V)

1.4

1.3

1.2

1.1

1.0

−40 0 40 12080

V

o(dif)=VDOUT

− V

DOUTQ

.

MGR945

Tj (°C)

Fig.11 Differential output voltage as function of

junction temperature.

1.4

handbook, halfpage

V

o(dif)

(V)

1.3

1.2

1.1

1

−3

10

V

o(dif)=VDOUT

− V

10

DOUTQ

−2

.

10

−1

V

i(dif)(p-p)

MGR946

110

(V)

Fig.12 Differential output voltage as function of

differential input voltage.

1999 Nov 03 13

2.0

handbook, halfpage

t

(ns)

1.8

1.6

1.4

1.2

1.0

−3

10

−2

10

10

−1

V

i(dif)(p-p)

MGR947

t

f

t

r

110

(V)

Fig.13 Differential output rise time and fall time as

function of differential input voltage.

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

2.0

handbook, halfpage

t

MGR948

(ns)

1.6

1.2

0.8

0.4

0

−40 0 40 120

80

Tj (°C)

Fig.14 Differential output rise time and fall time as

function of junction temperature.

50

handbook, halfpage

V

i(dif)

MGR949

(mV)

40

(1)
(2)

30

(3)

20

(4)

10

0

0 10 20 30 5040

V

i(dif)=VDIN

− V

DINQ

.

I

RSET

(µA)

(1) Input high threshold for 1 0 1 0 pattern (pin ST = HIGH).
(2) Input high threshold for 27− 1 PRBS pattern (pin ST = HIGH).
(3) Input low threshold for 1 0 1 0 pattern (pin ST = LOW).
(4) Input low threshold for 27− 1 PRBS pattern (pin ST = LOW).

Fig.15 Status detect level as function of I

RSET

.

80

MGR950

Tj (°C)

40

handbook, halfpage

V

i(dif)

(mV)

30

20

10

0

−40 0 40 120

V

i(dif)=VDIN

− V

DINQ

(1) Input high threshold for I
(2) Input low threshold for I
(3) Input high threshold for I
(4) Input low threshold for I

(1)

(2)

(3)

(4)

.

=45µA (pin ST = HIGH).

RSET

=45µA (pin ST = LOW).

RSET

=10µA (pin ST = HIGH).

RSET

=10µA (pin ST = LOW).

RSET

Fig.16 Status detect level as function of junction

temperature.

handbook, halfpage

5

hys

(dB)

4

3

(1)

(2)

2

1

0

0

10 20 30 5040

I

RSET

(µA)

(1) 1 0 1 0 pattern.
(2) 27− 1 PRBS pattern.

Fig.17 Status detect hysteresis as function of

I

.

RSET

MGR951

1999 Nov 03 14

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

handbook, halfpage

4

hys

(dB)

3

(1)

(2)

2

1

0

−40 0 40 120

(1) I
(2) I

RSET
RSET

=10µA.
=45µA.

80

Tj (°C)

Fig.18 Status detect hysteresis as function of

junction temperature.

MGR952

0.003

handbook, halfpage

Ratio
(A/V)

0.002

(1)

(2)

0.001

0

0

=

Ratio

7

(1) 2

− 1 PRBS pattern.

10 20 30 5040

I

RSET

-------------­V

idif()

where V

= input low threshold (pin ST = LOW).

i(dif)

(2) 1 0 1 0 pattern.

Fig.19 Status detect ratio as function of I

I

RSET

MGR953

(µA)

RSET

.

0.3

handbook, halfpage

t

PWD

(ns)

0.2

0.1

0

−3

10

−2

10

10

Fig.20 Pulse Width Distortion (t

differential input voltage.

−1

MGR954

110

V

(V)

i(dif)(p-p)

) as function of

PWD

1.55

handbook, halfpage

V

RSET

(V)

1.53

1.51

1.49

−40 0 40 120

V

RSET=VCCA

(1) VCC= 5.5 V.
(2) VCC= 3.0 V.

Fig.21 V

(1)

(2)

80

Tj (°C)

− 1.5 V.

as function of junction temperature.

RSET

MGR955

1999 Nov 03 15

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

handbook, full pagewidth

MGR942

200 mV/div

Fig.22 Differential output waveform with 4 mV differential input voltage.

handbook, full pagewidth

200 mV/div

Fig.23 Differential output waveform with 2 V differential input voltage.

1999 Nov 03 16

MGR943

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

APPLICATION INFORMATION

handbook, full pagewidth

100 nF

V

6

1.5 nF
DIN

1.5 nF

DINQ

The numbers in brackets refer to the pad numbers of the bare die version.

(11, 12)

4 (7)

5 (8)

(3, 4, 6, 9)

3

AGND

CCA

(1, 14)

1

16

(30)

SUB

180 kΩ

RSET

TZA3034

(16)

8

JAM

Fig.24 Application diagram.

V

(13)

CC

7

(17)

9

CF

STQ

V

ref

15

(29)

(19, 20, 22, 25)

(18)

10

ST

V

14

(27, 28)

(24) 13

(23) 12

11

DGND

CCD

100 nF

DOUT

DOUTQ

1 kΩ

50 Ω 50 Ω

MGR284

data outdata in

level detect
status

VCC − 2 V

1999 Nov 03 17

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1999 Nov 03 18

V

CC

width

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

10 nF

DREF

IPhoto

64.4 nH

64.4 nH

680 nF

100 Ω

1.5 nF

1.5 nF

4.5
pF

DIN

DINQ

100 nF

(11, 12)

4 (7)

5 (8)

(3, 4, 6, 9)

3

AGND

135 kΩ

CCA

(1, 14)

1

16

(30)

SUB

RSET

(16)

8

(13)

JAM

V

6

(1) (1) (1)

22 nF

V

CC

8

1

TZA3033T TZA3034

3

2

GND4GND5GND

OUTQ

7

31 pF

OUT

6

noise filter:
1-pole, 100 MHz

29.2
pF

optional noise filter:
3-pole, 120 MHz Bessel

7

(17)

CF

9

STQ

V

ref

15

(29)

(19, 20, 22, 25)

(18)

10

ST

V

14

(27, 28)

(24) 13

(23) 12

11

DGND

CCD

100 nF

DOUT

DOUTQ

1 kΩ

50 Ω 50 Ω

MGR285

data out

level detect
status

VCC − 2 V

(1) Ferrite bead e.g. Murata BLM10A700S.
The numbers in brackets refer to the pad numbers of the bare die version.

Fig.25 STM1/OC3 receiver using the TZA3033T and TZA3034.

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

BONDING PADS

COORDINATES

(1)

SYMBOL PAD

XY

SUB 1 −235.7 +647.8
TEST 2 −392.8 +647.8
AGND 3 −532.8 +647.8
AGND 4 −647.8 +507.1
n.c. 5 −647.8 +350.0
AGND 6 −647.8 +210.0
DIN 7 −647.8 +70.0
DINQ 8 −647.8 −70.0
AGND 9 −647.8 −210.0
TEST 10 −647.8 −350.0
V
V

CCA
CCA

11 −647.8 −507.1

12 −532.8 −647.8
CF 13 −392.8 −647.8
SUB 14 −235.7 −647.8
TEST 15 −78.6 −647.8
JAM 16 +61.4 −647.8
STQ 17 +218.5 −647.8
ST 18 +375.6 −647.8
DGND 19 +532.7 −647.8
DGND 20 +647.8 −507.1
TEST 21 +647.8 −350.0
DGND 22 +647.8 −210.0
DOUTQ 23 +647.8 −70.0
DOUT 24 +647.8 +70.0
DGND 25 +647.8 +210.0
TEST 26 +647.8 +350.0
V
V
V

CCD
CCD
ref

27 +647.8 +507.1

28 +532.7 +647.8

29 +392.7 +647.8
RSET 30 +235.6 +647.8
n.c. 31 +78.5 +647.8
n.c. 32 −78.6 +647.8

Note

1. The x and y coordinates represent the position of the
centre of the pad with respect to the centre of the die
(see Fig.26).

1999 Nov 03 19

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

handbook, full pagewidth

(1) Typical value.

1.55
mm

AGND 4

n.c.

AGND

DIN

(1)

DINQ

AGND 9

TEST 10

V

CCA

AGND2TEST1SUB32n.c.31n.c.30RSET29V

3

5
6
7
8

x

0

0
y

TZA3034U

11

12

CCA

V

13CF14

SUB

15

1.55

TEST

(1)

16

mm

ref

CCD

V

28

V

27

26
25
24
23
22

20

17

18ST19

JAM

STQ

DGND

MGR283

CCD

TEST
DGND
DOUT
DOUTQ
DGND
TEST21

DGND

Fig.26 Bonding pad locations of TZA3034U.

Table 1 Physical characteristics of bare die

PARAMETER VALUE

Glass passivation 2.1 µm PSG (PhosphoSilicate Glass) on top of 0.65 µm oxynitride
Bonding pad dimension minimum dimension of exposed metallization is 90 × 90 µm (pad size = 100 × 100 µm)
Metallization 1.22 µm W/AlCu/TiW
Thickness 380 µm nominal
Size 1.55 × 1.55 mm (2.4 mm

2

)
Backing silicon; electrically connected to GND potential through substrate contacts
Attache temperature <440 °C; recommended die attache is glue
Attache time <15 s

1999 Nov 03 20

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

PACKAGE OUTLINES

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

y

Z

16

pin 1 index

1

D

c

9

A

2

A

1

8

e

w M

b

p

E

H

E

detail X

A

X

v M

A

Q

(A )

L

p

L

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE

VERSION

SOT109-1

A

max.

1.75

0.069

A1A2A

0.25

1.45

0.10

1.25

0.010

0.057

0.004

0.049

IEC JEDEC EIAJ

076E07S MS-012AC

0.25

0.01

b

3

p

0.49

0.25

0.36

0.19

0.0100

0.019

0.0075

0.014

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

10.0

4.0

3.8

0.16

0.15

1.27

0.050

9.8

0.39

0.38

REFERENCES

1999 Nov 03 21

eHELLpQZywv θ

1.05

0.041

1.0

0.4

0.039

0.016

0.7

0.25

0.6

0.028

0.01 0.004

0.020

EUROPEAN

PROJECTION

0.25 0.1

0.01

0.7

0.3

0.028

0.012

ISSUE DATE

95-01-23
97-05-22

o

8

o

0

6.2

5.8

0.244

0.228

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

D

c

y

Z

16

pin 1 index

9

A

2

18

w M

b

e

p

A

1

E

H

E

L

detail X

SOT403-1

A

X

v M

A

Q

(A )

3

A

θ

L

p

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

A

max.

0.15

mm

1.10

OUTLINE
VERSION

SOT403-1 MO-153

0.05

0.95

0.80

IEC JEDEC EIAJ

0.25

b

3

p

0.30

0.19

0.2

0.1

(1)E(2) (1)

cD

5.1

4.5

4.3

0.65

4.9

REFERENCES

1999 Nov 03 22

eHELLpQZywv θ

6.6

6.2

0.75

0.50

0.4

0.3

EUROPEAN

PROJECTION

0.13 0.10.21.0

0.40

0.06

ISSUE DATE

94-07-12
95-04-04

o

8

o

0

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesaverybriefinsight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Nov 03 23

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

1999 Nov 03 24

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern
processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no
control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors
assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of
the die. It is the responsibility of the customer to test and qualify their application in which the die is used.

1999 Nov 03 25

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

NOTES

1999 Nov 03 26

Philips Semiconductors Product specification

SDH/SONET STM1/OC3 postamplifier TZA3034

NOTES

1999 Nov 03 27

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
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Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

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Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

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New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
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Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
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Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
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United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Uruguay: see South America
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 465012/100/03/pp28 Date of release: 1999 Nov 03 Document order number: 9397 750 06334