Datasheet tza3013a, tza3013b DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TZA3013A; TZA3013B

SDH/SONET STM16/OC48
transimpedance amplifier

Objective specification
File under Integrated Circuits, IC19

2000 Jun 19

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48

TZA3013A; TZA3013B

transimpedance amplifier

FEATURES

• Low equivalent input noise, typically 8 pA/√Hz

• Wide dynamic range, typically 6 µA to 1.7 mA (p-p)

• Differential transimpedance of 4 kΩ

• Bandwidth from DC to 1.9 GHz

• Differential outputs

• On-chip Automatic Gain Control (AGC)

• No external components required

• Single supply voltage 3.3 V

• Bias voltage for PIN diode

• Remains linear up to 1.7 mA (p-p) input current

(unclipped)

• Switched output polarity available (types A and B).

ORDERING INFORMATION

TYPE

NUMBER

TZA3013AHL LQFP32 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1
TZA3013AU − bare die in waffle pack carriers; die dimensions 0.810 × 1.230 mm −
TZA3013BU − bare die in waffle pack carriers; die dimensions 0.810 × 1.230 mm −

NAME DESCRIPTION VERSION

APPLICATIONS

• Digital fibre optic receiver in short, medium and long
haul optical telecommunications transmission systems
or in high speed data networks

• Wide-band RF gain block.

GENERAL DESCRIPTION

The TZA3013 is a transimpedance amplifier with AGC,
designed to be used in STM16/OC48 fibre-optic links.
It amplifies the current generated by a photo detector
(PIN diode or avalanche photodiode) and converts it to a
differential output voltage.

PACKAGE

2000 Jun 19 2

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

BLOCK DIAGRAM

handbook, full pagewidth

100 pF

DREF

GND

V

CC

2 (1)

4 (2)

IN

1, 7 to 9, 15 to 19,
22 to 25, 31, 32

250

Ω

GNDA GNDD

GAIN

CONTROL

low noise

amplifier

AGC PILOT

10 (4) 27 (12)

TZA3013AHL

TZA3013AU

5 (3)(7, 8) (10)

INQ

PEAK

DETECTOR

single-ended to

differential converter

BIAS

SOURCE

TZA3013A; TZA3013B

V

CC

Ω

2 kΩ

2 kΩ

TESTD

30 (15)

29 (14)
28 (13)

13 (6)
12 (5)

26 (11)

OUTSENSE
OUT

OUTQ
OUTQSENSE

MGT099

V

CC

50Ω50

20 (9)

TESTC

The numbers in brackets refer to the pad numbers of the bare die version.

Fig.1 Block diagram of TZA3013AHL and TZA3013AU.

handbook, full pagewidth

100 pF

DREF

V

CC

250

Ω

1

2

IN

GAIN

CONTROL

low noise

amplifier

AGC PILOT

412

PEAK

DETECTOR

TZA3013BU

single-ended to

differential converter

BIAS

SOURCE

37, 8 10

V

CC

50Ω50

9

Ω

V

2 kΩ

2 kΩ

CC

11

15

5
6

13
14

OUTSENSE
OUT

OUTQ
OUTQSENSE

MGU137

GNDA GNDD

INQ

Fig.2 Block diagram of TZA3013BU (bare die only).

2000 Jun 19 3

TESTC

TESTD

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48

TZA3013A; TZA3013B

transimpedance amplifier

PINNING

SYMBOL

GND 1 −−ground ground
DREF 2 1 1 analog

n.c. 3 −−n.c. not connected
IN 4 2 2 input current input; anode of PIN diode should

INQ 5 3 3 input decision level adjust input; note 1
n.c. 6 −−n.c. not connected
GND 7 −−ground ground
GND 8 −−ground ground
GND 9 −−ground ground
AGC 10 4 4 analog

n.c. 11 −−n.c. not connected
OUTQSENSE 12 5 14 analog

OUTQ 13 6 13 output data output; compliment of OUT
n.c. 14 −−n.c. not connected
GND 15 −−ground ground
GND 16 −−ground ground
GND 17 −−ground ground
GND 18 −−ground ground
GND 19 −−ground ground
TESTC 20 9 9 input test input; not used in the application
n.c. 21 −−n.c. not connected
GND 22 −−ground ground
GND 23 −−ground ground
GND 24 −−ground ground
GND 25 −−ground ground
TESTD 26 11 11 input test input; not used in the application
PILOT 27 12 12 analog

OUT 28 13 6 output data output; compliment of OUTQ; note 2

PIN

TZA3013AHL

PAD

TZA3013AU

PAD

TZA3013BU

TYPE DESCRIPTION

bias voltage output for PIN diode; connect

output

output

output

output

cathode of PIN diode to this pin

be connected to this pin; note 1

AGC voltage

data sense output for OUTQ; for test
purposes

pilot tone detection current output

2000 Jun 19 4

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48

TZA3013A; TZA3013B

transimpedance amplifier

SYMBOL

PIN

TZA3013AHL

OUTSENSE 29 14 5 analog

V

CC

30 15 15 supply supply voltage
GND 31 −−ground ground
GND 32 −−ground ground
GNDA − 7 7 ground analog ground
GNDA − 8 8 ground analog ground
GNDD − 10 10 ground digital ground

Notes

1. DC bias voltage = 0.86 V.

2. This pin goes HIGH when current flows into pin IN.

PAD

TZA3013AU

PAD

TZA3013BU

TYPE DESCRIPTION

data sense output for OUT; for test

output

purposes

handbook, full pagewidth

GND

DREF

n.c.

INQ

n.c.
GND
GND

CC

GND

GND
32

1
2
3
4

IN

5
6
7
8

9

GND

V

31

30

TZA3013AHL

11

10

n.c.

AGC

OUT

OUTSENSE
29

28

12

13

OUTQ

OUTQSENSE

PILOT
27

14
n.c.

TESTD
26

15

GND

GND
25

16

GND

24
23
22
21
20
19
18
17

MGT100

GND
GND
GND
n.c.
TESTC
GND
GND
GND

Fig.3 Pin configuration of TZA3013AHL.

2000 Jun 19 5

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

FUNCTIONAL DESCRIPTION

The TZA3013 is a transimpedance amplifier intended for
use in fibreopticlinks for signal recovery in STM16/OC48
applications. It amplifies the current generated by a photo
detector (PIN diode or avalanche photodiode) and
converts it to a differential output voltage.

The most important characteristics of the TZA3013 are
high receiver sensitivity and wide dynamic range. High
receiver sensitivity is achieved by minimizing
transimpedance amplifier noise.

handbook, full pagewidth

OUTSENSE

V

CC

50 Ω

2 kΩ 2 kΩ

OUT

TZA3013A; TZA3013B

The TZA3013 has a wide dynamic range to handle the
signal current generated by the PIN diode which can vary
from 6 µA to 1.7 mA (p-p). This is implemented by an
AGC loop which reduces the preamplifier feedback
resistance so that the amplifier remains linear over the
whole input range. The AGC loop hold capacitor is
integrated on-chip, so an external capacitor is not
required.

A differential amplifier converts the output of the
preamplifiertoadifferentialvoltage.Thedataoutputcircuit
is shown in Fig.4.

The logic level symbol definitions are shown in Fig.5.

50 Ω

OUTQ

OUTQSENSE

handbook, full pagewidth

V

O(max)

V

V

V

O(min)

OQH

V

OH

OQL

V

OL

16 Ω

16 Ω

Fig.4 Data output circuit.

V

OO

MGT102

V

CC

V

o(p-p)

MGR243

Fig.5 Logic level symbol definitions for data outputs OUT and OUTQ.

2000 Jun 19 6

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

PIN diode bias voltage DREF

The performance of an optical receiver is largely
determined by the combined effect of the transimpedance
amplifierand the PIN diode. Inparticular, the method used
toconnectthePIN diode to the input and the layout around
the input pin strongly influences the main parameters of a
transimpedance amplifier, such as sensitivity, bandwidth,
and PSRR. Sensitivity is most affected by the value of the
total capacitance at the input pin. Therefore, to obtain the
highest possible sensitivity requires the value of total
capacitance to be as low as possible by reducing the
capacitanceofthePIN diode and the parasitics around the
input pin. To minimize parasitics, the PIN diode should be
placed as close as physically possible to the IC.
The capacitance of the PIN diode can be reduced by
making the value of reverse voltage across it as high as
possible.

The PIN diode can be connected to the input in two ways.
Figure 6 shows the PIN diode connected between
pins DREF and IN.

TZA3013A; TZA3013B

Pin DREFprovidesan easy bias voltage for the PIN diode.
The voltage at DREF is derived from VCC by a low-pass
filtercomprising internal resistor R1and external capacitor
C2 which decouples any supply voltage noise. The value
of external capacitor C2 affects the value of PSRR and
should have a minimum value of 100 pF. Increasing this
value increases the value of PSRR.

For a supply voltage of 3.3 V, the reverse voltage across
the PIN diode is 2.438 V (3.3 V − 0.862 V). It is preferable
toconnect the cathode of the PIN diodetoavoltage higher
than VCC if there is one available on the PCB, leaving
pin DREF unconnected. If a negative supply voltage is
available, the configuration shown in Fig.7 can be used.
It shouldbe noted that inthis configuration, the directionof
the signal current is reversed to that shown in Fig.6. It is
essential that the PIN diode bias voltage is correctly
filtered to achieve the highest possible level of sensitivity.

V

R1

250 Ω

CC

30

TZA3013

MGU120

handbook, halfpage

100 pF

C2

2

DREF

I

i

4IN

Fig.6 ThePIN diodeconnected between the input

and pin DREF.

V

handbook, halfpage

negative supply

2

DREF

4IN

I

i

CC

30

250 Ω

TZA3013

MGT103

Fig.7 ThePIN diodeconnected between the input

and a negative supply voltage.

2000 Jun 19 7

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

AGC

The TZA3013 transimpedance amplifier can handle input
currents from 6 µA to 1.7 mA which is equivalent to a
dynamic range of 49 dB. At low input currents, the
transimpedance must be high to obtain enough output
voltage, and the noise should be low enough to guarantee
a minimum bit error rate. At high input currents however,
the transimpedance should be low to avoid pulse width
distortion.To achieve the wide dynamic rangerequires the
gain of the amplifier to depend on the level of the input
signal. This is achieved in the TZA3013 by an AGC loop.

TheAGC loop comprises a peakdetector,a hold capacitor
and a gain control circuit. The peak detector detects the
amplitude of the signal and the hold capacitor stores it.
The hold capacitor voltage is compared to a threshold
voltage which corresponds to an input current of
50 µA (p-p). The AGC is only active when the input signal
level is larger than the threshold level and is inactive when
the input signal is smaller than the threshold level.

TZA3013A; TZA3013B

When the AGC is inactive, the transimpedance is at its
maximum value of 4 kΩ differential. When the AGC is
active, the feedback resistor value of the transimpedance
amplifier is reduced, reducing its transimpedance, to keep
the output voltage constant. The transimpedance is
regulated from 4 kΩ at low currents (Ii<50µA) to 80 Ω at
highcurrents (Ii= 1.7mA). The AGC allowsthe amplifier to
remainlinearoverthe whole input current range compared
tootherconfigurationswhichclip the large signals, such as
those using Schottky diodes, for example.

The top half of Fig.8 showsthe output voltage at pins OUT
and OUTQ (V
current (II) at a supply voltage of 3.3 V. The bottom half of
Fig.8 shows the difference between V
The output voltage changes linearly up to an input current
of50 µA.At this point and above, theAGCbecomesactive
and tries to keep the differential output voltage constant,
which is about 220 mV for a large range input current of
<1.7 mA.

OUT

and V

) as a function of DC input

OUTQ

and V

OUT

OUTQ

.

3.2

handbook, full pagewidth

V

o

(V)

3.1

3.0

2.9

2.8

300

V

o(dif)

(mV)

200

100

0

110

V

o(dif)=VOUT

− V

OUTQ

MGT104

V

OUT

VCC = 3.3 V

V

OUTQ

10

2

3

10

Ii (µA)

4

10

Fig.8 AGC characteristics.

2000 Jun 19 8

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48

TZA3013A; TZA3013B

transimpedance amplifier

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

V

n

I

n

P

tot

T

stg

T

j

T

amb

supply voltage −0.5 +3.8 V
DC voltage

pins/pads IN and INQ −0.5 +2.0 V
pins/pads OUT and OUTQ −0.5 V
pins/pads OUTSENSE and OUTQSENSE −0.5 V
pin/pad PILOT −0.5 V
pin/pad DREF −0.5 V

+ 0.5 V

CC

+ 0.5 V

CC

+ 0.5 V

CC

+ 0.5 V

CC

DC current

pins/pads IN and INQ −4.0 +4.0 mA
pins/pads OUT and OUTQ −10 +10 mA
pin/pad PILOT −0.2 +0.2 mA

pin/pad DREF −4.0 +4.0 mA
total power dissipation − 300 mW
storage temperature −65 +150 °C
junction temperature − 150 °C
ambient temperature −40 +85 °C

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see

“Handling MOS devices”

).

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th(j-s)

thermal resistance from junction to solder point 15 K/W

CHARACTERISTICS

Typical values at T

=25°C and VCC= 3.3 V; minimum and maximum values are valid over the entire ambient

j

temperature range and supply range; all voltages are measured with respect to ground; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

supply voltage 3.0 3.3 3.6 V
supply current AC coupled; RL=50Ω; without

− 26 37 mA

input signal

P

tot

T

j

T

amb

R

tr

total power dissipation VCC= 3.3 V − 85.8 134 mW
junction temperature −40 − +125 °C
ambient temperature −40 +25 +85 °C
small-signal transresistance

of the receiver

measured differentially;
AC coupled

R

= ∞ 6.6 8.4 10 kΩ

L

R

=50Ω 3.3 4.2 5.0 kΩ

L

2000 Jun 19 9

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48

TZA3013A; TZA3013B

transimpedance amplifier

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

f

−3dB(h)

I

n(tot)(rms)

PSRR power supply rejection ratio measured differentially; note 2

Automatic gain control loop: pin AGC

t

att

t

decay

I

th(AGC)(p-p)

Input: pin IN

I

i(p-p)

V

I(bias)

R

i

Data outputs: pins OUT and OUTQ

V

o(cm)

V

o(se)(p-p)

V

OO

R

o

t

r

t

f

Notes

1. Measurement performed with Ci= 0.5 pF comprising 0.4 pF (photodiode) and 0.1 pF (allowed for PCB layout).

2. PSRR is defined as the ratio of change in input current (∆Ii) corresponding to change in supply voltage (∆VCC):
PSRR

For example, a +4 mV disturbance on V
current). The value of the external capacitor connected between pins DREF and GND has a significant effect on the
value of PSRR. The specification is valid with an external capacitor of 1 nF.

high frequency −3 dB point Ci= 0.5 pF 1.7 1.9 − GHz
total integrated RMS noise

current over bandwidth

referenced to input; ∆fi= 1.8 GHz

− 425 − nA

third-order Bessel filter; note 1

f

= 100 kHz to 100 MHz −− −µA/V

i

f

= 3 GHz −− −µA/V

i

AGC attack time − 10 −µs
AGC decay time − 10 −µs
AGC threshold current

referenced to input − 50 −µA

(peak-to-peak value)

input current

−1700 − +1700 µA

(peak-to-peak value)
input bias voltage − 862 − mV
small-signal input resistance tested at 1 MHz; Ii<20µA (p-p) − 53 −Ω

common mode output

AC coupled; RL=50Ω−V

− 0.243 − V

CC

voltage
single-ended load output

voltage (peak-to-peak value)
differential output offset

AC coupled; RL=50Ω;
Ii= 100 µA (p-p)

− 110 − mV

−100 0 +100 mV

voltage
output resistance single-ended; DC tested 40 53 65 Ω
rise time 20% to 80% − tbf − ps
fall time 80% to 20% − tbf − ps

∆I

i

=

-------------- ­∆V

CC

at 10 MHz will typically add an extra tbf nA to Ii (photodiode output

CC

2000 Jun 19 10

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

TYPICAL PERFORMANCE CHARACTERISTICS

33

handbook, halfpage

I

CC

(mA)

31

29

27

25

23

21

−40

(1) VCC= 3.6 V.
(2) VCC= 3.3 V.
(3) VCC= 3.0 V.

0

40

80

MGT105

(1)

(2)

(3)

160120

Tj (°C)

31

handbook, halfpage

I

CC

(mA)

29

27

25

23

21

3.0 3.2

Tj=25°C.

TZA3013A; TZA3013B

MGT106

3.4 3.6
VCC (V)

Fig.9 Supply current as a function of the junction

temperature.

866

handbook, halfpage

V

I(bias)
(mV)

864

862

860

858

3.0 3.2

Tj=25°C.

3.4 3.6

MGT107

VCC (V)

Fig.10 Supply current as a function of the supply

voltage.

965

handbook, halfpage

V

I(bias)
(mV)

925

885

845

805

765

725

−40

(1) VCC= 3.6 V.
(2) VCC= 3.3 V.
(3) VCC= 3.0 V.

040

80

MGT108

(1)
(2)
(3)

Tj (°C)

160120

Fig.11 Input bias voltage as a function of the

supply voltage.

2000 Jun 19 11

Fig.12 Input bias voltage as a function of the

junction temperature.

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

290

handbook, halfpage

V

o(cm)
(mV)

270

250

230

210

190

3.0 3.2

Tj=25°C.
(1) VCC− V
(2) VCC− V

OUT
OUTQ

.

.

(1)

3.4

Fig.13 Common modeoutputvoltage as a function

of the supply voltage referenced to VCC.

MGT109

(2)

VCC (V)

3.6

TZA3013A; TZA3013B

340

handbook, halfpage

V

o(cm)

(mV)

300

260

220

180

−40

(1) VCC= 3.6 V.
(2) VCC= 3.3 V.
(3) VCC= 3.0 V.

0

40

80

Fig.14 Common modeoutputvoltage as a function

of the junction temperature referenced to
VCC.

MGT110

(1)

(2)

(3)

Tj (°C)

160120

2000 Jun 19 12

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

APPLICATION AND TEST INFORMATION

handbook, full pagewidth

1 nF

V

30

DREF

2

100

pF

IN

4

TZA3013AHL

1, 7 to 9, 15 to 19,

22 to 25, 31, 32

CC

10 µH

GND

680 nF

TZA3013A; TZA3013B

V

P

transmission

OUT

28

OUTQ

13

line

Zo = 50 Ω

Zo = 50 Ω

100 nF

100 nF

R3
50 Ω

R4
50 Ω

MGT112

handbook, full pagewidth

PATTERN

GENERATOR

23

2

−1 PRBS CLOCK

23

−1 PRBS

2
DATA

Zo = 50 Ω

Fig.15 Application diagram.

NETWORK ANALYZER

S-PARAMETER TEST SET

PORT 1 PORT 2

V

CC

10 nF

60 Ω

330 Ω

R

IN

OUT

TZA3013

OUTQ

GND

100 nF

100 nF

Zo = 50 Ω

SAMPLING OSC

1
2

Zo = 50 Ω

MGT113

trigger
input

Total impedance of the test circuit = ZTand is calculated by the equation
where s
Typical values: R = 330 Ω, Z

is the insertion loss of ports 1 and 2.

21

=73Ω.

IN

ZTs21RZIN+()2××=

Fig.16 Test circuit.

2000 Jun 19 13

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48

TZA3013A; TZA3013B

transimpedance amplifier

BONDING PAD LOCATIONS

SYMBOL PAD TZA3013AU PAD TZA3013BU

DREF 1 1 −440 +155
IN 2 2 −440 +10
INQ 3 3 −440 −157
AGC 4 4 −266 −255
OUTQSENSE 5 −−40 −255

− 14 −40 +255

OUTQ 6 − +116 −255

− 13 +110 +255
GNDA 7 7 +256 −255
GNDA 8 8 +398 −255
TESTC 9 9 +448 −79
GNDD 10 10 +448 +70
TESTD 11 11 +410 +255
PILOT 12 12 +260 +255
OUT 13 − +110 +255

− 6 +116 −255
OUTSENSE 14 −−40 +255

− 5 −40 −255
V

CC

15 15 −266 +255

COORDINATES

xy

(1)

Note

1. All coordinates are referenced, in µm, to the centre of the die.

2000 Jun 19 14

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

handbook, halfpage

CC

OUTSENSE

TZA3013AU

0

0

y

OUTQSENSE

OUT

OUTQ

810

µm

DREF

INQ

V

15 14 13 12 11

1

IN

x

2
3

45678

AGC

1230 µm

TZA3013A; TZA3013B

handbook, halfpage

PILOT

TESTDGNDA

10

GNDA

9

MGT101

GNDD
TESTC

810

µm

DREF

IN

INQ

CC

OUTQSENSE

TZA3013BU

0

0

y

OUTSENSE

OUTQ

OUT

V

15 14 13 12 11

1

x

2
3

45678

AGC

1230 µm

PILOT

TESTDGNDA

10

9

GNDA

GNDD
TESTC

MGT167

Fig.17 Bonding pad locations of the TZA3013AU.

Fig.18 Bonding pad locations of the TZA3013BU.

Physical characteristics of the bare die

PARAMETER VALUE

Glass passivation 0.3 µm PSG (PhosphoSilicate Glass) on top of 0.8 µm silicon nitride
Bonding pad dimension minimum dimension of exposed metallization is 90 × 90 µm (pad size = 100 × 100 µm)

except pads 2 and 3 which have exposed metallization of 80 × 80 µm

(pad size = 90 × 90 µm)
Metallization 2.8 µm AlCu
Thickness 380 µm nominal
Size 0.810 × 1.230 mm (0.996 mm

2

)
Backing silicon; electrically connected to GND potential through substrate contacts
Attach temperature <440 °C; recommended die attach is glue
Attach time <15 s

2000 Jun 19 15

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

PACKAGE OUTLINE

LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm

c

y

X

24

25

17

Z

16

E

A

TZA3013A; TZA3013B

SOT401-1

e

pin 1 index

32

1

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

1.60

A

1A2A3bp

0.15

1.5

1.3

0.25

0.05

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

w M

b

p

D

H

D

cE

0.27

0.18

0.17

0.12

9

8

Z

D

B

0 2.5 5 mm

(1) (1)(1)

D

5.1

4.9

w M

b

p

v M

v M

scale

(1)

eH

H

5.1

4.9

0.5

7.15

6.85

D

E

A

B

H

E

E

7.15

6.85

A

LL

p

0.75

1.0

0.45

A

2

A

1

detail X

Z

D

0.2

0.12 0.1

0.95

0.55

(A )

3

L

p

L

Zywv θ

E

o

0.95

7

o

0.55

0

θ

OUTLINE
VERSION

SOT401-1 136E01 MS-026

IEC JEDEC EIAJ

REFERENCES

2000 Jun 19 16

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27
00-01-19

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48
transimpedance amplifier

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesa very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wavesoldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing,stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling)vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

TZA3013A; TZA3013B

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadson four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, thepackage must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2000 Jun 19 17

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48

TZA3013A; TZA3013B

transimpedance amplifier

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

SOLDERING METHOD

WAVE REFLOW

(2)

(3)(4)
(5)

suitable

suitable
suitable

(1)

.

2000 Jun 19 18

Philips Semiconductors Objective specification

SDH/SONET STM16/OC48

TZA3013A; TZA3013B

transimpedance amplifier

DATA SHEET STATUS

DATA SHEET STATUS

Objective specification Development This data sheet contains the design target or goal specifications for

Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be

Product specification Production This data sheet contains final specifications. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at any other conditions above thosegiveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected toresult in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

PRODUCT

STATUS

DEFINITIONS

product development. Specification may change in any manner without
notice.

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofanyof these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products,and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all
data sheet limits up to the point of wafer sawing for a
periodof ninety (90) daysfrom the date ofPhilips' delivery.
If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There is no post
waffle pack testing performed on individual die. Although
the most modern processes are utilized for wafer sawing
and die pick and place into waffle pack carriers, Philips
Semiconductorshas no control of third partyprocedures in
the handling, packing or assembly of the die. Accordingly,
Philips Semiconductors assumes no liability for device
functionality or performance of the die or systems after
handling, packing or assembly of the die. It is the
responsibility of the customer to test and qualify their
application in which the die is used.

(1)

2000 Jun 19 19

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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

70

Printed in The Netherlands 403510/50/01/pp20 Date of release: 2000 Jun 19 Document order number: 9397 750 06867