1.2 W differential input/output audio power amplifier
Features
■ Differential inputs
■ Near-zero pop & click
■ 100dB PSRR @ 217Hz with grounded inputs
■ Operating range from V
■ 1.2W rail-to-rail output power @ V
THD = 1%, F = 1kHz, with 8Ω
■ 90dB CMRR @ 217Hz
■ Ultra-low consumption in standby mode (10nA)
■ Selectable standby mode (active low or active
high)
■ Ultra fast startup time: 15ms typ.
■ Available in 9-bump flip-chip (300mm bump
diameter)
■ Lead-free package
= 2.5V to 5.5V
CC
CC
load
=5V,
TS4994FC
with selectable standb y
TS4994EIJT - Flip-chip (9 bumps)
Gnd
Gnd
V
V
BypassStdby
BypassStdby
V
V
765
765
O-
O-
8
8
1
1
IN+
IN+
9
9
2
2
V
V
CC
CC
The device is equipped with common mode
feedback circu itry allowing outputs to be always
biased at V
/2 regardless of the input common
CC
mode voltage.
V
V
O+
O+
4
4
V
V
3
3
IN-
IN-
Stdby Mode
Stdby Mode
Description
The TS4994 is an audio power amplifier capable
The TS4994 is designed for high quality audio
applications such as mobile phones and requir es
few external components.
of delivering 1W of continuous RMS output power
into an 8Ω load @ 5V. Due to its differential input s,
Applications
it exhibits outstanding noise immunity.
An external standby mode control reduces the
supply current to less than 10nA. An STBY
MODE pin allows the standby to be active HIGH
or LOW. An internal thermal shutdown protection
is also provided, making the device capable of
■ Mobile phones (cellular / cordless)
■ Laptop / notebook computers
■ PDAs
■ Portable audio devices
sustaining short-circuits.
Order codes
Part numberTemperature rangePackagePackagingMarking
Supply bypass capacitor that provides power supply filtering.
Bypass capacitor that provides half supply filtering.
Feedback resistor that sets the closed loop gain in conjunction with Rin
AV= closed loop gain = R
Inverting input resistor that sets the closed loop gain in conjunction with R
Optional input capacitor making a high pass filter together with Rin.
(FCL= 1/(2πRinCin).
Figure 1.Typical application
Diff. input -
GND
Diff. Input +
Cin1
+
220nF
Cin2
+
220nF
Optional
Rin1
20k
Rin2
20k
GND
+
Cb
1u
.
feed/Rin
VCC
+
Cs
Rfeed1
20k
Vin-
3
Vin+
1
Bypass
8
ModeStdbyTS4994IJ
4
2
VCC
-
+
Standby
GND
69
GND
1u
GND
Bias
Rfeed2
20k
Vo+
Vo-
.
feed
5
7
8 Ohms
GNDGNDVCCVCC
3/35
Page 4
Absolute maximum ratings and operating conditionsTS4994FC
2 Absolute maximum ratings and operating conditions
Table 1.Absolute maximum ratings
SymbolParameterValueUnit
(2)
(1)
(3)
6V
GND to V
CC
250°C/W
V
T
T
R
P
CC
V
oper
stg
T
thja
diss
Supply voltage
Input voltage
i
Operating free air tempe rature range-40 to + 85°C
Storage temperature-65 to +150°C
Maximum junction temperature150°C
j
Thermal resistance junction to ambient
Power dissipationinternally limitedW
Human body model2kV
ESD
Machine model200V
Latch-up immunity200mA
Lead temperature (soldering, 10sec)260°C
1. All voltage values are measured with respect to the ground pin.
2. The magnitude of the input signal must never exceed V
3. The device is protected by a thermal shutdown active at 150°C.
Table 2.Operating conditions
+ 0.3V / GND - 0.3V.
CC
V
SymbolParameterValueUnit
V
CC
Supply voltage2.5 to 5.5V
Standby mode voltage input:
V
SM
Standby active LOW
Standby active HIGH
=GND
V
SM
VSM=V
CC
Standby voltage input:
V
STBY
T
SD
R
L
R
thja
1. The minimum current consumption (I
temperature range.
Device ON (VSM= GND) or device OFF (VSM=VCC)
Device OFF (V
Figure 80. THD+N vs. output powerFigure 81. THD+N vs. output power
10
RL = 8
Ω
Vcc = 2.6V
Av = 1, Cb = 0
1
BW < 125kHz
Tamb = 25°C
0.1
F=20kHz
F=1kHz
THD + N (%)
0.01
F=20Hz
1E-3
1E-30.010.1
Output Power (W)
Figure 82. THD+N vs. output powerFigure 83. THD+N vs. output power
10
RL = 16
Ω
Vcc = 5V
Av = 1, Cb = 0
1
0.1
THD + N (%)
BW < 125kHz
Tamb = 25°C
F=20kHz
F=1kHz
0.01
1E-3
1E-30.010.11
F=20Hz
Output Power (W)
Figure 84. THD+N vs. output powerFigure 85. THD+N vs. output power
10
RL = 16
Ω
Vcc = 2.6V
Av = 1, Cb = 0
1
BW < 125kHz
Tamb = 25°C
0.1
THD + N (%)
0.01
1E-3
1E-30.010.1
Output Power (W)
F=20kHz
F=1kHz
F=20Hz
21/35
Page 22
Electrical characteristicsTS4994FC
2.53.03.54.04.55.0
80
85
90
95
100
105
110
Av = 2.5
Cb = 1μF
THD+N < 0.7%
Tamb = 25°C
RL=16
Ω
RL=4
Ω
RL=8
Ω
Signal to Noise Ratio (dB)
Power Supply Voltage (V)
Figure 86. SNR vs. power supply voltage with
unweighted filter
110
RL=16
RL=4
Ω
RL=8
Ω
Ω
105
100
95
90
Av = 2.5
Signal to Noise Ratio (dB)
Cb = 1μF
85
THD+N < 0.7%
Tamb = 25°C
80
2.53.03.54.04.55.0
Power Supply Voltage (V)
Figure 88. Startup time vs. bypass capacitor
20
Tamb=25°C
15
10
Vcc=5V
Vcc=3.3V
Figure 87. SNR vs. power supply voltage with
A-weighted filter
Startup Time (ms)
5
0
0.00.40.81.21.62.0
Vcc=2.6V
Bypass Capacitor Cb ( F)
22/35
Page 23
TS4994FCApplication information
4 Application information
4.1 Differential configuration principle
The TS4994 is a monolithic full-differential input/output power amplifier. The TS4994 also
includes a common mode feedback loop that controls the output bias value to average it at
V
/2 for any DC common mode input voltage. This allows the device to always have a
CC
maximum output voltage swing, and by co nsequence, maximize the output power.
Moreover, as the load is connected differentially, compared to a single-ended topology, the
output is four times higher for the same power supply voltage.
The advantages of a full-differential amplifier are:
●Very high PSRR (power supply rejection ratio).
●High common mode noise rejection.
●Virtually zero pop without additional circuitry, giving a faster start-up time compared
with conventional single-ended input amplifiers.
●Easier interfacing with differential output audio DAC.
●No input coupling capacitors required due to common mode feedback loop.
●In theory, the filtering of the internal bias by an external bypass capacitor is not
necessary . Bu t, to reach maximum performance in all tolerance situations , it is better to
keep this option.
The main disadvantage is:
●As the differential function is directly linked to the mismatch between external resistors,
paying particular attention to this mismatch is mandatory in order to get the best
performance from the amplifier.
4.2 Gain in typical application schematic
A typical differential application is shown in Figure 1 on page 3.
In the flat region of the frequency-response curve(no C
The result of the calculation must be in the range:
If the result of the V
0.6V V
calculation is not in this range, an input coupling capacitor must be
ICM
ICMVCC
used.
Example: With V
=2.5V, Rin=R
CC
= 20k and Vic= 2V, we find V
feed
higher than 2.5V- 0.9V = 1.6V, so input coupling capacitors are required. Alternatively, you
can change the V
value.
ic
4.4 Low and high frequency response
In the low frequency region, Cin starts to have an effect. Cin forms, with Rin, a high-pass filter
with a -3dB cut-off frequency. F
is in Hz.
CL
F
CL
=
1
CR2
××π×
value, use the
ICM
××+
feed
(V)=
(V)=
0.9V–≤≤
= 1.63V. This is
ICM
)Hz(
inin
In the high-frequency region, you can limit the bandwidth by adding a capacitor (C
parallel with R
. It forms a low-pass filter with a -3dB cut-of f frequency. FCH is in Hz.
feed
=
F
CH
1
××π×
CR2
feedfeed
)Hz(
feed
) in
While these bandwidth limitations are in theory attractive, in practice, because of low
performance in terms of capacitor precision (and by consequen ce in terms of mismatching),
they deteriorate the values of PSRR and CMRR.
The influence of mismatching on PSRR and CMRR performance is discussed in more detail
in the following sections.
Example: A typical application with input coupling and feedback capacitor with F
and F
= 8kHz. We assume that the mismatching between R
CH
in1,2
and C
feed1,2
=50Hz
CL
can be
neglected. If we sweep the frequency from DC to 20kHz we observe the following with
respect to the PSRR value:
●From DC to 200Hz, the C
C
impedance is high enough to be neglected. Due to the tolerance of C
feed
impedance decreases from infinite to a finite value and the
in
in1,2
, we
24/35
Page 25
TS4994FCApplication information
must introduce a mismatch fa ctor (R
in1xCin
≠ R
in2xCin2
) that will decrease the PSRR
performance.
●From 200Hz to 5kHz, the C
compared with R
and the C
in,
impedance is low enough to be neglected when
in
impedance is high enough to be neglected as well. In
feed
this range, we can reach the PSRR performance of the TS4994 itself.
●From 5kHz to 20kHz, the C
and the C
impedance decreases to a finite value. Due to tolerance of C
feed
introduce a mismatching factor (R
impedance is low to be neglected when compared to R
in
feed1xCfeed1
≠ R
feed2xCfeed2
) that will decrease the
PSRR performance.
4.5 Calculating the influence of mismatching on PSRR
performance
For calculating PSRR performance, we consider that Cin and C
use the same kind of resistor (same tolerance) and ΔR is the tolerance value in %.
The following PSRR equation is valid for frequencies ranging from DC to about 1kHz.
The PSRR equation is (ΔR in %):
⎡
×≤
Log20PSRR
×Δ
⎢
⎣
⎤
100R
⎥
2
Δ−
)R10000(
⎦
This equation doesn't include the additional performance provided by bypass capacitor
filtering. If a bypass capacitor is added, it acts, together with the internal high output
impedance bias, as a low-pass filter, and the result is a quite important PSRR improvement
with a relatively small bypass capacitor.
= 0, the minimum PSRR is -60dB. With a 100nF bypass
b
in microFarad and F in Hz) is:
b
R 100×Δ
2
) 1F
2
2
C
b
dB()
22.2××+×Δ–
capacitor, at 100Hz the new PSRR would be -93dB.
This example is a worst case scenario, where each resistor has extreme tolerance. It
illustrates the fact that with only a small bypass capacitor, the TS4994 provides high PSRR
performance.
Note also that this is a theoretical formula. Because the TS4994 has self-generated noise,
you should consider that the highest practical PSRR reachable is about -110dB. It is
therefore unreasonable to target a -120dB PSRR.
25/35
Page 26
Application informationTS4994FC
100100010000
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Cb=0.1μF
Cb=1μF
Cb=0
20k
20
Cb=0.47μF
Vcc = 3.3V, Vripple = 200mVpp
Av = 1, Cin = 4.7μF
Δ
R/R = 0.1%, RL ≥ 8
Ω
Tamb = 25°C, Inputs = Grounded
PSRR (dB)
Frequency (Hz)
The three following g raphs show PSRR v ersus frequency and v ersus b ypass capacitor Cb in
worst-case conditions (
Figure 89. PSRR vs. frequency (worst case
conditions)
0
-10
Vcc = 5V, Vripple = 200mVpp
-20
Av = 1, Cin = 4.7μF
-30
Δ
R/R = 0.1%, RL ≥ 8
-40
Tamb = 25°C, Inputs = Grounded
-50
-60
-70
-80
PSRR (dB)
-90
-100
-110
-120
-130
-140
Cb=1μF
20
100100010000
Ω
Cb=0.1μF
Cb=0.47μF
Frequency (Hz)
Δ
R = 0.1%).
Cb=0
Figure 90. PSRR vs. frequency (worst case
conditions)
20k
Figure 91. PSRR vs. frequency (worst case
conditions)
0
-10
Vcc = 2.5V, Vripple = 200mVpp
-20
Av = 1, Cin = 4.7μF
-30
Δ
R/R = 0.1%, RL ≥ 8
Tamb = 25°C, Inputs = Grounded
-40
-50
-60
-70
-80
PSRR (dB)
-90
-100
-110
-120
-130
-140
Cb=1μF
20
100100010000
Ω
Cb=0.1μF
Cb=0.47μF
Frequency (Hz)
Cb=0
20k
26/35
Page 27
TS4994FCApplication information
100100010000
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Cb=0.1μF
Cb=1μF
Cb=0
20k
20
Cb=0.47μF
Vcc = 2.5V, Vripple = 200mVpp
Av = 1, Cin = 4.7μF
Δ
R/R ≤ 0.1%, RL ≥ 8
Ω
Tamb = 25°C, Inputs = Grounded
PSRR (dB)
Frequency (Hz)
The two followin g graphs sho w typical applications of the TS4994 wit h a random selection of
four
Δ
R/R values with a 0.1% tolerance.
Figure 92. PSRR vs. frequency with random
choice condition
0
-10
Vcc = 5V, Vripple = 200mVpp
Av = 1, Cin = 4.7μF
-20
Δ
R/R ≤ 0.1%, RL ≥ 8
-30
Tamb = 25°C, Inputs = Grounded
-40
-50
-60
-70
-80
PSRR (dB)
-90
-100
-110
-120
-130
-140
Cb=1μF
20
100100010000
Ω
Cb=0.1μF
Cb=0.47μF
Frequency (Hz)
Figure 93. PSRR vs. frequency with random
choice condition
Cb=0
20k
4.6 CMRR performance
For calculating CMRR performance, we consider that Cin and C
has no influence in the calculation of the CMRR.
We use the same kind of resistor (same tolerance) and ΔR is the tolerance value in %.
The following CMRR equation is valid for frequencies ranging from DC to about 1kHz.
The CMRR equation is (ΔR in %):
Example: With ΔR = 1%, the minimum CMRR is -34dB.
This example is a worst case scenario where each resistor has extreme tolerance. Ut
illustrates the fact that for CMRR, good matching is essential.
As with the PSRR, due to self-generated noise, the TS4994 CMRR limitation is about
-110dB.
Figure 94 and Figure 95 show CMRR versus frequency and versus bypass capacitor C
worst-case conditions (ΔR=0.1%).
have no influence. Cb
feed
⎡
Log20CMRR
×≤
⎢
×Δ
⎣
⎤
200R
2
)R10000(
Δ−
)dB(
⎥
⎦
in
b
27/35
Page 28
Application informationTS4994FC
100100010000
-60
-50
-40
-30
-20
-10
0
Cb=1μF
Cb=0
20k
20
Vcc = 2.5V
Vic = 200mVpp
Av = 1, Cin = 470μF
Δ
R/R = 0.1%, RL ≥ 8
Ω
Tamb = 25°C
CMRR (dB)
Frequency (Hz)
100100010000
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Cb=1μF
Cb=0
20k
20
Vcc = 2.5V
Vic = 200mVpp
Av = 1, Cin = 470μF
Δ
R/R ≤ 0.1%, RL ≥ 8
Ω
Tamb = 25°C
CMRR (dB)
Frequency (Hz)
Figure 94. CMRR vs. frequency (worst case
conditions)
0
Vcc = 5V
Vic = 200mVpp
-10
Av = 1, Cin = 470μF
Δ
-20
-30
CMRR (dB)
-40
-50
-60
Tamb = 25°C
20
R/R = 0.1%, RL ≥ 8
Ω
Cb=1μF
Cb=0
100100010000
Frequency (Hz)
20k
Figure 96 and Figure 97 show CMRR versus frequency for a typical application with a
random selection of four
Δ
R/R values with a 0.1% tolerance.
Figure 96. CMRR vs. frequency with random
selection condition
Figure 95. CMRR vs. frequency (worst case
conditions)
Figure 97. CMRR vs. frequency with random
selection condition
0
Vcc = 5V
-10
Vic = 200mVpp
-20
Av = 1, Cin = 470μF
Δ
-30
-40
-50
CMRR (dB)
-60
-70
-80
-90
Tamb = 25°C
20
R/R ≤ 0.1%, RL ≥ 8
Ω
Cb=1μF
Cb=0
100100010000
Frequency (Hz)
20k
4.7 Power dissipation and efficiency
Assumptions:
●Load voltage and current are sinusoidal (V
●Supply voltage is a pure DC source (V
The output voltage is:
V
out
= V
CC
)
peak
and I
out
sinωt (V)
out
)
and
28/35
I
out
=
V
out
------------ -
R
L
(A)
Page 29
TS4994FCApplication information
and
2
V
peak
-------------------- -
P
out
=
2R
(W)
L
Therefore, the average current delivered by the supply voltag e is:
Equation 1
V
peak
---------------- -
AVG
= 2
I
CC
πR
(A)
L
The power delivered by the supply voltage is:
P
supplyVCCICC
AVG
(W)⋅=
Therefore, the power dissipated by each amplifier is:
P
diss
P
supplyPout
(W)–=
Equation 2
P
diss
----------------------
π R
L
–=
P
outPout
22V
CC
and the maximum value is obtained when:
∂P
diss
----------------- = 0
∂P
out
and its value is:
Equation 3
2
maxPdiss
Vcc2
=
π
)W(
2
R
L
Note:This maximum value is only dependent on the power supply voltage and load values.
The efficiency is the ratio between the output power and the power supply:
Equation 4
P
-------------------
η =
P
supply
The maximum theoretical value is reached when V
η =
out
π
---- -
= 78.5%
4
πV
--------------------
=
peak
peak
4V
CC
= VCC, so:
The maximum die temperature allowable for the TS4994 is 125°C. However, in case of
overheating, a thermal shutdown set to 150°C, puts the TS4994 in standby until the
temperature of the die is reduced by about 5°C.
29/35
Page 30
Application informationTS4994FC
To calculate the maximum ambient temperature T
●The value of the power supply voltage, V
●The value of the load resistor, R
●The R
Example: V
value f or the package type
thja
=5V, RL=8Ω, R
CC
thja-flipchip
Using the power dissipation formula given above in Equation 3 this gives a result of:
P
T
is calculated as follows:
amb
dissmax
= 633mW
Equation 5
T
amb
Therefore, the maximum allowable value for T
T
= 125-80x0.633=62°C
amb
4.8 Decoupling of the circuit
Two capacitors are needed to correctly bypass the TS4994. A power supply bypass
capacitor C
C
has particular influence on the THD+N in the high frequency region (abov e 7kHz) and an
s
indirect influence on power supply disturbances. With a value for C
similar THD+N performance to that shown in the datasheet.
and a bias voltage bypass capacitor Cb.
s
allowable, you need to know:
amb
CC
L
= 100°C/W (100mm² copper heatsink)
125° CR
×–=
TJHAPdissmax
is:
amb
s
of 1µF, you can expect
In the high frequency region, if C
on the power supply rail are less filtered.
On the other hand, if C
more filtered.
C
has an influence on THD+N at lower frequencies, but its function is critical to the final
b
result of PSRR (with input grounded and in the lower frequency region).
4.9 Wake-up time: t
When the standby is released to put the device ON, the bypass capa cit or Cb is not charged
immediately. As C
properly until the C
time or t
and is specified in Table 3 on page 5, with Cb=1µF. During the wake-up time, the
WU
TS4994 gain is close to zero. After the wake-up time, the gain is released and set to its
nominal value.
If C
has a value other than 1µF, refer to the graph in Figure 88 on page 22 to establish the
b
wake-up time.
is directly linked to the bias of the amplifier, the bias will not work
b
voltage is correct. The time to reach this voltage is called the wake-up
b
is lower than 1µF, it increases THD+N, and disturbances
s
is higher than 1µF, the disturbances on the power supply rail are
s
WU
30/35
Page 31
TS4994FCApplication information
−
4.10 Shutdown time
When the standby command is set, the time required to put the two output stages in high
impedance and the internal circuitry in shutdown mode is a few micr oseconds.
Note:In shutdown mode, the Bypass pin and Vin+, Vin- pins are short-circuited to ground by
internal switches. This allows a quick discharge of the C
and Cin capacitors.
b
4.11 Pop performance
Due to its fully differential structure, the pop performance of the TS4994 is close to perfect.
However, due to mismatching between internal resistors R
capacitors C
, some noise might remain at startup. To eliminate the effect of mismatched
in
, R
in
, and external input
feed
components, the TS4994 includes pop reduction circuitry . With this circuitry, the TS4994 is
close to zero pop for all possible common applications.
In addition, when the TS4994 is in standb y mode, due to the h igh impedance output stage in
this configuration, no pop is heard.
4.12 Single-ended input configuration
It is possible to use the TS4994 in a single-ended input configuration. However, input
coupling capacitors are needed in this configuration. The schematic in Figure 98 shows an
example of this configuration.
Figure 98. Single-ended input typical application
VCC
+
Cs
GND
Rfeed2
20k
1u
Vo+
5
Vo-
7
8 Ohms
Ve
GND
Cin1
220nF
Cin2
220nF
Rfeed1
20k
Rin1
+
20k
Rin2
+
20k
+
Cb
1u
GND
3
Vin-
1
Vin+
8
Bypass
ModeStdbyTS4994IJ
4
GNDGNDVCCVCC
2
VCC
-
+
Bias
Standby
GND
69
GND
The component calculations remain the same, except for the gain. In single-ended input
configuration, the formula is:
R
=
Av=
SE
VV
Ve
feedOO
−+
R
in
31/35
Page 32
Package informationTS4994FC
5 Package information
In order to meet environmental requirements, STMicroelectronics offers these devices in
ECOPACK
category of second level interconnect is marke d on the pa ckage and on the inner box label,
in compliance with JEDEC Standard JESD97. The maximum ratings related t o soldering
conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics
trademark. ECOPACK specifications are available at: www.st.com
®
packages. These packages have a Lead-free second level interconnect. The
.
Flip-chip package (9 bumps)
Dimensions in millimeters unless otherwise indicated.
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely res ponsibl e fo r the c hoic e, se lecti on an d use o f the S T prod ucts and s ervi ces d escr ibed he rein , and ST as sumes no
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