Page 1
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS01 1A – APRIL 1992 – REVISED OCTOBER 1995
• Low r
DS(on)
. . . 1.3 Ω Typ
• Avalanche Energy . . . 75 mJ
• Eight Power DMOS Transistor Outputs of
250-mA Continuous Current
• 1.5-A Pulsed Current Per Output
• Output Clamp Voltage up to 45 V
• Low Power Consumption
description
The TPIC6273 is a monolithic high-voltage
high-current power logic octal D-type latch with
DMOS transistor outputs designed for use in
systems that require relatively high load power.
The device contains a built-in voltage clamp on the
outputs for inductive transient protection. Power
driver applications include relays, solenoids, and
other medium-current or high-voltage loads.
The TPIC6273 contains eight positive-edgetriggered D-type flip-flops with a direct clear input.
Each flip-flop features an open-drain power
DMOS transistor output.
When clear (CLR
inputs meeting the setup time requirements is
transferred to the DRAIN outputs on the positivegoing edge of the clock pulse. Clock triggering
occurs at a particular voltage level and is not
directly related to the transition time of the
positive-going pulse. When the clock input (CLK)
is at either the high or low level, the D input signal
has no effect at the output. An asynchronous CLR
is provided to turn all eight DMOS-transistor
outputs off.
The TPIC6273 is characterized for operation over
the operating case temperature range of –40°C
to 125°C.
) is high, information at the D
DW OR N PACKAGE
(TOP VIEW)
CLR
1
D1
2
D2
3
DRAIN1
DRAIN2
DRAIN3
DRAIN4
GND
logic symbol
CLR
CLK
D1
D2
D3
D4
D5
D6
D7
D8
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984
and IEC Publication 617-12.
†
1
11
2
3
8
9
12
13
18
19
CLR
L
H
H
H
H = high level, L = low level, X = irrelevant
4
5
6
7
8
D3
9
D4
10
R
C1
1D
FUNCTION TABLE
(each channel)
INPUTS
CLK D
X
↑
↑
L
20
19
18
17
16
15
14
13
12
11
X
H
L
X
V
CC
D8
D7
DRAIN8
DRAIN7
DRAIN6
DRAIN5
D6
D5
CLK
OUTPUT
DRAIN
H
L
H
Latched
14
15
16
17
4
5
6
7
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
DRAIN8
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
Page 2
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS01 1A – APRIL 1992 – REVISED OCTOBER 1995
logic diagram (positive logic)
4
DRAIN1
CLR
D1
CLK
D2
D3
D4
D5
1
2
11
3
8
9
12
R
1D
R
1D
R
1D
R
1D
R
1D
C1
C1
C1
C1
C1
5
6
7
14
15
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
R
13
D6
18
D7
19
D8
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1D
R
1D
R
1D
C1
C1
C1
16
17
10
DRAIN7
DRAIN8
GND
Page 3
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
V
CC
Input
25 V
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS01 1A – APRIL 1992 – REVISED OCTOBER 1995
DRAIN
45 V
12 V
GND
12 V
GND
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)
Logic supply voltage, V
Logic input voltage range, V
Power DMOS drain-to-source voltage, V
Continuous source-drain diode anode current 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-drain diode anode current 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, I
Continuous drain current, each output, all outputs on, I
Peak drain current single output, I
Single-pulse avalanche energy, E
Avalanche current, I
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs, duty cycle ≤ 2%
4. DRAIN supply voltage = 15 V , starting junction temperature (TJS) = 25°C, L = 100 mH, IAS = 1 A (see Figure 4).
†
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
DM,TA
(see Note 4) 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AS
AS
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
(see Note 2) 45 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS
T
= 25°C (see Note 3) 750 mA. . . . . . . . . . . . . . . . . . .
Dn,
A
T
= 25°C 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . .
Dn,
= 25°C (see Note 3) 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
(see Figure 4) 75 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J
DISSIPATION RATING TABLE
PACKAGE
DW 1125 mW 9.0 mW/°C 225 mW
N 1150 mW 9.2 mW/°C 230 mW
TA ≤ 25°C
POWER RATING
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DERATING FACTOR
ABOVE TA = 25°C
TA = 125°C
POWER RATING
3
Page 4
TPIC6273
I
Off-state drain current
A
L
,
D
,
F
µ
ns
R
Thermal resistance, junction-to-ambient
All 8 outputs with equal power
°C/W
POWER LOGIC OCTAL D-TYPE LATCH
SLIS01 1A – APRIL 1992 – REVISED OCTOBER 1995
recommended operating conditions over recommended operating temperature range (unless
otherwise noted)
MIN MAX UNIT
Logic supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) –1.8 1.5 A
Setup time, D high before CLK↑, tsu (see Figure 2) 10 ns
Hold time, D high after CLK↑, th (see Figure 2) 15 ns
Pulse duration, tw (see Figure 2) 25 ns
Operating case temperature, T
CC
IH
IL
C
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
V
SD
I
IH
I
IL
I
CC
I
N
DSX
r
DS(on)
Drain-source breakdown voltage ID = 1 mA 45 V
Source-drain diode forward voltage IF = 250 mA, See Note 3 0.85 1 V
High-level input current VCC = 5.5 V, VI = V
Low-level input current VCC = 5.5 V, VI = 0 –1 µA
Logic supply current IO = 0, All inputs low 15 100 µA
Nominal current
Static drain-source on-state
resistance
V
IN = ID,T
VDS = 40 V 0.05 1
VDS = 40 V, TC = 125°C 0.15 5
ID = 250 mA, VCC = 4.5 V 1.3 2
ID = 250 mA, TC = 125°C,
VCC = 4.5 V
ID = 500 mA, VCC = 4.5 V 1.3 2
DS(on)
= 0.5 V,
CC
= 85°C
C
See Notes 5, 6, and 7 250 mA
See Notes 5 and 6
and Figures 8 and 9
4.5 5.5 V
0.85 V
CC
0.15 V
CC
–40 125 °C
1 µA
2 3.2
V
V
µ
Ω
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
Propagation delay time, low-to-high-level output from CLK 625 ns
PLH
t
Propagation delay time, high-to-low-level output from CLK
PHL
t
Rise time, drain output
r
t
Fall time, drain output 400 ns
f
t
Reverse-recovery-current rise time
a
t
Reverse-recovery time
rr
NOTES: 3. Pulse duration ≤ 100 µs, duty cycle ≤ 2%
5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
θJA
DW package
N package
C
= 30 pF, I
See Figures 1, 2, and 10
IF = 250 mA, di/dt = 20 A/µs,
See Notes 5 and 6 and Figure 3
= 250 mA,
p
150 ns
675 ns
100
300
p
111
108
°
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
POWER LOGIC OCTAL D-TYPE LATCH
SLIS01 1A – APRIL 1992 – REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
TPIC6273
Word
Generator
(see Note A)
Word
Generator
(see Note A)
Word
Generator
(see Note A)
11
CLK
D
1
CLR
TEST CIRCUIT
5 V
20
V
CC
D
DUT
11
CLK
GND
TEST CIRCUIT
5 V 24 V
V
CC
DUT
GND
20
DRAIN
10
I
D
4–7,
14–17
RL = 95 Ω
Output
CL = 30 pF
(see Note B)
CLK
D
CLR
Output
Figure 1. Resistive Load Normal Operation
D
CLK
Output
CLK
10%
D
INPUT SETUP AND HOLD WAVEFORMS
CLR
DRAIN
10
I
D
4–7,
14–17
24 V
95 Ω
Output
CL = 30 pF
(see Note B)
1
50%
t
su
VOLTAGE WAVEFORMS
t
PLH
90%
t
r
SWITCHING TIMES
50%
50%
t
w
50%
t
90%
h
50%
t
PHL
10%
t
5 V
0 V
5 V
0 V
5 V
0 V
24 V
0.5 V
5 V
0 V
5 V
0 V
24 V
0.5 V
f
5 V
0 V
5 V
0 V
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 KHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS01 1A – APRIL 1992 – REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
DRAIN
Circuit
Under
Test
I
(see Note B)
t
2
t
1
V
(see Note A)
NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.25 A, where t1 = 10 µs,
GG
t2 = 7 µs, and t3 = 3 µs.
B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
F
t
3
R
G
50 Ω
TEST CIRCUIT
TP K
Driver
L = 1 mH
TP A
2500 µF
250 V
25 V
0.25 A
+
–
I
RM
I
F
0
di/dt = 20 A/µs
t
a
t
rr
CURRENT WAVEFORM
25% of I
RM
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode
5 V 15 V
20
V
1
CLR
Word
Generator
(see Note A)
†
Non-JEDEC symbol for avalanche ftime.
NOTES: A. The word generator A has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 1 A.
Energy test is defined as EAS = IAS x V
11
CLK
D
Input
TEST CIRCUIT
CC
DUT
GND
DRAIN
10
I
4–7,
14–17
(BR)DSX
0.11 Ω
D
100 mH
V
DS
x tav/2 = 75 mJ, where tav = avalanche time.
Input
I
V
DS
See Note B
D
VOLTAGE AND CURRENT WAVEFORMS
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
t
w
†
t
av
IAS = 1 A
V
(BR)DSX
MIN
5 V
0 V
= 45 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
10
4
PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
TJS = 25°C
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS01 1A – APRIL 1992 – REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
800
VCC = 5 V
700
600
2
1
0.4
AS
I – Peak Avalanche Current – A
0.2
0.1
0.1 0.2 10.4 2 104
tav – Time Duration of Avalanche – ms
Figure 5 Figure 6
of Each Output – mA
– Maximum Continuous Drain Current
D
I
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
2
1.5
500
400
300
200
100
0
012 3 45
N – Number of Outputs Conducting Simultaneously
VCC = 5 V
TA = 25°C
d = tw/t
= 1 ms/t
TA = 125°C
period
period
TA = 25°C
TA = 100°C
678
1
– Peak Drain Current – A
D
I
0.5
0
012345
N – Number of Outputs Conducting Simultaneously
d = 50%
d = 80%
Figure 7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
d = 5%
d = 10%
678
7
Page 8
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS01 1A – APRIL 1992 – REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE
ON-STATE RESISTANCE
DRAIN CURRENT
Ω
4
VCC = 5 V
3.5
See Note A
3
2.5
2
1.5
1
– Static Drain-Source On-State Resistance –r
0.5
0
DS(on)
0.25 0.5 0.75 1
ID – Drain Current – A
Figure 8 Figure 9
vs
TC = 125 °C
TC = 25 °C
TC = – 40 °C
1.25 1.5
STATIC DRAIN-SOURCE
ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
Ω
3
ID = 250 mA
T
= 125 °C
2.5
2
1.5
1
0.5
– Static Drain-Source On-State Resistance –
0
DS(on)
34567
r
C
TC = 25 °C
TC = –40 °C
VCC – Logic Supply Voltage – V
See Note A
700
600
500
400
300
Switching Time – ns
200
100
– 50 0 50 100 150
NOTE A: Technique should limit TJ – TC to 10°C maximum.
SWITCHING TIME
vs
FREE-AIR TEMPERATURE
t
r
t
PLH
ID = 250 mA
See Note A
t
f
t
PHL
TA – Free-Air Temperature – ° C
Figure 10
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...