Page 1
TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APIRL 1992 – REVISED SEPTEMBER 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
• Low r
DS(on)
. . . 1.3 Ω Typical
• Avalanche Energy...75 mJ
•Eight Power DMOS Transistor Outputs of
250-mA Continuous Current
• 1.5-A Pulsed Current Per Output
• Output Clamp Voltage at 45 V
• Four Distinct Function Modes
• Low Power Consumption
description
This power logic 8-bit addressable latch controls
open-drain DMOS transistor outputs and is
designed for general-purpose storage applications in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multifunctional device capable of storing single-line
data in eight addressable latches with 3-to-8
decoding or demultiplexing mode active-low
DMOS outputs.
Four distinct modes of operation are selectable by
controlling the clear (CLR
) and enable (G) inputs
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G
should be held high (inactive) while the
address lines are changing. In the 3-to-8 decoding
or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are
high. In the clear mode, all outputs are high and unaffected by the address and data inputs.
Separate power and logic level ground pins are provided to facilitate maximum system flexibility . Pins 1, 10, 1 1,
and 20 are internally connected, and each pin must be externally connected to the power system ground in order
to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10,
11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the
logic and load circuits.
The TPIC6259 is characterized for operation over the operating case temperature range of –40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PGND
V
CC
S0
DRAIN0
DRAIN1
DRAIN2
DRAIN3
S1
LGND
PGND
PGND
CLR
D
DRAIN7
DRAIN6
DRAIN5
DRAIN4
G
S2
PGND
DW OR N PACKAGE
(TOP VIEW)
OUTPUT OF
ADDRESSED
DRAIN
EACH
OTHER
DRAIN
INPUTS
FUNCTION
CLR G
FUNCTION TABLE
LATCH SELECTION TABLE
SELECT INPUTS DRAIN
ADDRESSED
0
1
2
3
4
5
6
7
L
L
L
L
H
H
H
H
D
HHLLH
L
L
H
Q
io
Q
io
Q
io
Q
io
H H X Memory
LLLLH
L
L
H
H
H
8-Line
Demultiplexer
L H X H H Clear
Addressable
Latch
S2 S1 S0
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Page 2
TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APIRL 1992 – REVISED SEPTEMBER 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
logic symbol
†
0
3
S0
8
S1
2
12
S2
G8
13
Z9
18
D
Z10
19
8M 0/7
9,0D
9,1D
9,2D
9,3D
9,4D
9,5D
9,6D
9,7D
10,0R
DRAIN0
4
DRAIN1
5
DRAIN2
6
DRAIN3
7
DRAIN4
14
DRAIN5
15
DRAIN6
16
DRAIN7
17
10,1R
10,2R
10,3R
10,4R
10,5R
10,6R
10,7R
G
CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Page 3
TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APIRL 1992 – REVISED SEPTEMBER 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
logic diagram (positive logic)
D
C1
CLR
S0
D
C1
CLR
S2
S1
D
G
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
4
DRAIN0
5
DRAIN1
6
DRAIN2
7
DRAIN3
14
DRAIN4
15
DRAIN5
16
DRAIN6
17
DRAIN7
1,10,11, 20
PGND
3
12
8
18
13
19
Page 4
TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APIRL 1992 – REVISED SEPTEMBER 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
V
CC
Input
LGND
PGND
DRAIN
45 V
12 V
25 V
12 V
LGND
absolute maximum ratings over the recommended operating case temperature range (unless
otherwise noted)
†
Logic supply voltage, V
CC
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, V
I
–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, V
DS
(see Note 2) 45 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-drain diode anode current 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-drain diode anode current 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, I
Dn
, T
A
= 25°C (see Note 3) 750 mA. . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, I
Dn,
T
A
= 25°C 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . .
Peak drain current single output, I
DM, TA
= 25°C (see Note 3) 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, E
AS
(see Note 4) 75 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, I
AS
(see Note 4) 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to LGND and PGND.
2. Each power DMOS source is internally connected to PGND.
3. Pulse duration ≤ 100 µs, duty cycle ≤ 2%
4. DRAIN supply voltage = 15 V , starting junction temperature, (TJS) = 25°C, L = 100 mH, IAS = 1 A (see Figure 4).
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 125°C
POWER RATING
DW 1125 mW 9.0 mW/°C 225 mW
N 1150 mW 9.2 mW/°C 230 mW
Page 5
TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APIRL 1992 – REVISED SEPTEMBER 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
recommended operating conditions over recommended operating temperature range (unless
otherwise noted)
MIN MAX UNIT
Logic supply voltage, V
CC
4.5 5.5 V
High-level input voltage, V
IH
0.85 V
CC
V
Low-level input voltage, V
IL
0.15 V
CC
V
Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) –1.8 1.5 A
Setup time, D high before G↑, tsu(see Figure 2) 10 ns
Hold time, D high after G↑, th(see Figure 2) 5 ns
Pulse duration, tw (see Figure 2) 15 ns
Operating case temperature, T
C
–40 125 °C
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
Drain-source breakdown voltage ID = 1 mA 45 V
V
SD
Source-drain diode forward voltage IF = 250 mA, See Note 3 0.85 1 V
I
IH
High-level input current VCC = 5.5 V, VI = V
CC
1 µA
I
IL
Low-level input current VCC = 5.5 V, VI = 0 –1 µA
I
CC
Logic supply current IO = 0, All inputs low 15 100 µA
I
N
Nominal current
V
DS(on)
= 0.5 V, IN = ID, T
C
= 85°C,
See Notes 5, 6, and 7
250 mA
VDS = 40 V 0.05 1
I
DSX
Off-state drain current
VDS = 40 V, TC = 125°C 0.15 5
µ
A
ID = 250 mA, VCC = 4.5 V 1.3 2
r
DS(on)
Static drain-source on-state
resistance
ID = 250 mA, TC = 125°C,
VCC = 4.5 V
See Notes 5 and 6
and Figures 8 and 9
2 3.2
Ω
ID = 500 mA, VCC = 4.5 V 1.3 2
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output from D 625 ns
t
PHL
Propagation delay time, high-to-low-level output from D
C
= 30 pF, I
= 250 mA,
140 ns
t
r
Rise time, drain output
L
,
D
,
See Figures 1, 2, and 10
650 ns
t
f
Fall time, drain output 400 ns
t
a
Reverse-recovery-current rise time
IF = 250 mA, di/dt = 20 A/µs,
100
t
rr
Reverse-recovery time
F
µ
See Notes 5 and 6 and Figure 3
300
ns
NOTES: 3. Pulse duration ≤ 100 µs, duty cycle ≤ 2%
5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
DW package
p
p
111
°
R
θJA
Thermal resistance junction-to-ambient
N package
All 8 outputs with equal power
108
°C/W
Page 6
TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APIRL 1992 – REVISED SEPTEMBER 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
5 V 24 V
V
CC
DRAIN
LGND
CLR
RL = 95 Ω
Output
D
Word
Generator
(see Note A)
0 V
5 V
0.5 V
24 V
D
G
G
DRAIN5
CLR
VOLTAGE WAVEFORMS
S0
0 V
5 V
S1
0 V
5 V
S2
0 V
5 V
5 V
5 V
0 V
0 V
0.5 V
24 V
DRAIN3
S2
S1
S0
CL = 30 pF
(see Note B)
DUT
9
3
8
12
13
19
18
2
PGND
1, 10,
11, 20
4–7,
14–17
I
D
Figure 1. Typical Operation Mode
SWITCHING TIMES
G
D
5 V
0 V
5 V
0 V
50%
Output
24 V
0.5 V
90%
10%
t
PLH
t
r
50%
90%
10%
t
PHL
t
f
5 V
0 V
50%
D
5 V
0 V
50%
50%
t
su
t
h
t
w
INPUT SETUP AND HOLD WAVEFORMS
G
5 V
24 V
DUT
V
CC
CLR
DRAIN
LGND
D
95 Ω
I
D
TEST CIRCUIT
Word
Generator
(see Note A)
G
CL = 30 pF
(see Note B)
Output
Word
Generator
(see Note A)
PGND
2
19
9 1, 10,
11, 20
13
18
4–7,
14–17
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Page 7
TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APIRL 1992 – REVISED SEPTEMBER 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
0.25 A
I
F
0
I
RM
25% of I
RM
t
a
t
rr
dl/dt = 20 A/µs
+
–
2500 µF
250 V
L = 1 mH
I
F
(see Note B)
R
G
V
GG
(see Note A)
Driver
TP A
50 Ω
Circuit
Under
Test
DRAIN
25 V
t
1
t
3
t
2
TP K
TEST CIRCUIT CURRENT WAVEFORM
NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.25 A, where
t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs.
B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode
TEST CIRCUIT
5 V
15 V
V
CC
DRAIN
LGND
CLR
L = 100 mH
V
DS
D
Word
Generator
(see Note A)
G
DUT
0.11 Ω
PGND
9
1, 10, 11, 20
t
w
t
av
IAS = 1 A
V
(BR)DSX
= 45 V
MIN
VOLTAGE AND CURRENT WAVEFORMS
Input
I
D
V
DS
See Note B
S0
S1
S2
3
8
12
19
18
13
I
D
2
4–7,
14–17
5 V
0 V
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 1 A.
Energy test level is defined as EAS = IAS × V
(BR)DSX
× tav/2 = 75 mJ.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
Page 8
TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APIRL 1992 – REVISED SEPTEMBER 1995
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
– Maximum Continuous Drain Current
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY
400
200
100
0
012345
600
700
800
678
500
300
TA = 25°C
TA = 125°C
N – Number of Outputs Conducting Simultaneously
of Each Output – mA
D
I
2
1
10
4
0.1 0.2 10.4 2 104
0.2
0.1
0.4
I – Peak Avalanche Current – A
AS
PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
tav – Time Duration of Avalanche – ms
TJS = 25°C
VCC = 5 V
TA = 100°C
Figure 5 Figure 6
1
0.5
0
012345
Maximum Peak Drain Current
678
1.5
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY
D
VCC = 5 V
TA = 25°C
d = tw/t
period
= 1 ms/t
period
d = 10%
d = 5%
d = 50%
d = 80%
N – Number of Outputs Conducting Simultaneously
I –
2
of Each Output – A
Figure 7
Page 9
TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APIRL 1992 – REVISED SEPTEMBER 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
VCC – Logic Supply Voltage – V
0
0.5
1
1.5
2
2.5
3
34567
T
C
= 125°C
ID = 250 mA
See Note A
ID – Drain Current – A
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
Ω
DS(on)
– Static Drain-Source On-State Resistance –
2
1.5
0.5
0
0.25 0.5 0.75 1
2.5
3.5
4
1.25 1.5
1
3
TC = 25°C
TC = 125°C
VCC = 5 V
See Note A
r
TC = – 40°C
Ω
DS(on)
– Static Drain-Source On-State Resistance –r
TC = 25°C
TC = –40°C
Figure 8 Figure 9
500
300
200
100
700
400
– 50 0 50 100 150
600
SWITCHING TIME
vs
FREE-AIR TEMPERATURE
Switching Time – ns
t
PHL
t
PLH
t
r
t
f
ID = 250 mA
See Note A
TA – Free-Air Temperature – °C
Figure 10
NOTE A: Technique should limit TJ – TC to 10°C maximum.
Page 10
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