Page 1
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
D
Low r
DS(on)
D
High Output Voltage . . . 60 V
D
Pulsed Current . . . 10 A Per Channel
D
Avalanche Energy Capability . . . 105 mJ
D
Input Transient Protection . . . 2000 V
. . . 0.25 Ω Typ
description
The TPIC2601 is a monolithic power DMOS array
that consists of six electrically isolated N-channel
enhancement-mode DMOS transistors
configured with a common source and open
drains. Each transistor features integrated
high-current zener diodes to prevent gate
damage in the event that an overstress condition
occurs. These zener diodes also provide up to
2000 V of ESD protection when tested using the
human-body model.
†
TI Japan only
KTC or KTD† PACKAGE
(TOP VIEW)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DRAIN6
GATE6
DRAIN5
GATE5
DRAIN4
DRAIN4
GATE4
SOURCE/GND
GATE3
DRAIN3
DRAIN3
GATE2
DRAIN2
GATE1
DRAIN1
The TPIC2601 is offered in a 15-pin PowerFLEX(KTC) package and is characterized for operation over the
case temperature range of –40°C to 125°C.
A 15-pin PowerFLEX(KTD) package is also available for TI Japan
only .
schematic
GATE3
DRAIN3
SOURCE/GND
DRAIN4
8
DRAIN1
1 3 5, 6 10, 11 13 15
Q1 Q2 Q3 Q4 Q5 Q6
GATE1
NOTE A: For correct operation, no drain terminal may be taken below GND.
2
DRAIN2
GATE2
47
DRAIN5
GATE4
912
GATE5
DRAIN6
14
GATE6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerFLEX is a trademark of Texas Intruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
Page 2
TPIC2601
D
,
DS GS
,
I
Zero-gate-voltage drain current
DS
,
A
r
Static drain-to-source on-state resistance
D
,
Ω
f = 1 MHz
See Figure 11
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
absolute maximum ratings over operating case temperature range (unless otherwise noted)
†
Drain-to-source voltage, VDS 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage, VGS –9 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, T
= 25°C 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
Pulsed drain current, each output, IOmax, TC = 25°C (see Note 1 and Figure 7) 10 A. . . . . . . . . . . . . . . . . . .
Continuous gate-to-source zener diode current, T
Pulsed gate-to-source zener diode current, T
= 25°C ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
= 25°C ±250 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
Single-pulse avalanche energy, EAS, TC = 25°C (see Figures 4 and 16) 105 mJ. . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation at (or below) T
= 25°C 1.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
Power dissipation at (or below) TC = 75°C, all outputs on 18.75 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, T
Storage temperature range, T
stg
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
V
GS(th)
V
GS(th)match
V
(BR)GS
V
(BR)SG
V
DS(on)
V
F(SD)
DSS
I
GSSF
I
GSSR
DS(on)
g
fs
C
iss
C
oss
C
rss
NOTES: 2. Technique should limit TJ – TC to 10°C maximum.
Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 60 V
Gate-to-source threshold voltage
Gate-to-source threshold voltage matching
Gate-to-source breakdown voltage IGS = 250 µA 18 V
Source-to-gate breakdown voltage ISG = 250 µA 9 V
Drain-to-source on-state voltage
Forward on-state voltage, source-to-drain
Forward gate current, drain short circuited to
source
Reverse gate current, drain short circuited to
source
Forward transconductance
Short-circuit input capacitance, common source 180 225
Short-circuit output capacitance, common
source
Short-circuit reverse transfer capacitance,
common source
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
I
= 1 mA, V
See Figure 5
ID = 2 A,
See Notes 2 and 3
IS = 2A, VGS = 0,
See Notes 2 and 3 and Figure 12
V
= 48 V,
VGS = 0
VGS = 10 V, VDS = 0 20 200 nA
VSG = 5 V, VDS = 0 10 100 nA
VGS = 10 V,
I
=2 A,
See Notes 2 and 3
and Figures 6 and 7
VDS = 15 V,
See Notes 2 and 3
and Figure 9
VDS = 25 V,
=
,
= V
VGS = 10 V,
TC = 25°C 0.05 1
TC = 125°C 0.5 10
TC = 25°C 0.25 0.3
TC = 125°C 0.4 0.5
ID = 1 A 1.3 1.95 S
VGS = 0,
1.5 2.05 2.2 V
,
0.5 0.6 V
0.85 1 V
110 138
80 100
5 40 mV
µ
pF
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
V
di/dt
100 A/
QRRTotal diod
180nC
DD
,
L
,
en
,
ns
See Figure 3
nH
R
θJC
Junction-to-case thermal resistance
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
source-to-drain diode characteristics, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
rr(SD)
resistive-load switching characteristics, TC = 25°C
t
d(on)
t
d(off)
t
r
t
f
Q
Q
Q
L
L
R
Reverse-recovery time
Delay time, VGS↑ to VDS↓ turn on 194
Delay time, VGS↓ to VDS↑ turn off
Rise time, V
Fall time, V
Total gate charge
g
Threshold gate-to-source charge
gs(th)
Gate-to-drain charge
gd
D
S
Internal drain inductance 5
Internal source inductance 5
Internal gate resistance 500 Ω
g
e charge
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
= 25 V, R
t
= 10 ns,
DS
DS
dis
VDD = 48 V,
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
IS = 1 A,
= 0,
GS
See Figures 1 and 14
See Figure 2
ID = 1 A, VGS = 10 V,
VDS = 48 V,
=
= 25 Ω,t
= 10 ns,
µs,
TPIC2601
72 ns
430
90
180
5.1 6.4
0.5 0.63
2.75 3.4
nC
thermal resistance
R
Junction-to-ambient thermal resistance All outputs with equal power 72
θJA
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
All outputs with equal power 4
One output dissipating power 7
°C/W
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
2
TJ = 25°C
1
0
–1
–2
Reversed di/dt = 100 A/µs
25% of l
RM
{
Pulse Generator
(see Note A)
R
gen
50 Ω
TEST CIRCUIT
–3
– Source-to-Drain Diode Current – A
–4
SD
I
{
l
–5
–6
0 25 50 75 100 125 150 175 200 225 250
†
IRM = maximum recovery current
RM
t – Time – ns
Shaded Area = Q
t
rr(SD)
RR
Figure 1. Reverse-Recovery Current Waveform of Source-to-Drain Diode
V
DD
t
en
t
d(on)
90%
10%
t
f
VOLTAGE WAVEFORMS
90%
10%
R
L
V
DS
V
GS
DUT
50 Ω
V
GS
V
DS
t
dis
10 V
90%
0
t
d(off)
V
DD
V
DS(on)
t
r
NOTE A: The pulse generator has the following characteristics: ten ≤ 10 ns, t
Figure 2. Resistive Switching
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
≤ 10 ns, ZO = 50 Ω.
dis
Page 5
Battery
12-V
0.2 µF
50 kΩ
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
Same Type
0.3 µF
as DUT
V
DD
Q
gs(th)
10 V
V
GS
TPIC2601
Q
g
Q
gd
0
Pulse Generator
(see Note A)
R
gen
50 Ω
TEST CIRCUIT
IG = 1 mA
IG Sampling
Resistor
TEST CIRCUIT
DUT
ID Sampling
Resistor
Gate Voltage
t – Time – s
Qgs = Qg – Q
WAVEFORM
gd
Figure 3. Gate Charge Test Circuit and Waveform
25 V
L
V
V
I
D
V
GS
50 Ω
DS
DUT
GS
I
D
V
DS
t
w
VOLTAGE AND CURRENT WAVEFORMS
t
av
10 V
0
I
AS
(see Note B)
0
V
(BR)DSX
0
= 60 V MIN
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 2 A.
IAS
Energy test level is defined as EAS+
V
(BR)DSX
2
t
av
+
105 mJ minimum where tav+
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
avalanche time.
5
Page 6
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
2
1.5
1
0.5
– Gate-to-Source Threshold Voltage – V
GS(th)
V
0
– 40 – 20 0 20 40 60 80 100 120 140 160
TJ – Junction Temperature – °C
VDS = V
ID = 1 mA
ID = 100 µA
GS
Figure 5
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
1
TJ = 25°C
Ω
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
1
ID = 2 A
0.8
0.6
0.4
– Static Drain-to-Source
On-State Resistance – Ω
DS(on)
0.2
r
0
– 40 – 20 0 20 40 60 80 100 120 140 160
TJ – Junction Temperature – °C
VGS = 10 V
VGS = 15 V
Figure 6
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
9
8
7
VGS = 15 V
VGS = 10 V
Delta VGS = 0.4 V
Unless Otherwise
Noted
TJ = 25°C
VGS = 6 V
– Static Drain-to-Source
On-State Resistance –
DS(on)
r
0.1
110
6
VGS = 10 V
VGS = 15 V
ID – Drain Current – A
Figure 7
6
5
4
– Drain Current – A
D
3
I
2
1
0
0123456
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VGS = 4 V
78910
VDS – Drain-to-Source Voltage – V
Figure 8
Page 7
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
TYPICAL CHARACTERISTICS
DISTRIBUTION OF FORWARD TRANSCONDUCTANCE
40
Total Number of
Units = 367
35
VDS = 15 V
ID = 1 A
30
TJ = 25°C
TPIC2601
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
8
7
6
TJ = –40°C
TJ = 25°C
VDS = 15 V
25
20
15
Percentage of Units – %
10
5
0
1.85 1.875 1.9 1.925 1.95
gfs – Forward Transconductance – S
DRAIN-TO-SOURCE VOLTAGE
500
450
400
350
300
f = 1 MHz
TJ = 25°C
C
(0) = 257 pF
iss
C
(0) = 488 pF
oss
C
(0) = 213 pF
rss
Figure 9
CAPACITANCE
vs
1.975 2
5
4
3
– Drain Current – A
D
I
2
1
0
0
1234
VGS – Gate-to-Source Voltage – V
TJ = 150°C
5678910
Figure 10
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
10
VGS = 0
TJ = –40°C
250
200
Capacitance – pF
150
100
50
0
C
iss
C
oss
C
rss
10 20 30 40
VDS – Drain-to-Source Voltage – V
Figure 11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TJ = 150°C
– Source-to-Drain Diode Current – A
SD
I
0.1
0.1 1
VSD – Source-To-Drain Voltage – V
TJ = 25°C
10
Figure 12
7
Page 8
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
TYPICAL CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
60
50
40
TC = 25°C
See Figure 3
VDD = 20 V
VDD = 30 V
12
10
8
100
95
90
85
80
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
VDS = 48 V
VGS = 0
IS = 1 A
TJ = 25°C
See Figure 1
30
20
– Drain-to-Source Voltage – V
DS
V
10
0
0123
Qg – Gate Charge – nC
MAXIMUM DRAIN CURRENT
DRAIN-TO-SOURCE VOLTAGE
10
TC = 25°C
DC
1
VDD = 20 V
Figure 13
vs
DC
6
4
VDD = 48 V
2
0
456
10 ms
1 ms
0.5 ms
– Gate-to-Source Voltage – VV
GS
75
70
65
– Reverse-Recovery Time – ns
rr
60
t
55
50
0 50 100 150
Reverse di/dt – A/µs
Figure 14
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
100
See Figure 4
10
TC = 25°C
200 250 300
– Maximum Drain Current – A
D
I
0.1
10 100
VDS – Drain-To-Source Voltage
10 µs
– Maximum Peak Avalanche Current – A
AS
I
1
0.1 1 10
Figure 15
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TC = 125°C
100
tav – Time Duration of Avalanche – ms
Figure 16
Page 9
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
THERMAL INFORMATION
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
1
DC Conditions
C/W
°
d = 0.2
d = 0.1
d = 0.05
0.1
d = 0.02
d = 0.01
Single Pulse
– Normalized Junction-to-Ambient Thermal Resistance –
JAθ
R
KTC PACKAGE
†
vs
PULSE DURATION
t
c
t
w
I
D
0
0.01
0.0001
†
Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink.
NOTE A: ZθA(t) = r(t) R
tw = pulse duration
tc = cycle time
d = duty cycle = tw/t
θJA
0.001 0.01
tw – Pulse Duration – s
c
Figure 17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.1 1 10
9
Page 10
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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