Datasheet TN5325 Specification

TN5325

3-lead SOT-23 (TO-236AB)

(Top view)

See Table 2-1, Table 2-2 and Table 2-3 for pin information.

3-lead TO-92

(Top view)

3-lead SOT-89 (243AA)

(Top view)

N-Channel Enhancement-Mode Vertical DMOS FET

Features

• Low Threshold (2V Maximum)

• High Input Impedance and High Gain

• Free from Secondary Breakdown

• Low CISS and Fast Switching Speeds

Applications

• Logic-level Interfaces (Ideal for TTL and CMOS)

• Solid State Relays

• Battery-operated Systems

• Photo-voltaic Drives

• Analog Switches

• General Purpose Line Drivers

• Telecommunication Switches

General Description

The TN5325 is a low-threshold, Enhancement-mode
(normally-off) transistor that utilizes a vertical DMOS
structure and a well-proven silicon gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, this device is free from thermal
runaway and thermally induced secondary breakdown.

Microchip’s vertical DMOS FETs are ideally suited to a

e range of switching and amplifying applications

wid
where very low threshold voltage, high breakdown
voltage, high input impedance, low input capacitance
and fast switching speeds are desired.

Package Types

DRAIN

 2017 Microchip Technology Inc. DS20005709A-page 1

GATE

SOURCE

SOURCE

DRAIN

DRAIN

GATE

SOURCE

DRAIN

GATE

TN5325

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings†

Drain-to-source Voltage ....................................................................................................................................... BV

Drain-to-gate Voltage .......................................................................................................................................... BV

Gate-to-source Voltage ......................................................................................................................................... ±20V

Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C

Storage Temperature, T

..................................................................................................................... –55°C to +150°C

S

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.

DSX

DGX

DC ELECTRICAL CHARACTERISTICS

1

Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C.

Parameter Sym. Min. Typ. Max. Unit Conditions

Drain-to-source Breakdown Voltage BV

Gate Threshold Voltage V

Change in V

with Temperature ∆V

GS(th)

Gate Body Leakage I

Zero-gate Voltage Drain Current I

On-state Drain Current I

Static Drain-to-source On-state

ance

Resist

Change in R

with Temperature ∆

DS(ON)

R

RDS(ON)

DSS

GS(th)

GS(th)

GSS

DSS

D(ON)

DS(ON)

250 — — V VGS = 0V, ID = 100 µA

0.6 — 2 V VGS = VDS, ID = 1 mA

— — –4.5 mV/°C VGS = VDS, ID = 1 mA (Note 2)

— — 100 nA VGS = ± 20V, VDS = 0V

— — 1

— — 10 V

— — 1 mA

0.6 — —

1.2 — — V

— — 8

— — 7 V

VGS = 0V, VDS = 100V

µA

A

Ω

= 0V, VDS = Maximum Rating

GS

= 0.8 Maximum Rating,

V

DS

= 0V, TA = 125°C (Note 2)

V

GS

VGS = 4.5V, VDS = 25V

= 10V, VDS = 25V

GS

VGS = 4.5V, ID = 150 mA

= 10V, ID = 1A

GS

— — 1 %/°C VGS = 4.5V, ID = 150 mA (Note 2)

Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty

cycle.

pecification is obtained by characterization and is not 100% tested.

2: S

DS20005709A-page 2  2017 Microchip Technology Inc.

TN5325

AC ELECTRICAL CHARACTERISTICS

2

Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C.

Parameter Sym. Min. Typ. Max. Unit Conditions

Forward Transconductance G

Input Capacitance C

Common Source Output Capacitance C

Reverse Transfer Capacitance C

Turn-on Delay Time t

d(ON)

Rise Time t

Turn-off Delay Time t

d(OFF)

Fall Time t

FS

ISS

OSS

RSS

150 — — mmho VDS = 25V, ID = 200 mA

— — 110

— — 60

— — 23

pF

V

= 0V, 

GS

= 25V, 

V

DS

f = 1 MHz

— — 20

V

= 25V, 

r

f

— — 15

— — 25

— — 25

ns

DD

= 150 mA, 

I

D

R

= 25Ω

GEN

DIODE PARAMETER

Diode Forward Voltage Drop V

Reverse Recovery Time t

Note 1: All DC p

arameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty

SD

rr

— — 1.8 V VGS = 0V, ISD = 200 mA (Note 1)

— 300 — ns VGS = 0V, ISD = 200 mA (Note 2)

cycle.

pecification is obtained by characterization and is not 100% tested.

2: S

TEMPERATURE SPECIFICATIONS

Parameter Sym. Min. Ty p. Max. Unit Conditions

TEMPERATURE RANGE

Operating Ambient Temperature T

Storage Temperature T

PACKAGE THERMAL RESISTANCE

3-lead SOT-23 

3-lead TO-92 

3-lead SOT-89 

Note 1: Mounted

on FR5 25 mm x 25 mm x 1.57 mm

JA



JC

JA



JC

JA



JC

–55 — +150 °C

A

–55 — +150 °C

S

— 350 — °C/W

— 200 — °C/W

— 170 — °C/W

— 125 — °C/W

— 78 — °C/W Note 1

— 15 — °C/W

THERMAL CHARACTERISTICS

( 1)

I

Package

D

(Continuous)

(mA)

3-lead SOT-23 150 0.4 0.36 150 0.4

3-lead TO-92 215 0.8 0.74 215 0.8

3-lead SOT-89 316 1.5 1.6

Note 1: ID (continuous) is limited by maximum TJ.

2: Mounted

 2017 Microchip Technology Inc. DS20005709A-page 3

on FR5 board, 25 mm x 25 mm x 1.57 mm

I

D

(Pulsed)

(A)

Power Dissipation at

TA = 25°C

(W)

( 2)

( 1)

I

DR

(mA)

316 1.5

I

DRM

(A)

TN5325

2.0 PIN DESCRIPTION

Table 2-1, Ta b le 2-2 and Table 2-3 show the

description of pins in TN5325 3-lead SOT-23, 3-lead
TO-92 and 3-lead SOT-89, respectively. Refer to

Package Types for the location of pins.

TABLE 2-1: SOT-23 PIN FUNCTION TABLE

Pin Number Pin Name Description

1 Gate Gate

2 Source Source

3 Drain Drain

TABLE 2-2: TO-92 PIN FUNCTION TABLE

Pin Number Pin Name Description

1 Source Source

2 Gate Gate

3 Drain Drain

TABLE 2-3: SOT-89 PIN FUNCTION TABLE

Pin Number Pin Name Description

1 Gate Gate

2 Drain Drain

3 Source Source

4 Drain Drain

DS20005709A-page 4  2017 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

90%

10%

90%

90%

10%

10%

Pulse

Generator

VDD

R

L

OUTPUT

D.U.T.

t

(ON)

t

d(ON)

t

(OFF)

t

d(OFF)

t

r

INPUT

INPUT

OUTPUT

10V

VDD

R

GEN

0V

0V

t

f

Figure 3-1 illustrates the switching waveforms and test

circuit for TN5325.

FIGURE 3-1: Switching Waveforms and Test Circuit.

PRODUCT SUMMARY

R

BV

/BV

DSS

DGS

(V)

250V 7 1.2 2

DS(ON)

(Maximum)

(Ω)

I

D(ON)

(Minimum)

(A)

TN5325

V

GS(th)

(Maximum)

(V)

 2017 Microchip Technology Inc. DS20005709A-page 5

TN5325

Legend: XX...X Product Code or Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC

®

designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.

3

e

3

e

XXXNNN

N3C232

3-lead SOT-23

Example

3-lead TO-92

YWWNNN

XXXXXX
XXXX

e3

Example

725698

TN5325
N3

e3

3-lead SOT-89 Example

XXXXYWW

NNN

TN3C714
478

4.0

PACKAGING INFORMATION

4.1 Package Marking Information

DS20005709A-page 6  2017 Microchip Technology Inc.

3-Lead TO-236AB (SOT-23) Package Outline (K1/T)

2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch

Symbol A A1 A2 b D E E1 e e1 L L1 ș

Dimension

(mm)

MIN 0.89 0.01 0.88 0.30 2.80 2.10 1.20

0.95
BSC

1.90
BSC

0.20

†

0.54
REF

0

O

NOM - - 0.95 - 2.90 - 1.30 0.50 -

MAX 1.12 0.10 1.02 0.50 3.04 2.64 1.40 0.60 8

O

JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.

Drawings not to scale.

View B

View A - A

Side View

Top View

View B

Gauge

Plane

Seating

Plane

0.25

L1

L

E1

E

D

3

1

2

e

e1

b

A

A

Seating

Plane

A

A2

A1

TN5325

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

 2017 Microchip Technology Inc. DS20005709A-page 7

TN5325

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

DS20005709A-page 8  2017 Microchip Technology Inc.

3-Lead TO-243AA (SOT-89) Package Outline (N8)

Symbol A b b1 C D D1 E E1 e e1 H L

Dimensions

(mm)

MIN

1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.00

†

1.50
BSC

3.00
BSC

3.94 0.73

†

NOM-------- --

MAX 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 4.25 1.20

JEDEC Registration TO-243, Variation AA, Issue C, July 1986.

† This dimension differs from the JEDEC drawing
Drawings not to scale.

b

b1

D

D1

E

H

E1

C

A

12 3

e

e1

Top View

Side View

L

TN5325

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

 2017 Microchip Technology Inc. DS20005709A-page 9

TN5325

NOTES:

DS20005709A-page 10  2017 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision A (April 2017)

• Converted Supertex Doc# DSFP-TN5325 to
Microchip DS20005709A

• Changed the part marking format

• Removed the N3 P003, N3 P005, N3 P013 and
N3 P014 media types

• Made minor text changes throughout the docu­ment

TN5325

 2017 Microchip Technology Inc. DS20005709A-page 11

TN5325

Examples:

a) TN5325K1-G: N-Channel Enhancement-

Mode Vertical DMOS FET,
3-lead SOT-23, 3000/Reel

b) TN5325N3-G: N-Channel Enhancement-

Mode Ver-tical DMOS FET,
3-lead TO-92, 1000/Bag

c) TN5325N3-G-P002: N-Channel Enhancement-

Mode Vertical DMOS FET,
3-lead TO-92, 2000/Reel

d) TN5325N8-G: N-Channel Enhancement-

Mode Vertical DMOS FET,
3-lead SOT-89, 2000/Reel

PART NO.

Device

Device: TN5325 = N-Channel Enhancement-Mode Vertical

DMOS FET

Packages: K1 = 3-lead SOT-23

N3 = 3-lead TO-92

N8 = 3-lead SOT-89

Environmental: G = Lead (Pb)-free/RoHS-compliant Package

Media Types: (blank) = 3000/Reel for a K1 Package

= 1000/Bag for an N3 Package

= 2000/Reel for an N8 Package

P002 = 2000/Reel for an N3 Package

XX

Package

-

X - X

Environmental

Media Type

Options

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

DS20005709A-page 12  2017 Microchip Technology Inc.

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ISBN: 978-1-5224-1556-5

 2017 Microchip Technology Inc. DS20005709A-page 13

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DS20005709A-page 14  2017 Microchip Technology Inc.

11/07/16