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GLOBAL AND SCALABLE ARCHITECTURE
The TL850 has a programmable architecture that supports multiple international standards including ATSC, OpenCable,
European DVB, the Japanese ARIB standard and proprietary standards such as DIRECTV
®
.
This single-chip solution integrates an MPEG-2 MP@HL video decoder, a display processor with scan rate converter, a transport
demultiplexer and a graphics accelerator for Digital Television. It supports all DVB/ATSC/ARIB decode and display formats.
The TL850 can handle an ATSC, DVB or DIRECTV transport stream, PES, ES and/or legacy analog formats.
MAKING TELEVISION COMPELLING AND ENGAGING
The graphics processor supports a variety of graphics planes in addition to the video and cursor planes. The pixel depth and
graphics resolution is selectable to allow a trade off between look and feel and
memory footprint.
The TL850’s graphics engine supports high quality, flicker-reduced OSD and
graphics to provide a rich, crisp, TV-centric GUI and other advanced graphical
features needed for advanced STBs and TVs.
A key differentiating feature of the TL850 is the ability to do multiple standard
definition decode and display. The display processor supports split screen,
picture-in-picture and picture-out-of-picture modes. These are complemented by
two video input ports. One port is for a transport stream and the other port is for
simultaneous input of an externally digitized analog stream. The TL850 has two outputs – a primary output supporting all formats
and an auxiliary output for VCR recording.
All Format video/graphics processor for Consumer Electronic OEMs
manufacturing Digital TV sets, Digital Set-Top Boxes and PVRs
TL850
Digital TV Decoder
Transport
Stream
CCIR656
QPSK, QAM or
VSB Receiver
NTSC/PAL
Decoder
PCI Bus
4MB - 64MB
SDRAM
TL850
Tuner
RGB/YUV
CCIR656
HDTV or
Monitor
5.1 Channel
Analog Audio
16:9
4:3
32
TL850 SYSTEM DIAGRAM
integrated circuits
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Copyright 2000. TeraLogic, Inc. All rights reserved worldwide. TeraLogic and the TeraLogic logo are registered trademarks of TeraLogic, Inc. Janus is a
trademark of TeraLogic, Inc. All other trademarks are properties of their respective owners and are acknowledged. 11/00 - 5K
TeraLogic, Inc. 1240 Villa Street Mountain View CA 94041
tel 650.526.2000 fax 650.526.2006 www.teralogic.tv
circuits
APPLICATIONS
• Digital TV Sets
• Digital Set-top Boxes
• Personal Video Recorders
SUPPORTING TERALOGIC PRODUCTS
• TL81x STB/PVR Controller ICs
• Cougar Development Platform
HIGH PERFORMANCE DIGITAL VIDEO DECODER
• MP@HL MPEG-2 decoder
• ATSC/DVB/ARIB/DIRECTV compliant
• Decodes 1 HD or 4 SD streams
simultaneously
HIGH PERFORMANCE DISPLAY PROCESSOR
• All 18 ATSC formats supported
• Letterbox and pan-and-scan options for
displaying 16:9 video on 4:3 TVs
• Frame rate conversion for 3:2 pulldown
• Multiple video services displayed on the
same screen including picture-in-picture
(PIP) and picture-out-of-picture (POP)
applications
• Graphics overlay plane with up to 24 bits
per pixel and 8-bit alpha channel
• Cursor plane with 32x32 pixel cursor with 4bit index (16 colors with 8-bit alpha blending)
• Analog RGB (EIA-770) or YCrCb output
for HDTV display or SD display in downconversion mode
• 16- or 24-bit digital video output
AUDIO PROCESSING
• Digital audio inputs supporting up to six
channel sources (
I
2
S compatible)
• Audio capture to memory or bypass
to output
• Three channel internal PCM audio play
• Audio stream play from memory
• Audio mix, cross-fade and attenuate
between sources
• Six channel audio output
• IEC-958 formatted output supported
• Provides audio rate buffer
• Provides audio and video PTS
synchronization
MEMORY CONTROLLER
• Programmable clock generator
• Up to 64 Mbytes addressing range
• Advanced Memory Reduction (AMR)
mode supports HD decode in 8 Mbytes
of memory
PROGRAMMABLE TRANSPORT
DEMULTIPLEXER
• ATSC/ARIB/DVB/DIRECTV compliant
• Transport or PES can be fed through
PCI bus or dedicated input
ACCELERATED 2-D GRAPHICS
• Hardware BLT engine
• 1-, 4-, 8-, 15-, 16- and 24-bit per pixel
RGB GRAPHICS SUPPORT
• Up to 32 bpp Graphics in RGB color space
• Alpha channel arithmetic engine
• Hardware color expansion and reduction
• Hardware flicker reduction for
interlaced display
• Full alpha blend support
PCI BUS INTERFACE
• 32-bit interface (master or slave)
• 50 MHz or 33 MHz bus clock
TECHNOLOGY
• 2.5 V core, 3.3 V I/O, 0.25µ CMOS
• 348-pin ball grid array package
FLEXIBLE FORMAT CONVERTER
• High-quality scan conversion from ATSC
source formats to output display formats
• Many nonstandard output and source
formats supported
• High quality up-conversion and downconversion of source video to selected
display format
• Integrated, high-quality line doubling using
adaptive interpolation
NTSC VIDEO INTEGRATION
• Video capture port for NTSC/PAL digital
video (CCIR656 compatible)
• Supports analog VCR recording of off-air
programming
• Analog inputs upscaled to HD resolution
TL850 Digital TV Decoder
2D Graphics
• 32 bit engine
• Anti-alias filter
• Alpha blending
Memory 4/8/16 MB
PCI Bus
TL850
Memory Controller
PCI Controller
SD/HD Transport
Stream
Digital Video
CCIR656
Audio In
Digital HD
Video
Analog HD Out
(RGB/YP
b
P
r
)
Audio Out
(I
2
S and IEC958)
CCIR656
SD Video
Display Processor
• All form
ats
• 1080i, 720p, 480p, 480i
Transport
Demultiplexer
• ATSC
• ARIB
• DVB
• DIRECTV
Video Scaler
• 19 tap H/V filters
• Line doubler
• High quality
up/down conversion
• I to P conversion
• Aspect ratio
conversion
Audio
Processor/
Mixer
32
Digital Video Decoder
• M
P@
HL M
PEG2
• Decodes all 18 ATSC form
ats
• 1 HD or 4 SD stream
s
• Decodes DVD video
• ATSC, DVB, ARIB com
pliant
TL850 BLOCK DIAGRAM
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