Datasheet tda8798 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8798

Dual 8-bit, 100 Msps A/D converter
with DPGA

Objective specification
Supersedes data of 1998 Apr 15
File under Integrated Circuits, IC02

1999 Sep 16

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with

TDA8798

DPGA

FEATURES

• Dual 8-bit Analog-to-Digital Converter (ADC)

• Sampling rate up to 100 million samples per

second (Msps)

• Dual 34 dBV 6-bit Digitally Programmable Gain
Amplifier (DPGA) with optional power-off

• Optional external equalization filter with capacitive
coupling between DPGA and ADC

• Serial Interface (SI) for DPGA gain control using either
parallel load mode or count-up/count-down mode

• 3.3 V TTL/CMOS compatible I/O

• Differential or single-ended TTL/CMOS clock interface

• AC or DC coupling for DPGA inputs.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
V
V
I

DDA

DDA
DDD
DDO

analog supply voltage 3.15 3.3 3.45 V
digital supply voltage 3.0 3.3 3.6 V
output stage supply voltage 2.7 3.3 3.6 V
analog supply current with DPGAEN LOW − 106 − mA

with DPGAEN HIGH − tbf − mA

I

DDD

I

DDO

digital supply current − 30 − mA
output stage supply current − 3 − mA

INL DC integral non-linearity from IC analog input to digital

output; ramp input;
f

CLK

DNL DC differential non-linearity from IC analog input to digital

output; ramp input;
f

CLK

V

n(o)(rms)

output referred noise (RMS value) DPGA at G

noise bandwidth = 15 MHz

B

(−3dB)(ADC)

B

(−3dB)(DPGA)

f

(sample)(max)

P

tot

ADC −3 dB analogue bandwidth at V
DPGA −3 dB bandwidth at V
maximum sampling rate 100 −−Msps
total power dissipation with DPGAEN LOW − 460 500 mW

with DPGAEN HIGH − tbf tbf mW

APPLICATIONS

• High-dynamic range acquisition front-ends

• Digital data storage read channels.

GENERAL DESCRIPTION

The TDA8798 is a dual 8-bit ADC with DPGA.
The 100 Mspsmaximumsamplingrateand34 dBVDPGA
gain range optimizes the ADC for high dynamic range
applications.

= 100 MHz

with DPGA at G

(min)

−±3.0 tbf LSB

without DPGA −±1.0 tbf LSB

= 100 MHz

with DPGA at G

(min)

−±0.5 tbf LSB

without DPGA −±0.5 tbf LSB

i(dif)(FS)
i(dif)(max)

; Zi =50Ω;

(max)

− tbf 2 mV

− 120 − MHz

30 tbf − MHz

rms

1999 Sep 16 2

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

ORDERING INFORMATION

to BUF2
to BUF2N

V

oref2

64

BUFFER

TDA8798

BUFFER

1718161514

V

oref1

PACKAGE

TE

TEST

54

62

REGULATOR

REGULATOR

DDA3

V

SSA3

V

V

SR

52

ADC2

ADC1

DDO1

V

V

SSA4

A

A

DDO2

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8798HL LQFP64 plastic low profile quad flat package; 64 leads;

body 10 × 10 × 1.4 mm

BLOCK DIAGRAM

handbook, full pagewidth

analog
input 2

analog
input 1

VIN2N

VIN2

V

DDA2

V

SSA2

V

SSD1

V

DDD1

DPGAEN

V

DDD2

V

SSD2

V

SSA1

V

DDA1

VIN1

VIN1N

6
7
5

8
24
25

53
56

57

9
12

10
11

to DPGA2

to DPGA2N

DPGAC2

DPGA2

SERIAL

INTERFACE

DPGA1

3

DPGA2

DPGA2N

2

6

6

OPTIONAL

EXTERNAL

FILTER 2

BUF2N

1

BUF1NDPGA1

BUF2

63

BUF1DPGA1NDPGAC1

V

6055

D

D

V

SSO1

DDA4

61 51

325031212019

OE

V

SSO2

41 to 48

40 to 33

49

MGM863

TDA8798

SOT314-2

58

CLK2

59

CLK2N

digital
output 2
B0 to B7

4

V

ref2

27

SEN2

29

SCLK

26

SMODE

28

SDATA

30

SEN1

13

V

ref1

digital
output 1
A0 to A7

23

CLK1

22

CLK1N

to DPGA1N

to DPGA1

OPTIONAL

EXTERNAL

FILTER 1

Fig.1 Block diagram.

1999 Sep 16 3

to BUF1N
to BUF1

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

handbook, full pagewidth

I

OUT

−

I

OUT

External filtering may be used between DPGA and ADC to limit the noise bandwidth.

The external filterhasalow-passcut-offfrequency of .

and a high-pass cut-off frequency of

Other types of filter may be used if DC biasing is correct.

C

o(DPGA)

C

o(DPGA)

f

10 µH

(1)

DPGA

L

R

o(DPGA)

R

o(DPGA)

DPGAN

(3)

L

10 µH

TDA8798 TDA8798

R2⁄ R

+

l 3dB–()

1

C×

1

×≈

------ -

------------------------------------------

2π

.

L

h 3dB–()

1

×≈

------ -

----------------------------- -

2π

R

f

iADC()

100 nF

C

R
1 kΩ

C

100 nF

oDPGA()

(2)

BUF

R

i(ADC)

R

i(ADC)

(4)

BUFN

(1) DPGA1/DPGA2
(2) BUF1/BUF2
(3) DPGA1N/DPGA2N
(4) BUF1N/BUF2N

C

i(ADC)

C

i(ADC)

TDA8798

FCE267

Fig.2 External filter.

PINNING

SYMBOL PIN DESCRIPTION

DPGA2N 1 DPGA2 inverting output
DPGA2 2 DPGA2 non-inverting output
DPGAC2 3 DPGA2 bandwidth limitation control
V
V

ref2
DDA2

4 ADC2 reference output

5 DPGA2 analog supply voltage
VIN2N 6 DPGA2 inverting input voltage
VIN2 7 DPGA2 non-inverting input voltage
V
V

SSA2
SSA1

8 DPGA2 analog ground

9 DPGA1 analog ground
VIN1 10 DPGA1 non-inverting input voltage
VIN1N 11 DPGA1 inverting input voltage
V
V

DDA1
ref1

12 DPGA1 analog supply voltage

13 ADC1 reference output
DPGAC1 14 DPGA1 bandwidth limitation control
DPGA1 15 DPGA1 non-inverting output
DPGA1N 16 DPGA1 inverting output

1999 Sep 16 4

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

SYMBOL PIN DESCRIPTION

BUF1 17 buffer1 non-inverting input
BUF1N 18 buffer1 inverting input
V

oref1

V

DDA3

V

SSA3

CLK1N 22 ADC1 inverting clock input
CLK1 23 ADC1 non-inverting clock input
V

SSD1

V

DDD1

SMODE 26 serial interface mode input
SEN2 27 serial interface enable 2 (active low)
SDATA 28 serial interface data input
SCLK 29 serial interface clock input
SEN1 30 serial interface enable 1 (active low)
V

DDO1

V

SSO1

A7 33 channel 1 output bit 7 (MSB)
A6 34 channel 1 output bit 6
A5 35 channel 1 output bit 5
A4 36 channel 1 output bit 4
A3 37 channel 1 output bit 3
A2 38 channel 1 output bit 2
A1 39 channel 1 output bit 1
A0 40 channel 1 output bit 0 (LSB)
B0 41 channel 2 output bit 0 (LSB)
B1 42 channel 2 output bit 1
B2 43 channel 2 output bit 2
B3 44 channel 2 output bit 3
B4 45 channel 2 output bit 4
B5 46 channel 2 output bit 5
B6 47 channel 2 output bit 6
B7 48 channel 2 output bit 7 (MSB)
V

SSO2

V

DDO2

OE 51 digital output enable (active LOW)
SR 52 digital output bit slew-rate control
DPGAEN 53 DPGA enable (active LOW)
TEST 54 test input (to be grounded)
TE 55 track-and-hold enable (active LOW)
V

DDD2

V

SSD2

19 buffer1 common mode reference output

20 ADC1 analog supply voltage 3

21 ADC1 analog ground 3

24 digital ground 1

25 digital supply voltage 1

31 output stage supply voltage 1

32 output stage ground 1

49 output stage ground 2

50 output stage supply voltage 2

56 digital supply voltage 2

57 digital ground 2

TDA8798

1999 Sep 16 5

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

SYMBOL PIN DESCRIPTION

CLK2 58 ADC2 non-inverting clock input
CLK2N 59 ADC2 inverting clock input
V

SSA4

V

DDA4

V

oref2

BUF2N 63 buffer2 inverting input
BUF2 64 buffer2 non-inverting input

handbook, full pagewidth

60 ADC2 analog ground 4

61 ADC2 analog supply voltage 4

62 buffer2 common mode reference output

oref2

DDA4

SSA4

V

V

61

60

CLK2N
59

CLK2
58

TDA8798HL

DPGA2N

DPGA2

DPGAC2

V

ref2

V

DDA2

VIN2N

VIN2

V

SSA2

V

SSA1

VIN1

VIN1N

V

DDA1

V

ref1

DPGAC1

DPGA1

DPGA1N

BUF2N

BUF2

64
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

V

63

62

SSD2

V

57

DDD2

V

56

55

TE

TEST
54

SR

DPGAEN
53

52

OE

51

DDO2

V

50

SSO2

V

49

TDA8798

48

B7

47

B6

46

B5

45

B4

44

B3

43

B2
B1

42

B0

41
40

A0

39

A1

38

A2

37

A3

36

A4

35

A5

34

A6

33

A7

20

21

22

23

CLK1

24

V

17

BUF1

18

V

BUF1N

19

oref1

DDA3

V

SSA3

V

CLK1N

Fig.3 Pin configuration.

1999 Sep 16 6

SSD1

25

DDD1

V

26

27

SEN2

SMODE

28

SDATA

29

SCLK

30

SEN1

31

DDO1

V

32

SSO1

V

MGM864

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

FUNCTIONAL DESCRIPTION

The TDA8798 comprises two independent fully differential
signalchainseachhavingaDPGAandahigh-speed ADC.
A serial interface allows the gain of each DPGA to be
controlledindependently. To improve signal conditions, an
AC-coupled external filter can be connected between a
DPGAandADC.TheTDA8798canbeused as a dual 8-bit
ADC without DPGA functionality, using less power.

Digitally Programmable Gain Amplifier (DPGA)

The gain of the differential DPGA is programmable from
0 to 34 dBV in 63 equal steps by a 6-bit word output in
parallel from a gain control register in the SI. For all gain
settings, the DPGA signal bandwidth exceeds 30 MHz.
The settling time between gain changes can be adjusted
by an external decoupling capacitor connected to
DPGAC1 (pin 14) and/or DPGAC2 (pin 3). The analog
input signals can be either AC or DC coupled. When used
only as a dual 8-bit ADC, both DPGAs can be disabled to
reduce power consumption.

Analog-to-Digital Converter (ADC)

The 8-bit ADC converts the differential analog input signal
into a binary output format at a maximum conversion rate
of 100 Msps. All digital input and output signals are
TTL/CMOS compatible.

The ADC clock signal can be from either a differential or a
single-ended source; when single-ended, the unused
clockinputpinshouldbe decoupled externally. The analog
input to the ADC is AC coupled.

TDA8798

Serial Interface (SI)

The SI allows the gain of each DPGA to be controlled
independently using either a parallel load mode or a
count-up/count-down mode. The gain control mode is
selected by the state of SMODE. The operation of DPGA
gain control is shown in Timing diagram, (see Fig.4).

Parallel load mode

This mode loads gain control data serially into a decoder
in the SI. Each of the six bits are loaded on the rising edge
ofSCLK.After the load has completed, SEN goes inactive,
loading the data in parallel to a gain control register in the
SI, changing the gain of the DPGA.

Count-up/count-down mode

Count-up/count-down mode is selected when SMODE is
in the opposite state to parallel load mode. This mode
either increments or decrements the SI gain control
register in one-bit steps when SEN and SCLK are both
active; the state of SDATA determines the count direction
(up or down). This allows the gain of the DPGA to be
changed asynchronously and intermittently.

ADC digital outputs

Digital noise on the internal supply lines increases when
the V
between channels. This effect can be reduced by making
SR (pin 52) HIGH, changing the slew-rate of the ADC
digital outputs.

voltage increases, affecting the crosstalk

DDO

Whenused only as a dualADC, the ADC can beexternally
biased by regulator output V
V

(pin 62) using series resistors of, for example, 50 Ω,

oref2

(pin 19) and/or

oref1

connected to the ADCbuffer inputs providing a lower input
impedance. This requires V

oref1

and/or V

oref2

to be

decoupled to ground by a 10 nF capacitor.
V

(pin 13) and/or V

ref1

(pin 4) provide a voltage

ref2

corresponding to the bias of the ADC which can be used
as a reference output to an external control circuit.
Alternatively, an external control voltage can be applied to
these pins to adjust the full-scale range of the ADC.

1999 Sep 16 7

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

Table 1 Serial interface truth table; see notes 1 and 2

SMODE SCLK SEN1 SEN2 SDATA ACTION

0 1 1 U WAIT

X,

0 1 1 Di SISR: SISR ← Di

0 0 1 1 SISR: SISR ← 1

0 0 1 0 SISR: SISR ← 0

0 1 0 1 SISR: SISR ← 1

0 1 0 0 SISR: SISR ← 0

0 0 0 1 SISR: SISR ← 1

0 0 0 0 SISR: SISR ← 0

1 U WAIT

X, X, X,

TDA8798

GCR1: GCR1 + 1

GCR1: GCR1 − 1

GCR2: GCR2 + 1

GCR2: GCR2 − 1

GCR1: GCR1 + 1
GCR2: GCR2 + 1

GCR1: GCR1 − 1
GCR2: GCR2 − 1

1 Di SISR: SISR ← Di

X, X,

1 U GCR1: SISR

X, X,

1 U GCR2: SISR

X, X,

1 U GCR1: SISR

X,

Notes

1. ‘← Di’: shifting LSB and loading new LSB with value Di.

2. In count-up/count-down mode, thegain control register cannotbe incremented above themaximum gain value of 63,
or decremented below the minimum gain value of 0.

1999 Sep 16 8

GCR2: SISR

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

Table 2 Abbreviations

SYMBOL DESCRIPTION

GCR1 DPGA1 gain control register value
GCR2 DPGA2 gain control register value
SISR Serial interface shift register value
X can be either logic state 0 or logic

state 1
rising edge

falling edge

U can be either undefined logic stateX

rising edge or falling edge

Di Data input

Table 3

TE truth table

TE ADC TRACK-AND-HOLD

0 track-and-hold enabled
1 track enabled

Table 4 SR truth table

SR ADC DIGITAL OUTPUT SLEW RATE

0 maximum
1 minimum

Table 5 DPGAEN truth table

DPGAEN DPGA FUNCTIONALITY

0 enabled
1 disabled

Table 6 Gain Control

GAIN CONTROL

REGISTER VALUE

GAIN (dBV)

000000 0.00
000001 0.54
000010 1.08

... ...

... ...

... ...

111110 33.46
111111 34.00

TDA8798

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V
∆V

V

DDA
DDD
DDO

DDX

i(VIN)

analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
output stage supply voltage −0.3 +7.0 V
supply voltage differences between

V

and V
V
V

DDA
DDO
DDA

and V

and V

DDD
DDD
DDO

input voltage range on VIN1 and VIN2

referenced to V

SSA

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

−0.3 +7.0 V

(pins 10 and 7)

I

O

T

stg

T

amb

T

j

output current − 10 mA
storage temperature −55 +150 °C
ambient temperature 0 70 °C
junction temperature − 104 °C

1999 Sep 16 9

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with

TDA8798

DPGA

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

CHARACTERISTICS

V

DDA=V5

to 3.6 V; V
V

= −0.25 to +0.25 V; V

DDD

values measured at V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

V

DDD

V

DDO

I

DDA

I

DDD

I

DDO

Digital programmable gain amplifiers

thermal resistance from junction to ambient in free air 68 K/W

(or V12 or V20 or V61) to V8 (or V9 or V21 or V60) = 3.15 to 3.45 V; V

DDO=V31

(or V50) to V32 (or V49) = 2.7 to 3.6 V; V

to V

DDD

DDA=VDDD=VDDO

= −0.25 to +0.90 V; V

DDO

= 3.3 V and T

amb

, V

SSD

to V

and V

= −0.25 to +0.75 V; T

DDO

SSA

DDA

=25°C; unless otherwise specified.

DDD=V25

SSO

(or V56) to V24 (or V57) = 3.0

shorted together; V

=0to70°C; typical

amb

DDA

analog supply voltage 3.15 3.3 3.45 V
digital supply voltage 3.0 3.3 3.6 V
output stage supply voltage 2.7 3.3 3.6 V
analog supply current DPGAEN LOW − 106 − mA

DPGAEN HIGH − tbf − mA
digital supply current − 30 − mA
output stage supply current f

= 100 MHz;

CLK

− 3 − mA

ramp input

to

ANALOG INPUTS (VIN1, VIN1N, VIN2 AND VIN2N)
V

i(dif)(max)(p-p)

V

i(cm)(DPGA)

I

i(DPGA)

R

i(DPGA)

C

i(DPGA)

maximum differential input
voltage (peak-to-peak value)

common mode input voltage tbf 2.8 tbf V
input current at V
input resistance 1 −−kΩ
input capacitance −− 5pF

at G

at G

(min)
(max)

i(cm)(DPGA)

ANALOG OUTPUTS (DPGA1, DPGA1N, DPGA2 AND DPGA2N)
V

o(dif)(max)(p-p)

V

o(cm)(DPGA)

R

o(DPGA)

C

o(DPGA)

maximum differential output
voltage (peak-to-peak value)

at G

at G

(min)
(max)

common mode output voltage − 3.1 − V
output resistance at V

o(cm)(DPGA)

output capacitance −− 5pF

1999 Sep 16 10

− 0.5 − V

− 10 − mV

− tbf −µA

− 0.5 − V

− 0.5 − V

− 115 160 Ω

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with

TDA8798

DPGA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

BANDWIDTH AND SETTLING
B

(−3dB)(DPGA)

t

st

t

d(g)

GAIN
G

(min)

G

(max)

G

step

G

step(L)

G

(m)(c-c)

∆G/∆T amplifier gain stability as a

∆G/∆V

DD

AIN SWITCHING;T

G
t

st(G-G)

t

PD

REJECTION
PSRR power supply rejection ratio DC to 15 MHz

CMRR common mode rejection ratio 40 −−dB

ARMONICS;T

H
HD2 second harmonic distortion f

HD3 third harmonic distortion f

DPGA −3 dB bandwidth at V

i(dif)(max)

settling time full-scale transition

30 tbf − MHz
40 −−ns

10% to 90%
group delay fi up to 15 MHz

at G
at G

(min)
(max)

− tbf − ps

− tbf − ps

minimum gain setting tbf 0 tbf dBV
maximum gain setting tbf 34 tbf dBV
gain step size − 0.54 − dBV
gain step size linearity (actual

−0.75 − +0.75 dBV

gain step/average − 1)
channel-to-channel gain

matching

function of temperature
amplifier gain stability as a

function of power supply
voltage

=25°C

AMB

settling time between two

at G

at G

at G

at G

at G

at G

(min)
(max)
(min)
(max)
(min)
(max)

− tbf − dB

− tbf − dB

− 8 tbf mdB/°C

− 8 tbf mdB/°C

− 0.4 tbf dB/V

− 0.8 tbf dB/V

CL=68pF − 160 − ns
consecutive gain settings

propagation delay −− 20 ns

40 −−dB

at G

(min)

=25°C

AMB

= 15 MHz;

i

at V

o(dif)(max)

; at gain

control register:

00H 40 tbf − dB
20H 40 tbf − dB
3FH − tbf − dB

= 15 MHz;

i

at V

o(dif)(max)

; at gain

control register:

00H tbf 50 − dB
20H tbf 50 − dB
3FH − 50 − dB

1999 Sep 16 11

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with

TDA8798

DPGA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

NOISE
V

n(o)(rms)

ADC (without DPGA; f

NALOG INPUTS (BUF1, BUF1N, BUF2 AND BUF2N)

A
V

i(dif)(FS)(p-p)

V

i(cm)(ADC)

I

i(ADC)

R

i(ADC)

C

i(ADC)

STATIC LINEARITY
NL

dc(i)

NL

dc(dif)

DYNAMIC PERFORMANCE
THD total harmonic distortion fi= 4.43 MHz −−55 − dB

S/N signal-to-noise ratio without harmonics −−46 − dB
B

ANDWIDTH

B

(−3dB)(ADC)

CROSSTALK BETWEEN ADC1 AND ADC2

α

ct

CLOCK INPUTS: CLK1, CLK1N, CLK2 AND CLK2N; note 1
V

IL

V

IH

I

IH

I

IL

DIGITAL CONTROL INPUTS (OE, TE, TEST, DPGAEN AND SR)
V

IL

V

IH

I

IH

I

IL

output referred noise
(RMS value)

DPGA at G

(max)

Zi=50Ω; noise

;

− tbf 2 mV

bandwidth = 15 MHz

= 100 MHz; from buffer input to digital output)

CLK

differential input voltage

− 500 − mV
full-scale amplitude;
(peak-to-peak value)

common mode input voltage − tbf − V
input current at V

i(cm)(ADC)

− tbf −µA
input resistance − 20 − kΩ
input capacitance − 3 − pF

DC integral non-linearity ramp input;

without DPGA −±1.0 tbf LSB
with DPGA

at G

(min)

−±3.0 tbf LSB

DC differential non-linearity ramp input;

without DPGA −±0.5 tbf LSB
with DPGA

at G

(min)

−±0.5 tbf LSB

ADC −3 dB analog bandwidth − 120 − MHz

crosstalk between channels −−40 − dB

LOW-level clock input voltage −− 0.8 V
HIGH-levelclock input voltage 2.0 − V

DDD

V
HIGH-level clock input current −− 100 µA
LOW-level clock input current −100 −−µA

LOW-level input voltage −− 0.8 V
HIGH-level input voltage 2.0 − V

DDD

V
HIGH-level input current −5 − +5 µA
LOW-level input current −5 − +5 µA

rms

1999 Sep 16 12

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with

TDA8798

DPGA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DIGITAL OUTPUTS (A0 TO A7 AND B0 TO B7)
V

OL

V

OH

I

OZ

ADC CLOCK TIMING
f

CLK(max)

t

W(CLKL)

t

W(CLKH)

t

r(CLK)

t

f(CLK)

DATA TIMING (see Fig.4); F
t

d(s)(D)

t

d(Q)

t

h(Q)

3-

STATE OUTPUT DELAY TIMES (see Fig.6)

t

dZH

t

dZL

t

dHZ

t

dLZ

ADC R

EFERENCE OUTPUTS (V

V

o(ref)

R

o(ref)

I

o(ref)(max)

C

o(ref)

LOW-level output voltage IO =1mA −− 0.4 V
HIGH-level output voltage IO = −1mA V
output current in 3-state mode VO> 0.4 V;

VO<(V

DDO

− 0.4 V)

− 0.4 V −−V

DDO

−20 − +20 µA

maximum clock frequency 100 −−MHz
clock pulse width LOW

4.0 −−ns

duration
clock pulse width HIGH

4.0 −−ns

duration
clock pulse rise time 0.75 1 2 ns
clock pulse fall time 0.75 1 2 ns

= 100 MHZ;C

CLK

DPGAC

=10PF

data sampling delay time −− tbf ns
data output delay time SR HIGH − 5.0 tbf ns

SR LOW − tbf tbf ns

data output hold time SR HIGH tbf 5.0 − ns

SR LOW tbf tbf − ns

output delay enable at logic
HIGH

output delay enable at logic
LOW

output delay disable at logic
HIGH

output delay disable at logic
LOW

AND V

REF1

REF2

SR HIGH − tbf tbf ns
SR LOW − tbf tbf ns
SR HIGH − tbf tbf ns
SR LOW − tbf tbf ns
SR HIGH − tbf tbf ns
SR LOW − tbf tbf ns
SR HIGH − tbf tbf ns
SR LOW − tbf tbf ns

)

ADC reference output voltage − 1.24 − V
ADC reference output

at V

o(ref)

−− 10 Ω

resistance
ADC reference maximum

− 4.0 − mA

output current
ADC reference output

−− 3pF

capacitance

1999 Sep 16 13

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with

TDA8798

DPGA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

COMMON MODE REFERENCE OUTPUTS (V
V

o(ref)

R

o(ref)

I

o(ref)

reference output voltage − V
reference output resistance at V
reference maximum output

current

C

o(ref)

reference output capacitance −− 3pF

Serial Interface

DIGITAL INPUTS (SEN1, SEN2, SCLK, SDATA AND SMODE)
V

IL

V

IH

I

IH

I

IL

LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2.0 − V
HIGH-level input current −50 +5µA
LOW-level input current −50 +5µA

GAIN CONTROL DATA TIMING (see Fig.4)
f

SCLK(max)

t

W(SCLKH)

t

W(SCLKL)

t

su(SEN-SCLK

t

h(SEN-SCLK)

t

su(SDATA-SCLK)

t

h(SMODE-SCLK)

t

h(SMODE-SEN)

t

d(SEN-Q)

maximum clock frequency 5 −−MHz
clock pulse width HIGH 20 −−ns
clock pulse width LOW 20 −−ns

) SEN to SCLK set-up time 5 −−ns

SEN to SCLK hold time 5 −−ns
SDATA to SCLK set-up time 5 −−ns
SMODE to SCLK hold time 5 −−ns
SMODE to SEN hold time 5 −−ns
delay SEN rising edge to

change gain control register
value

t

d(SCLK-Q)

delay SCLK rising edge to
change gain control register
value

OREF1

AND V

at V

OREF2

o(cm)(ref)
o(cm)(ref)

)

− 0.42 V − V

DDA

− 400 −Ω

− 0.2 V − 170 −µA

DDD

−− 5ns

−− 5ns

V

Note

1. Single-ended clock signal sources are allowed. The unused clock input is internally biased at the logical threshold
(1.65 V for nominal supply conditions), and should be correctly decoupled.

1999 Sep 16 14

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1999 Sep 16 15

handbook, full pagewidth

parallel load mode count-up/count-down mode

Dual 8-bit, 100 Msps A/D converter with

DPGA

Philips Semiconductors Objective specification

SMODE

SEN

SCLK

SDATA

SI GAIN

CONTROL

REGISTER

DPGA

OUTPUTS

t

su(SEN-SCLK)

t

su(SDATA-SCLK)

t

h(SMODE-SEN)

t

h(SMODE-SCLK)

t

W(SCLKH)

D5

(MSB) (LSB)

D4 D3 D2 D1 D0

t

W(SCLKL)

t

su(SEN-SCLK)

t

h(SEN-SCLK)

t

su(SEN-SCLK)

up = 1

down = 0

t

d(SEN-Q)

D5 D4 D3 D2 D1 D0 REG +/−1 REG +/−1

t

st(G-G)

t

PD

down = 0

t

d(SCLK-Q)

up = 1

50%

50%

50%

10%

90%

MGM865

Fig.4 Timing diagram of serial interface.

TDA8798

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

W(CLKH)

sample N

t

d(s)(D)

t

W(CLKL)

sample N + 1 sample N + 2

DATA

N − 1

t

d(Q)

handbook, full pagewidth

CLK

V

i

DATA
A0 to A7
B0 to B7

t

DATA
N − 2

t

h(Q)

DATA

N

DATA

N + 1

TDA8798

HIGH

50 %

LOW

HIGH

50 %

LOW

MGM866

handbook, full pagewidth

output

output

V

DDO

OE

data

data

0 V

tdLZ

logic LOW

high impedance

10%

TDA8798

OE

Fig.5 Timing diagram for the ADC.

tdHZ

t

dZL

A0 to A7
B0 to B7

logic HIGH

50%

3.3 kΩ

10 pF

90%

high impedance

S1

V

DDO

50%

t

dZH

50%

TEST S1

t

dLZ

t

dZL

t

dHZ

t

dZH

V

DDO

V

DDO
GND
GND

MGM868

Fig.6 Timing diagram and test conditions of 3-state output delay time.

1999 Sep 16 16

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

TEST AND APPLICATION INFORMATION

handbook, full pagewidth

100 nF

V

SSA

V

SSA

3.3 V
V

IN2N
V

IN2

V

IN1

V

IN1N

3.3 V

V

SSA

V

SSA

(2)

68 pF

100 nF

100 nF

100 nF

100 nF

68 pF

100 nF

100 nF

(3)

(1)

(4)

(4)

(4)

(4)

(1)

(3)

100 nF

(2)

DPGA2N

DPGA2

DPGAC2

V

ref2

V

DDA2

VIN2N

VIN2

V

SSA2

V

SSA1

VIN1

VIN1N

V

DDA1

V

ref1

DPGAC1

DPGA1

DPGA1N

BUF2

64
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

BUF2N

V

63

oref2

62

3.3 V

DDA4

V

100 nF

V

SSA

V

61

(1)

SSA4

60

V

SSA

V

100 nF

CLK2N

59

SSD

CLK2

3.3 V
100 nF

V

SSD

CLK2

SSD2

DDD2

V

V

58

57

56

TDA8798HL

TE

TDA8798

3.3 V

(1)

V

SSD

V

SSD

TEST

54

DPGAEN

DPGAEN

53

TE

55

SR

SR

52

OE

OE

V

51

100 nF

V

DDO2

50

SSO

SSO2

V

(1)

V

SSO

49

B7

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

B6
B5
B4
B3
B2
B1
B0
A0
A1
A2
A3
A4
A5
A6
A7

B7
B6
B5
B4
B3
B2
B1
B0
A0
A1
A2
A3
A4
A5
A6
A7

20

21

22

23

24

25

26

27

28

29

30

31

DDO1

V

3.3 V3.3 V3.3 V

SSO1

V

V

SSO

100 nF

32

(1)

V

SSO

MGM867

100 nF

(2)

100 nF

(2)

17

BUF1

18

V

BUF1N

19

oref1

DDA3

V

SSA3

V

V

SSA

100 nF

CLK1N

(1)

CLK1

CLK1

100 nF
V

SSD

V

SSA

V

SSD1

V

SSD

DDD1

V

SMODE

100 nF

SEN2

SEN2

SMODE

(1)

SDATA

V

SSD

SCLK

SDATA

SCLK

SEN1

SEN1

Analog and digital supplies must be separate and decoupled.
(1) Supply decoupling capacitor must be placed as close as possible to the chip’s pin. Value may need changing depending on the external filter

characteristics.
(2) Capacitor may be replaced when an external filter is used with AC coupling.
(3) Capacitor value may be changed to adjust settling time between DPGA gain changes.
(4) Capacitor value may need changing depending on the high-pass cut-off frequency of the external filter.

Fig.7 Application diagram.

1999 Sep 16 17

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

INTERNAL PIN CONFIGURATIONS

handbook, halfpage

handbook, halfpage

V

DDA3

V

DDA1

VIN1

VIN1N

V

SSA1

1 kΩ

Fig.8 DPGA1 analog input.

0.5 V

MGM869

handbook, halfpage

handbook, halfpage

V

V

V

DDA4

DDA2

VIN2

VIN2N

SSA2

1 kΩ

Fig.9 DPGA2 analog input.

TDA8798

0.5 V

MGM870

V

oref1

BUF1

BUF1N

V

SSA3

Fig.10 ADC1 buffer input and V

handbook, halfpage

V

DDD1

CLK1

CLK1N

20
kΩ

20
kΩ

oref1

1.4 V

0.42 V

MGM871

output.

V

oref2

BUF2

BUF2N

V

SSA4

Fig.11 ADC2 buffer input and V

handbook, halfpage

V

DDD2

CLK2

CLK2N

20
kΩ

20
kΩ

oref2

1.4 V

0.42 V

MGM872

output.

V

SSD1

MGM873

Fig.12 ADC1 clock buffer input.

1999 Sep 16 18

V

SSD2

MGM874

Fig.13 ADC2 clock buffer input.

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

handbook, halfpage

100 Ω

MGM875

Fig.14 DPGA1 buffer output.

V

DDA3

V

DDA1

DPGA1
DPGA1N

V

SSA1

handbook, halfpage

TDA8798

100 Ω

MGM876

Fig.15 DPGA2 buffer output.

V

DDA4

V

DDA2

DPGA2
DPGA2N

V

SSA2

handbook, halfpage

handbook, halfpage

V

DDD1

SMODE
SEN1
SEN2
SDATA
SCLK

V

SSD1

MGM877

Fig.16 Serial Interface inputs.

V

DDO2

OE

SR

handbook, halfpage

handbook, halfpage

V

DDD2

TE

DPGAEN

V

SSD2

MGM878

Fig.17 TE and DPGAEN inputs.

V

OE

A0N

DDO1

A0

V

SSO2

MGM879

Fig.18 OE and SR inputs.

1999 Sep 16 19

V

SSO1

MGM880

Fig.19 ADC1 A0 to A7 outputs.

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

handbook, halfpage

OE

B0N

MGM881

Fig.20 ADC2 B0 to B7 outputs. Fig.21 V

V

DDO2

B0

V

SSO2

1.24 V

ref1

FCE268

output.

TDA8798

V

DDA3

V

ref1

V

SSA3

1.24 V

Fig.22 V

ref2

FCE269

output.

V

DDA4

V

ref2

V

SSA4

1999 Sep 16 20

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

PACKAGE OUTLINE

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

c

y

X

A

48 33

49

Z

32

E

TDA8798

SOT314-2

e

w M

b

p

e

pin 1 index

1.45

1.35

b

0.25

17

16

Z

w M

p

D

H

D

p

0.27

0.18

0.17

0.12

D

(1)

(1) (1)(1)

cE

D

10.1

10.1

9.9

9.9

v M

B

v M

B

0 2.5 5 mm

scale

eH

H

12.15

0.5

11.85

64

1

DIMENSIONS (mm are the original dimensions)

mm

A

A1A2A3b

max.

0.20

1.60

0.05

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

D

A

E

H

12.15

11.85

E

LL

E

A

A

0.75

0.45

2

p

(A )

A

1

L

detail X

Z

D

0.12 0.11.0 0.2

1.45

1.05

3

L

p

Zywv θ

E

1.45

1.05

o

7

o

0

θ

OUTLINE

VERSION

SOT314-2

IEC JEDEC EIAJ

REFERENCES

1999 Sep 16 21

EUROPEAN

PROJECTION

ISSUE DATE

95-12-19
97-08-01

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with
DPGA

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesavery brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wavesoldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing,stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

TDA8798

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

1999 Sep 16 22

Philips Semiconductors Objective specification

Dual 8-bit, 100 Msps A/D converter with

TDA8798

DPGA

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)
(5)

SOLDERING METHOD

(1)

suitable

suitable
suitable

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Sep 16 23

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252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545004/25/02/pp24 Date of release: 1999 Sep 16 Document order number: 9397 750 05466