Datasheet TDA8793HL-C1 Datasheet (Philips)

DATA SH EET

Preliminary specification
Supersedes data of 1998 May 14
File under Integrated Circuits, IC02

1999 Oct 06

INTEGRATED CIRCUITS

TDA8793

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

1999 Oct 06 2

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

FEATURES

• 8-bit low-power ADC (170 mW typical)

• 2.7 to 3.6 V operation

• Sampling rate up to 100 Msps

• Track-and-hold circuit

• CMOS/TTL compatible digital inputs and outputs

• Internal references

• Adjustable full scale range possibility with external

reference

• Power-down mode; 5 mW.

APPLICATIONS

• Radio communications

• Digital data storage read channels

• Medical imaging

• Digital instrumentation.

GENERAL DESCRIPTION

The TDA8793 is an 8-bit low-power Analog-to-Digital
Converter (ADC) which includes a track-and-hold circuit
and internal references. The device converts an analog
input signal, up to 100 MHz, into 8-bit binary codes at a
maximum sample rate of 100 Msps. All digital inputs and
outputareTTL/CMOScompatible.Asinewaveclockinput
signal can also by used.

The Power-down mode enables the device power
consumption to be reduced to 5 mW.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 2.7 3.0 3.6 V

V

CCD

digital supply voltage 2.7 3.0 3.6 V

V

CCO

output stages supply voltage 2.7 3.0 3.6 V

I

CCA

analog supply current operating 32 40 48 mA

standby 0 5 100 µA

I

CCD

digital supply current operating 13 16 22 mA

standby 0 0.65 1.1 mA

I

CCO

output stages supply current − 0.1 − mA

INL integral non-linearity ramp input; f

CLK

= 2 MHz;

V

CCA=VCCD

=3V

−±0.8 tbf LSB

DNL differential non-linearity ramp input; f

CLK

= 2 MHz;

V

CCA=VCCD

=3V

−±0.25 tbf LSB

f

CLK(max)

maximum clock input frequency 100 −−MHz

P

tot

total power dissipation VCC=3V − 170 − mW

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8793HL LQFP32 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1

1999 Oct 06 3

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

BLOCK DIAGRAM

handbook, full pagewidth

MGR016

TRACK-AND-

HOLD

ADC

LATCHES

CMOS

OUTPUTS

V

REFOUT

= 1.85 V

V

SDN

= 1.25 V

REFERENCE

3

4

INN

5

REFOUT

2

REFIN

32

SDN

8

STDBY

INP

D7

26

D6

25

D5

24

D4

23

D3

18

D2

17

D1

16

D0

15

CLK

11

12

TEN

DEC

31

AGND

6

7

V

CCA

10

V

CCD

22

V

CCO2

20

V

CCO1

CLOCK DRIVER

DGND

9

OGND119ODGND2

21

TDA8793

Fig.1 Block diagram.

1999 Oct 06 4

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
REFIN 2 reference input for ADC
INN 3 negative input
INP 4 positive input
REFOUT 5 reference for AC coupling
AGND 6 analog ground
V

CCA

7 analog supply voltage
STDBY 8 standby mode input
DGND 9 digital ground
V

CCD

10 digital supply voltage
CLK 11 clock input
TEN 12 track enable input (active LOW)
n.c. 13 not connected
n.c. 14 not connected
D0 15 data output bit 0 (LSB)
D1 16 data output bit 1

D2 17 data output bit 2
D3 18 data output bit 3
OGND1 19 output ground 1
V

CCO1

20 output supply voltage 1
OGND2 21 output ground 2
V

CCO2

22 output supply voltage 2
D4 23 data output bit 4
D5 24 data output bit 5
D6 25 data output bit 6
D7 26 data output bit 7 (MSB)
n.c 27 not connected
n.c 28 not connected
n.c 29 not connected
n.c 30 not connected
DEC 31 decoupling
SDN 32 stabilized decoupling node

SYMBOL PIN DESCRIPTION

handbook, full pagewidth

TDA8793

MGR017

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

n.c.

REFOUT

STDBY

V

CCA

INN

AGND

DGND

CLK

n.c.

V

CCD

D0

D7

n.c.

SDN

n.c.

V

CCO2

V

CCO1

n.c.

D4

D3

D2

OGND2

DEC

n.c.

D1

D6

D5

OGND1

n.c.

TEN

INP

REFIN

Fig.2 Pin configuration.

1999 Oct 06 5

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage −0.3 +7.0 V

V

CCD

digital supply voltage −0.3 +7.0 V

V

CCO

output stages supply voltage −0.3 +7.0 V

∆V

CC

supply voltage differences between

V

CCA

and V

CCD

−1.0 +1.0 V

V

CCO

and V

CCD

−1.0 +1.0 V

V

CCA

and V

CCO

−1.0 +1.0 V

V

INP, INN

input voltage range referenced to AGND −0.3 +7.0 V

I

O

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

ambient temperature 0 70 °C

T

j

junction temperature −−°C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 94 K/W

1999 Oct 06 6

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

CHARACTERISTICS

V

CCA=V7

to V6= 2.7 to 3.6 V; V

CCD=V10

to V9= 2.7 to 3.6 V; V

CCO=V20

(or V22) to V19 (or V21) = 2.7 to 3.6 V;

AGND to DGND and OGND shorted together; V

CCA

to V

CCD

= −0.15 to +0.15 V; V

CCD

to V

CCO

= −0.15 to +0.15 V;

V

CCA

to V

CCO

= −0.15 to +0.15 V; T

amb

= 0 to 70 °C; typical values measured at V

CCA=VCCD=VCCO

= 3.0 V and

T

amb

=25°C; single-ended input; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

analog supply voltage 2.7 3.0 3.6 V

V

CCD

digital supply voltage 2.7 3.0 3.6 V

V

CCO

output stages supply voltage 2.7 3.0 3.6 V

I

CCA

analog supply current 32 40 48 mA

I

CCD

digital supply current 13 16 22 mA

I

CCO

output stages supply current fi= ramp input − 0.1 tbf mA

f

i

= 20 MHz − 4 tbf mA
Internal reference (pin SDN); note 1
V

ref

reference voltage 1.21 1.25 1.29 V

V

reg

line regulation voltage 2.7 < V

CCA

< 3.6 V − 0.4 3 mV

TC temperature coefficient − 18 − ppm/K

I

L

load current −1 −−mA

Internal reference (pin REFOUT)

V

o(ref)

reference voltage 1.76 1.82 1.88 V

V

o(reg)

line regulation voltage 2.7 < V

CCA

< 3.6 V − 1.5 4 mV

TC temperature coefficient − 18 − ppm/K

I

L

load current −1 −−mA
Adjustable full scale input (pin REFIN); see Figs 3, 4, and 7
I

ref

input current V

REFIN

= 1.25 V −−0.87 − mA
Clock input (pin CLK); note 2
V

IL

LOW-level input voltage 0 − 0.8 V

V

IH

HIGH-level input voltage 2 − V

CCD

V

I

IL

LOW-level input current V

CLK

=0 −2 − +2 µA

I

IH

HIGH-level input current V

CLK=VCCD

−−5µA

t

r

clock rise time 0.75 − tbf ns

t

f

clock fall time 0.75 − tbf ns

Z

i

input impedance f

CLK

= 100 MHz − 32 − kΩ

C

i

input capacitance f

CLK

= 100 MHz − 2 − pF
Standby input (pin STDBY); see Table 1
V

IL

LOW-level input voltage 0 − 0.8 V

V

IH

HIGH-level input voltage 2 − V

CCD

V

I

IL

LOW-level input current V

STDBY

=0 −5 −−µA

I

IH

HIGH-level input current V

STDBY=VCCD

−−5µA

1999 Oct 06 7

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

Track enable input (pin TEN); see Table 2
V

IL

LOW-level input voltage 0 − 0.8 V

V

IH

HIGH-level input voltage 2 − V

CCD

V

I

IL

LOW-level input current V

TEN

=0 −5 −−µA

I

IH

HIGH-level input current V

TEN=VCCD

−−5µA

Inputs (pins INP and INN); analog input voltage referenced to AGND; V

REFIN

= 1.27 V; see Table 3

V

i(p-p)

input voltage range
(peak-to-peak value)

Vi=V

INP

− V

INN

;

T

amb

=25°C

0.90 0.97 1.040 V

∆T

CI

input voltage range drift − 0.5 − mV/K

V

i(os)

input offset voltage output code = 127 −25 − +25 mV

Z

i

input impedance f

INP

= 50 MHz − 90 − kΩ

C

i

input capacitance f

INP

= 50 MHz − 2 − pF

I

IL

LOW-level input current V

INP=VREFOUT

+ 0.5 −1 −−µA

V

INP=VREFOUT

− 0.5 −1 −−µA

I

IH

HIGH-level input current V

INP=VREFOUT

+ 0.5 −−40 µA

V

INP=VREFOUT

− 0.5 −−40 µA

Adjustable full scale range; V

REFIN

= 1.2 to 1.35 V; see Fig.3

V

I(p-p)

input voltage range
(peak-to-peak value)

Vi=V

INP

− V

INN

;

T

amb

=25°C

− 1 − V

Voltage controlled regulator input pin V

REFIN

(referenced to AGND); note 3

V

i(ref)

reference voltage tbf 1.25 tbf V

I

i(ref)

input current on pin V

REFIN

− tbf 1.1 mA

Outputs; ADC data outputs

V

OL

LOW-level output voltage IO=1mA −−0.5 V

V

OH

HIGH-level output voltage IO= −0.4 mA V

CCO

− 0.5 − V

CCO

V

C

L

output load capacitance −−10 pF

δv/δt slew rate 10% to 90%; C

L

=10pF − 1.2 − V/ns
Switching characteristics; note 2; see Table 1
f

CLK(min)

minimum clock frequency track = LOW −−6 MHz

f

CLK(max)

maximum clock frequency 100 −−MHz

t

W(CLKH)

clock pulse width HIGH 4 −−ns

t

W(CLKL)

clock pulse width LOW 4 −−ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Oct 06 8

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

Analog signal processing; note 3; see Figs 4, 5, 6 and 7
INL integral non-linearity ramp input; f

CLK

= 2 MHz;

V

CCA=VCCD

=3V

−±0.8 tbf LSB

DNL differential non-linearity ramp input; f

CLK

= 2 MHz;

V

CCA=VCCD

=3V

−±0.25 tbf LSB

S/N signal-to-noise ratio (full scale) without harmonics;

f

CLK

= 100 MHz

f

i

= 20 MHz 42 45 − dB

f

i

= 50 MHz − 45 − dB

B

W(−3dB)

−3 dB analog bandwidth − 350 − MHz

THD total harmonics distortion f

i

= 20 MHz −−56 − dB

f

i

= 50 MHz −−52 − dB

H

fund(FS)

full scale fundamental harmonics f

CLK

= 100 MHz

f

i

= 20 MHz −−0dB

f

i

= 50 MHz −−0dB

H

D2(FS)

second harmonic distortion (full
scale) all components included

differential inputs;
f

CLK

= 100 MHz

f

i

= 20 MHz − 66 − dB

f

i

= 50 MHz − 57 − dB

single-ended input;
f

CLK

= 100 MHz

f

i

= 20 MHz − 66 − dB

f

i

= 50 MHz − 55 − dB

H

D3(FS)

third harmonic distortion (full scale)
all components included

differential inputs;
f

CLK

= 100 MHz

f

i

= 20 MHz − 64 − dB

f

i

= 50 MHz − 61 − dB

single-ended input;
f

CLK

= 100 MHz

f

i

= 20 MHz − 64 − dB

f

i

= 50 MHz − 59 − dB

SFDR spurious free dynamic range f

CLK

= 100 MHz dB

f

i

= 20 MHz − 57 − dB

f

i

= 50 MHz − 54 − dB

EB effective bits f

CLK

= 100 MHz; note 4 bits

f

i

= 20 MHz 7.0 7.4 − bits

f

i

= 50 MHz − 7.2 − bits

Data timing; f

CLK

= 100 MHz; CL=10pF;see Fig.8

t

ds

sampling delay −−1.5 ns

t

h

output hold time 3 −−ns

t

d

output delay time − 58ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Oct 06 9

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

Notes

1. It is possible to use the reference output voltage (pin SDN) to drive other analog circuits under the limits indicated.

2. In addition to a good layout of the digital and analog grounds, it is recommended that the rise and fall times of the
clock must be not less than 0.75 ns.

3. It is possible with an external reference voltage connected to REFIN pin to adjust the ADC input range. The input
range variation will be fixed.

4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 k acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(nyquist frequency). Conversion to signal-to-noise ratio: SINAD = 6.02 × EB + 1.76 dB.

Table 1 Standby selection

Table 2 Track-and-hold selection

Table 3 Output coding and input voltage (typical values; referenced to AGND); V

REFIN

= 1.27 V

PIN STDBY D0 TO D7 I

CCA+ICCD

LOW inactive 56 mA

HIGH active; output logic state LOW 0.7 mA

PIN

TEN TRACK-AND-HOLD

LOW active

HIGH inactive; tracking mode

STEP V

INP

(V) V

INN

(V)

BINARY OUTPUT BITS

D7 D6 D5 D4 D3 D2 D1 D0

Underflow <1.6 >2.1 0 0000000

0 1.6 2.1 00000000

1 ... ... 00000001

... ... ... ... ... ... ... ... ... ... ...

127 1.85 1.85 ... ... ... ... ... ... ... ...

... ... ... ... ... ... ... ... ... ... ...

254 ... ... 11111110

255 2.1 1.6 11111111

Overflow >2.1 <1.6 1 1111111

1999 Oct 06 10

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

handbook, halfpage

1.15 1.25
V

REFIN

(V)

V

i(p-p)

(V)

1.35 1.45

1.4

1.2

0.8

0.6

1

FCE421

Fig.3 ADC input voltage as a function of V

REFIN

reference input voltage.

Typical values measured at V

CCA=VCCD=VCCO

= 3.0 V,

f

CLK

= 100 MHz, T

amb

=25°C and single-ended input.

handbook, halfpage

1.15 1.25

(1)

(2)

V

REFIN

(V)

SFDR

S/N

(dB)

1.35 1.45

67

42

62

57

52

47

FCE423

Fig.4 Noise and spurious free dynamic range as

a function of V

REFIN

reference input voltage.

(1) SFDR
(2) S/N
Typical values measured at V

CCA=VCCD=VCCO

= 3.0 V,

f

CLK

= 100 MHz, T

amb

=25°C and single-ended input.

handbook, halfpage

55

45

47

49

51

53

FCE419

1

(3)

10

fi (MHz)

THD

S/N

(dB)

10

2

(1)

(2)

Fig.5 Noise and distortion as a function of input

frequency.

(1) THD for differential inputs
(2) THD for single-ended input
(3) S/N
Typical values measured at V

CCA=VCCD=VCCO

= 3.0 V,

f

CLK

= 100 MHz and T

amb

=25°C.

handbook, halfpage

8

5.5

6

6.5

7

7.5

FCE420

110

EB

(bits)

10

2

(1)

(2)

fi (MHz)

Fig.6 Effective bits as a function of input frequency.

(1) Differential inputs
(2) Single-ended input
Typical values measured at V

CCA=VCCD=VCCO

= 3.0 V,

f

CLK

= 100 MHz and T

amb

=25°C.

Fig.6 Effective bits as a function of input frequency.

1999 Oct 06 11

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

handbook, halfpage

1.15

8

7

6

5

1.25 1.35
V

REFIN

(V)

EB

(bits)

1.45

FCE422

Fig.7 Effective bits as a function of V

REFIN

reference input voltage.

Typical values measured at V

CCA=VCCD=VCCO

= 3.0 V,

f

CLK

= 100 MHz, T

amb

=25°C and single-ended input.

handbook, full pagewidth

t

ds

CLK

MGR018

50 %

HIGH

LOW

50 %

HIGH

LOW

sample N

sample N + 1 sample N + 2

V

l

DATA

D0 to D7

t

h

t

d

t

CPH

t

CPL

DATA

N − 1

DATA

N − 2

DATA
N + 1

DATA

N

Fig.8 Timing diagram.

1999 Oct 06 12

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

APPLICATION INFORMATION

handbook, full pagewidth

MGR019

50 Ω 50 Ω

2

31

3
4

5

100 nF

10 nF

220 nF

100 nF

input

REFIN

DEC

32

SND

INN
INP

REFOUT

100 nF

TDA8793

Fig.9 Application diagram for single-ended input mode with internal reference.

handbook, full pagewidth

MGR020

50 Ω 50 Ω

2

31

3
4

5

100 nF

10 nF

220 nF

100 nF

input

REFIN

DEC

INN
INP

REFOUT

100 nF

EXTERNAL

REFERENCE

1.25 V

TDA8793

Fig.10 Application diagram for single-ended input mode with external reference.

1999 Oct 06 13

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

handbook, full pagewidth

MGR021

50 Ω

50 Ω

2

31

3

4
5

100 nF

220 nF

220 nF

100 nF

input 1

input 2

REFIN

DEC

32

SND

INN

INP

REFOUT

100 nF

TDA8793

Fig.11 Application diagram for differential input mode with internal reference.

handbook, full pagewidth

MGR022

100 Ω 100 Ω

2

31

3

4

5

100 nF

100 nF

input

REFIN

DEC

32

1 : 1

SND

INN

INP

REFOUT

100 nF

100 nF

220 nF

TDA8793

Fig.12 Application diagram for differential input mode using a transformer.

1999 Oct 06 14

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

PACKAGE OUTLINE

0.2

UNIT

A

max.

A

1A2A3bp

cE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

1.60

0.15

0.05

1.5

1.3

0.25

0.27

0.17

0.18

0.12

5.1

4.9

0.5

7.15

6.85

1.0

0.95

0.55

7
0

o
o

0.12 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT401-1

95-12-19
97-08-04

D

(1) (1)(1)

5.1

4.9

H

D

7.15

6.85

E

Z

0.95

0.55

D

b

p

e

E

B

8

D

H

b

p

E

H

v M

B

D

Z

D

A

Z

E

e

v M

A

X

1

32

25

24

17

16

9

θ

A

1

A

L

p

detail X

L

(A )

3

A

2

y

w M

w M

0 2.5 5 mm

scale

LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm

SOT401-1

c

pin 1 index

1999 Oct 06 15

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesaverybriefinsightto a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboardbyscreenprinting,stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfour sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Oct 06 16

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wavesoldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1999 Oct 06 17

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

NOTES

1999 Oct 06 18

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

NOTES

1999 Oct 06 19

Philips Semiconductors Preliminary specification

8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)

TDA8793

NOTES

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable andmaybe changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

68

Philips Semiconductors – a w orldwide compan y

For all other countries apply to: Philips Semiconductors,

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
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Middle East: see Italy

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Printed in The Netherlands 545004/02/pp20 Date of release: 1999 Oct 06 Document order number: 9397 750 06028