Datasheet TDA8792M-C2-R1, TDA8792M-C2, TDA8792M-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1995 Apr 26
File under Integrated Circuits, IC02

1996 Feb 21

INTEGRATED CIRCUITS

TDA8792

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

1996 Feb 21 2

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

FEATURES

• 8-bit resolution

• Sampling rate up to 25 MHz

• 30 MHz input signal bandwidth (full scale)

• High signal-to-noise ratio over a large analog input

frequency range (7.3 effective bits at 4.43 MHz
full-scale input at f

clk

= 25 MHz)

• CMOS compatible digital inputs

• External reference voltage regulator

• Power dissipation only 53 mW (typical)

• Standby mode (only 1.2 mW typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

APPLICATIONS

Analog-to-digital conversion for:

• General purpose

• Hand-held equipment

• Mobile telecommunication

• Instrumentation

• Video.

GENERAL DESCRIPTION

The TDA8792 is a 8-bit analog-to-digital converter (ADC)
for low-voltage, portable applications. It operates at 3.3 V
and converts the analog input signal into 8-bit
binary-coded digital words at a maximum sampling rate of
25 MHz. The output data is valid after a delay of 6 clock
cycles.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

analog supply voltage 2.85 3.3 3.6 V

V

DDD

digital supply voltage 2.70 3.3 3.6 V

V

DDO

output stages supply voltage 2.5 3.3 3.6 V

I

DDA

analog supply current − 12 20 mA

I

DDD

digital supply current − 36mA

I

DDO

output stages supply current f

clk

= 25 MHz; CL= 15 pF;

ramp input

− 12mA

INL integral non-linearity f

clk

= 25 MHz; ramp input −±0.4 ±0.8 LSB

DNL differential non-linearity f

clk

= 25 MHz; ramp input −±0.3 ±0.75 LSB

f

clk(max)

maximum clock frequency 25 −−MHz

P

tot

total power dissipation f

clk

= 25 MHz; CL= 15 pF;

ramp input

− 53 100 mW

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8792M SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

1996 Feb 21 3

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

BLOCK DIAGRAM

Fig.1 Block diagram.

dbook, full pagewidth

1

2

3

4

5

6

7

8

8

9

10

12

V

DDO

V

SSO

STDBY

22

23

24

OUTPUT
BUFFER

DECODER

LATCHES

MLD119 - 1

D014

D1 15

D2 16

D317

D4 18

D519

D620

21 D7

OE 13

TDA8792

data outputs

LSB

MSB

DDD

V

SSD2

V

DDA

bias

V

RT

V

RM

V

RB

V

SSA2

V

SSA1

V

I

V

I

CLK

DAC

7 x 8

OFFSET

COMPENSATED

COMPARATORS

REFERENCE

LADDER

1996 Feb 21 4

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

PINNING

SYMBOL PIN DESCRIPTION

STDBY 1 standby input
V

DDD

2 digital supply voltage (+3.3 V)

V

SSD2

3 digital ground 2

V

SSA1

4 analog ground 1

V

I

5 analog input voltage

V

DDA

6 analog supply voltage (+3.3 V)

I

bias

7 bias current input

V

RT

8 reference voltage TOP input

V

RM

9 reference voltage MIDDLE

V

RB

10 reference voltage BOTTOM input
n.c. 11 not connected
V

SSA2

12 analog ground 2
OE

13

output enable input (CMOS level

input, active LOW)
D0 14 data output; bit 0 (LSB)
D1 15 data output; bit 1
D2 16 data output; bit 2
D3 17 data output; bit 3
D4 18 data output; bit 4
D5 19 data output; bit 5
D6 20 data output; bit 6
D7 21 data output; bit 7 (MSB)
V

DDO

22

positive supply voltage for output

stage (+3.3 V)
V

SSO

23 output ground

CLK 24 clock input

Fig.2 Pin configuration.

handbook, halfpage

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21

20
19
18
17
16
15
14
13

TDA8792



CLK
V

STDBY

V

n.c.

D1

D7
D6
D5
D4
D3
D2

D0

OE

V

I

bias

V

RM

V

RB

MLD120 - 1

V

RT

DDD

V

SSD2

V

SSA1

V

SSA2

V

DDA

V

I

SSO

DDO

1996 Feb 21 5

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

DDA

, V

DDD

and V

DDO

may have any value between −0.5 V and +5.0 V provided that the

differences ∆V

DD1

, ∆V

DD2

and ∆V

DD3

are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

analog supply voltage note 1 −0.5 +5.0 V

V

DDD

digital supply voltage note 1 −0.5 +5.0 V

V

DDO

output stages supply voltage note 1 −0.5 +5.0 V

∆V

DD1

supply voltage differences between
∆V

DD1=VDDA

− V

DDD

−0.3 +0.3 V

∆V

DD2

supply voltage differences between
∆V

DD2=VDDD

− V

DDO

−1.0 +1.0 V

∆V

DD3

supply voltage differences between
∆V

DD3=VDDA

− V

DDO

−1.0 +1.0 V

V

I

input voltage referenced to V

SSA

−0.5 +5.0 V

V

clk(p-p)

AC input voltage for switching
(peak-to-peak value)

referenced to V

SSD

− V

DDD

V

I

O

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature −20 +75 °C

T

j

junction temperature − +125 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 119 K/W

1996 Feb 21 6

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

CHARACTERISTICS

V

DDA=V6

to V

4,12

= 2.85 to 3.6 V; V

DDD=V2

to V3and V1= 2.7 to 3.6 V; V

DDO=V22

to V23= 2.5 to 3.6 V;

V

SSA,VSSD

and V

SSO

shorted together; V

DDA

to V

DDD

= −0.15 to +0.15 V; f

clk

= 25 MHz; 50% duty factor; VIL=0V;

VIH=V

DDD

; CL= 15 pF; T

amb

= 0 to +70 °C; typical values measured at V

DDA=VDDD=VDDO

= 3.3 V and T

amb

=25°C;

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply

V

DDA

analog supply voltage 2.85 3.3 3.6 V

V

DDD

digital supply voltage 2.7 3.3 3.6 V

V

DDO

output stages supply voltage 2.5 3.3 3.6 V

I

DDA

analog supply current − 12 20 mA

I

DDD

digital supply current − 36mA

I

DDO

output stages supply current CL= 15 pF; ramp input − 12mA

Inputs

C

LOCK INPUT CLK (REFERENCED TO V

SSD

); note 1

V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

DDD

V

I

IL

LOW level input current V

clk

= 0.4 V −10 −−µA

I

IH

HIGH level input current V

clk

= 2.7 V −−10 µA

C

I

input capacitance − 10 − pF

INPUTS OE AND STDBY (REFERENCED TO V

SSD

); see Tables 2 and 3

V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

DDD

V

I

IL

LOW level input current VIL= 0.4 V −10 −−µA

I

IH

HIGH level input current VIH= 2.7 V −−+10 µA

VI(ANALOG INPUT VOLTAGE REFERENCED TO V

SSA

)

I

IL

LOW level input current VI=0V −20 −−µA

I

IH

HIGH level input current VI= 1.5 V −−+20 µA

Z

I

input impedance fi= 4.43 MHz − 35 − kΩ

C

I

input capacitance fi= 4.43 MHz − 5 − pF
Reference voltages for the resistor ladder; see Table 1
V

RB

reference voltage BOTTOM 0 − 0.15 V
V

RT

reference voltage TOP 1.4 − 1.6 V
V

diff

differential reference voltage VRT− V

RB

1.25 1.5 1.6 V

I

ref

reference current − 1.3 − mA
R

LAD

resistor ladder − 1250 −Ω
TC

RLAD

temperature coefficient of the resistor

ladder

− 1 −Ω/K

1996 Feb 21 7

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

Outputs

DIGITAL OUTPUTS D7 TO D0 (REFERENCED TO V

SSO

)

V

OL

LOW level output voltage IO=1mA 0 − 0.4 V
V

OH

HIGH level output voltage IO= −1mA V

DDO

− 0.4 − V

DDO

V

I

OZ

output current in 3-state mode 0.4V<VO<V

DDO

−10 − +10 µA

Switching characteristics

C

LOCK INPUT CLK (V

DDA

= 3.15 TO 3.45 V; V

DDD

= 3.15 TO 3.45 V); see Fig.3 and note 1

f

clk(max)

maximum clock frequency 25 −−MHz
f

clk(min)

minimum clock frequency 0.5 −−MHz
t

CPH

clock pulse width HIGH 16 −−ns
t

CPL

clock pulse width LOW 16 −−ns

Analog signal processing

L

INEARITY

INL integral non-linearity ramp input −±0.4 ±0.8 LSB
DNL differential non-linearity ramp input −±0.3 ±0.75 LSB

B

ANDWIDTH (V

DDA

= 3.15 TO 3.45 V; V

DDD

= 3.15 TO 3.45 V); T

AMB

=25°C

B analog bandwidth full-scale sine wave;

note 2

20 30 − MHz

small signal at mid-scale;
Vi= ±10 LSB at
code 128; note 2

− 35 − MHz

t

STLH

analog input settling time LOW-to-HIGH full-scale square wave;

Fig.5; note 3

− 812ns

t

STHL

analog input settling time HIGH-to-LOW full-scale square wave;

Fig.5; note 3

− 812ns

HARMONICS
h

1

fundamental harmonics (full scale) fi= 4.43 MHz −−0dB
h

all

harmonics (full scale); all components fi= 4.43 MHz

second harmonics −−61 − dB
third harmonics −−61 − dB

THD total harmonic distortion f

i

= 4.43 MHz −−58 − dB
SIGNAL-TO-NOISE RATIO; see Figs 6 and 11; note 4
S/N signal-to-noise ratio (full scale) without harmonics;

f

clk

= 25 MHz;

fi= 4.43 MHz

− 46 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Feb 21 8

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.

2. The analog bandwidth is defined as the maximum full-scale input sine wave frequency which can be applied to the
device. No glitches greater than 8 LSBs are observed in the reconstructed signal neither is there any significant
attenuation.

3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.

4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

5. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.

6. Output data acquisition: the output data is available after the maximum delay time of t

d

. In the event of 25 MHz clock
operation, the hardware design must be taken into account the td and th limits with respect to the input characteristics
of the acquisition circuit.

7. Maximum value standby mode start-up output delay time (HIGH-to-LOW transition): .

E

FFECTIVE BITS; see Figs 6 and 11;note4

EB effective bits f

clk

= 25 MHz

f

i

= 2.0 MHz − 7.4 − bits

f

i

= 4.43 MHz − 7.3 − bits

f

i

= 7.5 MHz − 7.2 − bits

f

i

= 10 MHz − 7.0 − bits
DIFFERENTIAL GAIN; see note 5
G

diff

differential gain f

clk

= 25 MHz;

PAL modulated ramp

− 1.5 − %

DIFFERENTIAL PHASE; see note 5

ϕ

diff

differential phase f

clk

= 25 MHz;

PAL modulated ramp

− 0.5 − deg

Timing (f

clk

= 25 MHz); see Fig.3 and note 6

t

ds

sampling delay time −−2ns

t

h

output hold time 6 −−ns

t

d

output delay time 8 13 25 ns
3-state output delay times; see Fig.4
t

dZH

enable HIGH − 17 28 ns
t

dZL

enable LOW − 22 30 ns
t

dHZ

disable HIGH − 20 28 ns
t

dLZ

disable LOW − 22 30 ns

Standby mode output delay times

t

dSTBLH

standby (LOW-to-HIGH transition) −−200 ns
t

dSTBHL

start-up (HIGH-to-LOW transition) −−note 7 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

100

7000

f

clk

(MHz)

------------------------

+

1996 Feb 21 9

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

Table 1 Output coding and input voltage (typical values; referenced to V

SSA

)

STEP V

I(p-p) (V)

BINARY OUTPUT BITS

D7 D6 D5 D4 D3 D2 D1 D0

Underflow <000000000
0 0 00000000
1 . 00000001

. . ........

. . ........

254 . 1 1 1 1 1 1 1 0
255 1.5 11111111
Overflow >1.5 11111111

Table 2 Mode selection

OE D7 TO D0

1 high impedance
0 active; binary

Table 3 Standby selection

STDBY D7 TO D0 I

DDA+IDDD

(typ.)

1 LOW 0.4 mA
0 active 15 mA

Fig.3 Timing diagram.

ds

t

sample N 2

sample N 1

CLK

MLD121

sample N 6

1.4 V

V

l

DATA
D0 to D7

t

d

t

h

CPH

t

CPL

t

DATA

N 1

DATA

N 5

DATA

N 6

0.4 V

0.4 V

DATA

N

V

DDO

50%

1996 Feb 21 10

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

Fig.4 Timing diagram and test conditions of 3-state output delay time.

fOE= 100kHz.

handbook, full pagewidth

MLD122

50 %

50 %

HIGH

LOW

dZH

t

dHZ

t

50 %

HIGH

LOW

dZL

t

dLZ

t

10 %

90 %

output
data

V

DDD

output
data

3.3 kΩ

15 pF

S1

V

DDD

TDA8792

OE

OE

TEST

dLZ

t

dZL

t

dHZ

t

dZH

S1

DDD

V

DDD

V

GND
GND

t

1996 Feb 21 11

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

Fig.5 Analog input settling-time diagram.

MLD123

50 %

STLH

t

2 ns

code 0

code 255

I

50 %

2 ns

50 %

2 ns

STHL

t

50 %

2 ns

CLK

V

Fig.6 Typical Fast Fourier Transform (f

clk

= 25 MHz; fi= 4.43 MHz).

Effective bits: 7.42; THD =−57.27 dB;
Harmonic levels (dB): 2nd =−60.76; 3rd = −60.96; 4th = −76.17; 5th = −80.63; 6th = −66.96.

handbook, full pagewidth

12.5

0

120

0 3.13 4.69 6.25 9.38 10.91.56 7.82

MLD118

40

80

100

60

20

A

(dB)

f (MHz)

1996 Feb 21 12

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

INTERNAL PIN CONFIGURATIONS

Fig.7 Digital data outputs.

D7 to D0

MLD124

Fig.8 Analog inputs.

V

MLD125

DDA

V

SSA

V

I

Fig.9 Digital inputs.

handbook, halfpage

V

MLD126 - 1

DDD

V

SSD



OE,

CLK or STDBY



Fig.10 VRB, VRM and VRT.

handbook, halfpage

R

MLC859

V

RB

V

RM

V

DDA

V

SSA

V

RT

LAD

Fig.11 Bias current input.

MLD127

V

DDA

V

SSA

I

bias

1996 Feb 21 13

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

APPLICATION INFORMATION

Fig.12 Application diagram.

The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. The reference

ladder voltages can also be derived from a well regulated V

DDA

supply through a resistor bridge and a decoupled capacitor.

For applications where the input signal must remain well centred around middle scale, VRM must be decoupled and connected to analog input signal
(pin 5) through a resistor. The values must be defined in accordance with the input signal frequency in order to avoid direct coupling into the ADC ladder
(e.g. R = 5 kΩ and C = 100 nF).

(1) V

RB

, VRM and VRT are decoupled to V

SSA

.

(2) Pin 11 should be connected to V

SSA

in order to prevent noise influence.

handbook, full pagewidth

24

23

22

21

20

19

18

17

16

15

14

13

TDA8792

1

2

3

4

5

6

7

8

9

10

11

12

MLD128 - 1

100 nF

100 nF

100 nF

(1)

(1)

(1)

(2)

CLK

V

STDBY

V

n.c.

D1

D7

D6

D5

D4

D3

D2

D0

OE

V

I

bias

V

RM

V

RB

V

RT

DDD

V

SSD2

V

SSA1

V

SSA2

V

DDA

V

I

SSO

DDO

3.3 V

100 nF

100 nF

100 nF

22 kΩ

3.3 V

3.3 V

3.3 V

1996 Feb 21 14

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

PACKAGE OUTLINE

UNIT A1A2A

3

b

p

cD

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

8.4

8.0

5.4

5.2

0.65 1.25

7.9

7.6

0.9

0.7

0.8

0.4

8
0

o
o

0.13 0.10.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

1.03

0.63

SOT340-1 MO-150AG

93-09-08
95-02-04

X

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

(A )

3

A

112

24 13

0.25

y

pin 1 index

0 2.5 5 mm

scale

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm

SOT340-1

A

max.

2.0

1996 Feb 21 15

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

SOLDERING SSOP
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
cases reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from 215 to
250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering isnot recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds at between 270 and
320 °C.

1996 Feb 21 16

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1996 Feb 21 17

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

NOTES

1996 Feb 21 18

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

NOTES

1996 Feb 21 19

Philips Semiconductors Product specification

3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)

TDA8792

NOTES

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SCDS47 © Philips Electronics N.V. 1996

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Document order number: 9397 750 00675