Datasheet TDA8786, TDA8786A Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8786; TDA8786A

10-bit analog-to-digital interface for
CCD cameras

Preliminary specification
Supersedes data of 1996 May 15
File under Integrated Circuits, IC02

1997 May 20

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

FEATURES

• Correlated double sampling (CDS), AGC, soft clipper,
pre-blanking, 10-bit ADC and reference regulator
included

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 18 MHz

• AGC gain from 3.5 dB to 33.5 dB (in 0.1 dB steps)

• Programmable soft clipper for white compression

(starting at 40% of the input signal)

• Stand-by mode available for each block for power
saving applications (14 mW)

• 6 dB fixed gain analog output for analog iris control

• 8-bit and 10-bit DAC included for analog settings

• Low power consumption of only 400 mW (typ.)

• 5 V operation and 2.5 to 5 V operation for the digital

outputs

• Active control pulse: TDA8786 = HIGH;
TDA8786A = LOW

• TTL compatible inputs, TTL and CMOS compatible
outputs.

TDA8786; TDA8786A

GENERAL DESCRIPTION

The TDA8786; TDA8786A is a 10-bit analog-to-digital
interface for CCD cameras. The device includes a
correlated double sampling circuit, AGC, a soft clipper
circuit and a low power 10-bit analog-to-digital converter
(ADC) together with its reference voltage regulator.

The AGC and soft clipper circuits are controlled by on-chip
DACs via a serial interface.

A 10-bit DAC controls the ADC input clamp level.
A pre-blanking function is also included.
An additional DAC is provided for additional system

controls; its output voltage range is 1.4 V (p-p) which is
available at pin OFD.

APPLICATIONS

• CCD camera systems.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.5 4.75 5.5 V
digital supply voltage 4.5 4.75 5.5 V
digital outputs supply voltage 2.5 2.6 5.5 V
analog supply current − 73 − mA
digital supply current − 20 − mA
digital outputs supply current f

= 18 MHz;

CLK

− 1 − mA

CL= 20 pF; ramp input

ADC

res

V

iCDS(p-p)

G

CDS

f

ss(max)

AGC

dyn

S/N total signal-to-noise ratio from CDS input

ADC resolution − 10 − bits
CDS input voltage (peak-to-peak value) − 400 1200 mV
CDS output amplifier gain − 6 − dB
maximum clock frequency 18 −−MHz
AGC dynamic range − 30 − dB

CDS input = 600 mV (p-p) − 55 − dB

to ADC output

P

tot

total power consumption − 440 − mW

ORDERING INFORMATION

TYPE

NUMBER

TDA8786
TDA8786A

NAME DESCRIPTION VERSION

LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

PACKAGE

1997 May 20 2

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

BLOCK DIAGRAM

handbook, full pagewidth

STGE

AGND1

AMPOUT

PBK

AGCOUT

CLPOPB

PBIN

V

CCA1

PBOUT

ADCIN

CLPADC

IN2

47

19
5

4
2

7

1

8

6

9
10

11

IN1 AGND3

TDA8786

TDA8786A

1

OPTICAL

BLACK
CLAMP

1

CLAMP

V

TRACK-

AND-HOLD

CLIPPER

10-BIT DAC

CCA3

CDSP2 CDSP1 CLPCDS CLK

454846

TRACK-

AND-HOLD

TRACK-

AND-HOLD

CLAMP

CLAMP

SOFT

ref1

ref2

TRACK-

AND-HOLD

TRACK-

AND-HOLD

+

6 dB

AGC

9-BIT DAC

4-BIT DAC

REGULATOR

DGND2

CLOCK

GENERATOR

10-BIT ADC

SERIAL

INTERFACE

TDA8786; TDA8786A

V

V

CCD2

OUTPUTS

BUFFER

8-BIT DAC

OE

CCO

3738394041424344

36

OGND

35

D9

34

D8

33

D7

32

D6

31

D5

30

D4

29

D3

28

D2

27

D1

26

D0

25

DGND1

3

OFDOUT

14

12

V

ref

13 15 16 17 18

AGND2

V

CCA2

V

RB

DACOUT

V

RT

DEC1

Fig.1 Block diagram.

1997 May 20 3

23

STDBY

SEN

22

SCLK

21

SDATA

20

V

CCD1

24

MGE361

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

PINNING

SYMBOL PIN DESCRIPTION

CLPOPB 1 optical black clamp control pulse input (active HIGH for TDA8786, active LOW for TDA8786A)
PBK 2 pre-blanking control pulse input; if PBK is HIGH (LOW) the signal is replaced by the optical

black level for TDA8786 (TDA8786A)
OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface)
AMPOUT 4 CDS amplifier output (fixed gain = +6 dB)
AGND1 5 analog ground 1
V

CCA1

AGCOUT 7 AGC and soft clipper amplifier signal output
PBIN 8 optical black clamp and pre-blanking block signal input (from AGCOUT via a capacitor)
PBOUT 9 optical black clamp and pre-blanking block signal output
ADCIN 10 ADC analog signal input (from PBOUT or AGCOUT via a capacitor)
CLPADC 11 clamp control input for ADC analog input signal clamp (active HIGH for TDA8786 and active

V

ref

DACOUT 13 DAC output for ADC clamp level
AGND2 14 analog ground 2
V

CCA2

V

RB

V

RT

DEC1 18 decoupling 1 (decoupled to ground via a capacitor)
STGE 19 CDS offset storage
SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 4-bit DAC for soft clipper;

SCLK 21 serial clock input for the control DACs and their serial interface; see Table 1
SEN 22 enable input for the serial interface shift register (active when SEN = logic 0); see Table 1
STDBY 23 stand-by control pin (active HIGH); all the output bits are logic 0 when stand-by is enabled
V

CCD1

DGND1 25 digital ground 1
D0 26 ADC digital output 0 (LSB)
D1 27 ADC digital output 1
D2 28 ADC digital output 2
D3 29 ADC digital output 3
D4 30 ADC digital output 4
D5 31 ADC digital output 5
D6 32 ADC digital output 6
D7 33 ADC digital output 7
D8 34 ADC digital output 8
D9 35 ADC digital output 9 (MSB)
OGND 36 digital output ground

6 analog supply voltage 1

LOW for TDA8786A)

12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT)

15 analog supply voltage 2
16 ADC reference voltage (BOTTOM) code 0
17 ADC reference voltage (TOP) code 1023

additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the stand-by

mode per block; see Table 1)

24 digital supply voltage 1

1997 May 20 4

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

SYMBOL PIN DESCRIPTION

V

CCO

OE 38 output enable (LOW: digital outputs active; HIGH: digital outputs high impedance)
V

CCD2

DGND2 40 digital ground 2
CLK 41 ADC clock input
CLPCDS 42 CDS clamp control input (active HIGH for TDA8786; active LOW for TDA8786A)
CDSP1 43 CDS control pulse input 1 (active HIGH for TDA8786; active LOW for TDA8786A)
CDSP2 44 CDS control pulse input 2 (active HIGH for TDA8786; active LOW for TDA8786A)
V

CCA3

IN1 46 input signal 1 from CCD (usually black channel)
IN2 47 input signal 2 from CCD (usually video channel)
AGND3 48 analog ground 3

37 digital output supply voltage

39 digital supply voltage 2

45 analog supply voltage 3

CLPOPB

PBK
OFDOUT
AMPOUT

AGND1

V

CCA1

AGCOUT

PBIN

PBOUT

ADCIN

CLPADC

V

ref

CCA3

IN1

IN2
47

46

14

15

V

AGND2

CCA2

V

CDSP2

45

44

TDA8786

TDA8786A

16

17

RT

RB

V

V

AGND3

48

1
2
3
4
5
6
7
8

9
10
11
12

13

DACOUT

CLPCDS

CDSP1
43

42

18

19

DEC1

STGE

CLK
41

20

DGND2
40

21

SCLK

SDATA

CCD2

V

39

22

SEN

OE

V

38

23

STDBY

V

CCO

24 37

CCD1

36
35
34
33
32
31
30
29
28
27
26
25

MGE360

OGND
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DGND1

Fig.2 Pin configuration.

1997 May 20 5

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V

V

i

V

clk(p-p)

I

o

T

stg

T

amb

T

j

CC

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output stages supply voltage note 1 −0.3 +7.0 V
supply voltage difference

between V
between V
between V

CCA
CCA
CCD

and V
and V
and V

CCD
CCO
CCO

input voltage referenced to V
AC input voltage for switching

referenced to V

−1.0 +1.0 V

−1.0 +4.0 V

−1.0 +4.0 V

−0.3 +7.0 V

SSA

− V

SSD

CCD

V

(peak-to peak-value)
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature −20 +75 °C
junction temperature − 150 °C

Note

1. The supply voltages V

CCA

CCD

and V

may have any value between −0.3 and +7.0 V provided that the supply

CCO

, V

voltage difference ∆VCC remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 76 K/W

1997 May 20 6

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

CHARACTERISTICS

V

CCA=VCCD

= 4.75 V; V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.5 4.75 5.5 V
digital supply voltage 4.5 4.75 5.5 V
supply voltage output 2.5 2.6 5.5 V
analog supply current − 73 − mA
digital supply current − 20 − mA
supply current output CL= 20 pF on all data

Digital inputs

LOCK INPUT: CLK (REFERENCED TO DGND)

C
V

IL

V

IH

I

IL

I

IH

Z

I

C

I

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current V
HIGH level input current V
input impedance f

input capacitance f
INPUTS: CDSP1 AND CDSP2
V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.6 V

HIGH level input voltage 2.2 − V

LOW level input current VIL= 0.6 V −−100 −µA

HIGH level input current VIH= 2.2 V − 0 −µA
INPUTS: SEN, STDBY, CLPCDS, CLPOPB, PBK AND CLPADC
V

IL

V

IH

I

i

LOW level input voltage 0 − 0.6 V

HIGH level input voltage 2.2 − V

input current −2 − +2 µA

Correlated double sampling; CDS

V

iCDS(p-p)

CDS input amplitude

(peak-to-peak value)
I

STGE,IN1,IN2

input current pins 19, 46

and 47
t

CDS(min)

CDS control pulses

minimum active time

(HIGH for TDA8786,

LOW for TDA8786A)
t

h1

hold time IN1 compared to

control pulse CDSP1
t

h2

hold time of IN2 compared to

control pulse CDSP2

CCO

= 2.6 V; f

= 18 Msps; T

CLK

=25°C; unless otherwise specified.

amb

− 1 − mA

outputs; ramp input

= 0.8 V −1 − +1 µA

CLK

= 2.0 V −− 20 µA

CLK

= 18 MHz − 2 − kΩ

CLK

= 18 MHz − 2 − pF

CLK

− 400 1200 mV

−2 − +2 µA

f

iCDS1,2=fCLK(pix)

12 −−ns

− 1 − ns

−−0.5 − ns

CCD

CCD

CCD

V

V

V

1997 May 20 7

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Amplifier outputs

G

AMPOUT

Z

AMPOUT

V

AMPOUT(p-p)

V

AMPOUT(BL)

V

AGCOUT(p-p)

V

AGCOUT

Z

AGCOUT

I

AGCOUT

V

OPB(p-p)

V

OPB

Z

OPB

I

OPB

I

PBIN

G

AGCmin

G

AGCmax

V

AGCOUT

V

inflex(p-p)

CR

sc

output amplifier gain − 6 − dB

output amplifier impedance − 300 −Ω

output amplifier dynamic

− 2.4 − V

voltage (peak-to-peak value)

output amplifier black level

− 1.1 − V

voltage

AGC output amplifier

− 1800 − mV
dynamic voltage level
(peak-to-peak value)

AGC output amplifier

− 1.1 − V
black level voltage

AGC output amplifier output

at 10 kHz − 5 −Ω

impedance
AGC output static drive

static −− 1mA

current
optical black clamp and

− 1.8 − V
blanking block output
dynamic voltage
(peak-to-peak value)

optical black clamp and

− 1.4 − V
blanking block output
black level voltage

optical black clamp and

at 10 kHz −− 5Ω
blanking block output
impedance

OPB output

static −− 1mA
current drive

input current pin 8 −2 − +2 µA
minimum gain of AGC circuit AGC DAC input code = 00

− 3.5 − dB

(9-bit control)
maximum gain of AGC

circuit
AGC output amplifier

AGC DAC input code = ≥319

(9-bit control)

− 33.5 − dB

− 1.1 − V

black level voltage
voltage at soft clipper

inflexion point
(peak-to-peak value)

soft clipper compression
ratio

soft clipper 4-bit control DAC

input code = 00

soft clipper 4-bit control DAC

input code = 15

V

<V

i(sc)

V

i(sc)

>V

inflex
inflex

− 40 %
V

AGCOUT(p-p)

− 100 %
V

AGCOUT(p-p)

− 1.0 −

− 0.66 −

− V

− V

1997 May 20 8

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CLAMPS

G

mADC

ADC clamps
transconductance

G

mPBK

PBK clamp
transconductance

G

mCDS

CDS clamps
transconductance

V

PBINclamp

clamp voltage
at PBIN input

Analog-to-digital converter; ADC

f

CLK(max)

t

CPH

t

CPL

SR

CLK

maximum clock frequency 18 −−MHz
clock pulse width HIGH 15 −−ns
clock pulse width LOW 15 −−ns
clock input slew rate

(rising and falling edge)

V

iADC(p-p)

ADC input voltage level
(peak-to-peak value)

V

RB

ADC reference voltage
output code 0

V

RT

ADC reference voltage
output code 1023

I

ADCIN

input current pin 10 −2 − +2 µA
ILE integral linearity error f
DLE differential linearity error f
S/N signal-to-noise ratio f

at clamp level − 60 − mS

at clamp level − 60 − mS

at clamp level − 5.5 − mS

− 1.4 − V

10% to 90% 0.5 −−V/ns

− 1.8 − V

− 1.4 − V

− 3.2 − V

= 18 Msps; ramp input −±1.3 ±2.0 LSB

CLK

= 18 Msps; ramp input −±0.5 ±0.9 LSB

CLK

= 18 Msps: fi= 4.43 MHz− 56 − dB

CLK

THD total harmonic distortion f

= 18 Msps; fi= 4.43

CLK

MHz

t

ds

sampling delay time −− 5ns

Total chain timing (CDS + ADC + SOFT clipper + PRE BLANKING + ADC)

t

d

time delay between

CDSP1 and CLK

50% at rising edges CLK
and CDSP1:
transition full scale code 0 to
code 1023

1997 May 20 9

− 60 − dB

− 40 − ns

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

SYMBOL P ARAMETER CONDITIONS MIN. TYP . MAX. UNIT

Digital-to-analog converters (OFD DAC)

V

OFD(p-p)

additional 8-bit control DAC
(OFD) output voltage
(peak-to-peak value)

V

OFD(0)

V

OFD(255)

DC output voltage for code 0 − 2.0 − V
DC output voltage for

code 255

Z

OFD

additional 8-bit control DAC
(OFD) output impedance

I

OFD

OFD output

current drive
ADC CLAMP CONTROL DAC (see Fig.5)
V

DACOUT(p-p)

ADC clamp 10-bit control

DAC output voltage

(peak-to-peak value)
V

DACOUT

Z

DACOUT

DC output voltage code 0 − 1.4 − V

ADC clamp control DAC

output impedance
I

DACOUT

DAC output

current drive
OFE

LOOP

maximum offset error of code 0 −± 5 − LSB

DAC + ADC clamp loop code 1023 −± 5 − LSB

static −− 50 µA

code 1023 − 2.3 − V

static −− 50 µA

− 1.4 − V

− 3.4 − V

− 2000 −Ω

− 0.9 − V

−− 250 Ω

Digital outputs (f

V

V
I

OH

OL

OZ

HIGH level output voltage IOH= −1mA V

LOW level output voltage IOL= 1 mA 0 − 0.5 V

output current in 3-state

mode
t

h

t

d(OUT)

output hold time 5 −−ns

output delay

Ci=20pF

Serial interface

f

SCLK

maximum frequency of serial

interface

= 18 MHz; CL=20pF)

CLK

−

CCO

− V

0.5

0.5 V < Vo< V

V

= 4.75 V − 12 15 ns

CCO

= 3.15 V − 17 20 ns

V

CCO

V

= 2.7 V − 21 24 ns

CCO

CCO

−20 +20 µA

5 −−MHz

CCO

V

1997 May 20 10

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

handbook, halfpage

33.5

G

AGC

(dB)

3.5
0 319

AGC control DAC input code

TDA8786; TDA8786A

MGE365

511

handbook, full pagewidth

V

o

(1)

(2)

1=

-----­V

i

V

o

0.66=

-----­V

i

Fig.3 AGC gain as a function of DAC input code.

AGCOUT

100%

40%

0

0

40%

control DAC

input code = 15

(1)

(2)

100% 130%

MGE364

control DAC

input code = 00

soft clipper input

Fig.4 Soft clipper output voltage as a function of soft clipper input voltage.

1997 May 20 11

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

handbook, halfpage

ADC CLAMP DAC

voltage

output

(V)

2.3

1.4
0

ADC CLAMP control DAC input code

MGE366

1023

handbook, halfpage

OFD DAC

voltage

output

(V)

3.4

2.0

TDA8786; TDA8786A

MGD599

0

OFD control DAC input code

255

handbook, full pagewidth

8 × f

SC

= 2f

CLK

CDSP1

CDSP2

Fig.5 DAC voltage output as a function of DAC input code.

>12 ns

>12 ns

MGE370

Fig.6 CCD high-band control signal timing (TDA8786).

1997 May 20 12

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

handbook, full pagewidth

8 × f

SC

= 3f

CLK

CDSP1

CDSP2

TDA8786; TDA8786A

>12 ns

>12 ns

MGE369

handbook, full pagewidth

8 × f

SC

= 2f

CLK

CDSP1

CDSP2

Fig.7 CCD normal-band control signal timing (TDA8786).

>12 ns

MGE371

>12 ns

Fig.8 CCD high-band control signal timing (TDA8786A).

1997 May 20 13

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

handbook, full pagewidth

8 × f

SC

= 3f

CLK

CDSP1

CDSP2

Fig.9 CCD normal-band control signal timing (TDA8786A).

TDA8786; TDA8786A

>12 ns

MGE372

>12 ns

I

handbook, halfpage

PBIN
(µA)

450

0

−450

I

handbook, halfpage

ADCIN

(µA)

450

0

−450

1.4

30 mV

Fig.10 Typical PBK clamp current.

V

ref

30 mV

500 mV

V

(V)

PBIN

MBK058

slope = 1 kΩ

V

(V)

ADCIN

MBK059

I

handbook, halfpage

(µA)

350

0

−350

2.85

200 mV

V (V)

MBK057

Fig.11 Typical clamp currents for pins IN1, IN2 and

STGE.

ADC clamping

When CLPADC is HIGH (TDA8786) (LOW for
TDA8786A), the ADC input is clamped to voltage level V
V

should normally be connected to VRB (ADC output

ref

ref

code 0 pin) or to DACOUT (10-bit DAC output). The DAC
is controlled via the serial interface, its output covers the
lower half of the ADC input range.

.

Fig.12 Typical ADC clamp current.

1997 May 20 14

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

handbook, full pagewidth

SDATA

D0

SCLK

SEN

8
(D7 to D0)

OFD

LATCHES

8-bit DAC 10-bit DAC

D1 D2 D3 D4 D510D6

LSB MSB

9
(D8 to D0)

AGC GAIN

LATCHES

AGC control soft clip

SHIFT REGISTER

4
(D3 to D0)

SOFT CLIP

LATCHES

control

TDA8786; TDA8786A

D7 D8 D9 A0 A1 A2

LATCH

SELECTION

4
(D3 to D0)

PARTIAL

STANDBY

standby

control

10
(D9 to D0)

CLAMP

REFERENCE

LATCHES

MGD526

handbook, full pagewidth

SCLK

SEN

Fig.13 Serial interface block diagram.

t

su

t

MSB LSB

A1 A0 D9 D7 D6 D5 D4 D3

A2SDATA

t

su

hd3

D8

D2 D1 D0

MGE373

t

hd4

t

su

tsu= 4 ns (min.); t

hd3=thd4

4 ns (min.).

Fig.14 Loading sequence of control DACs input data via the serial interface.

1997 May 20 15

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

Table 1 Serial interface programming (see note 1)

ADDRESS BITS

A2 A1 A0

0 0 0 OFD output control (D7 to D0).
0 0 1 Soft clipper control. Only the 4 LSBs (D3 to D0) are used. Bits D9 to D4 should be set to

logic 0.
0 1 0 AGC gain control (D8 to D0).
0 1 1 Partial stand-by controls for power consumption optimization. Only the 4 LSBs

(D3 to D0) are used. Bits D9 to D4 should be set to logic 0:

D0 = 1: CDS + AGC + soft clipper block in stand-by; I
D1 = 1: optical black clamp + blanking block in stand-by; I
D2 = 1: OFD DAC in stand-by; I
D3 = 1: 6 dB amplifier (output on AMPOUT pin) in stand-by; I

1 0 0 Clamp reference DAC (D9 to D0).

Note

1. At the end of each programming sequence (usually during the video vertical blanking), the soft clipper register must
be reloaded (for example if the soft clipper is not used, code 15 must be entered in the soft clipper register at the end
of each TDA8786(A) programming sequence)

DATA BITS D9 to D0

CCA+ICCD

=92mA

CCA+ICCD

CCA+ICCD

CCA+ICCD

=44mA

=87mA

=92mA.

Table 2 Stand-by selection.

STDBY D9 to D0 I

1 LOW 3 mA
0 active 94 mA

CCA+ICCD

(typ.)

1997 May 20 16

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

t

handbook, full pagewidth

IN1 and IN2

CDSP1
(active HIGH)

sample N

CDSP2
(active HIGH)

CLK

DATA
OUTPUT
D0 to D7

The hatched areas represent active video.

PIXEL N-4 PIXEL N-3 PIXEL N-2 PIXEL N-1 PIXEL N

hd1

t

hd2

TDA8786; TDA8786A

t

d

t

h

t

d (OUT)

MGE367

handbook, full pagewidth

Fig.15 Pixel frequency timing diagram.

AGCOUT VIDEO OPTICAL BLACK HORIZONTAL FLYBACK DUMMY VIDEO

CLPCDS
(active HIGH)

CLPOPB
(active HIGH)

PBK
(active HIGH)

PRE­BLANKING
OUTPUT

CLPADC
(active HIGH)

VIDEO BLACK LEVEL VIDEO

MGE368

Fig.16 Line frequency timing diagram.

1997 May 20 17

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

APPLICATION INFORMATION

TDA8786 and SAA8110 can be used with Sharp CCDs. TDA8786A and SAA8110 can be used with Sony CCDs. Table
gives as an example some references of ICs which may be used with Philips TDA8786(A)/SAA8110. This overview is
not restrictive, both devices are compatible with other CCD/V-driver/PPG combinations including the more recent ones.

Table 3 Possible components for the application of Figs 17 and 18.

NTSC PAL

CCD TYPE COMPONENT TYPE

SONY CCDs CCD LZ2313H5 LZ2353A LZ2323H5 LZ2363

V-driver LR36683N
timing generator LZ95G55 LZ95G71 LZ95G55 LZ95G71

SHARP CCDs CCD ICX056AK ICX068AK ICX057AK ICX069AK

V-driver CXD1250MN, CXD1267N
timing generator CXD1257AR CXD1265R CXD1257AR CXD1265R

Notes to the application diagram

MEDIUM

RESOLUTION

HIGH

RESOLUTION

MEDIUM

RESOLUTION

HIGH

RESOLUTION

• In the configuration of Figs 17 and 18, the microcontroller reads and writes data from/to the DSP using the SNERT-bus

(UART-mode 0). Optional external control is available through the I2C-bus.

• Free I/O pins of the microcontroller can be used to control PGG, or for other purposes.

• 83Cxxx processing is synchronized by VD interruption. Depending on VD polarity, it can be necessary to invert VD.

• A customized 83Cxx is available for this application. Please contact your nearest Philips sales office.

1997 May 20 18

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

handbook, full pagewidth

VERTICAL DRIVER

(PPG)

V4 V3 V2 V1 H1 H2

CCD

(optional)

V

DD

44

P0.0/AD0

43

P0.1/AD1

42

P0.2/AD2

41

P0.3/AD3

40

P0.4/AD4

39

P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8

V

V

DDD

38
37
36
35
33
32
31
30
29
28
27
26
25
24

H2

SMP_CLK
(from DSP)

10 µF

DDD

RESET_DSP
(to DSP)

V

DDD

4JB

+5 V

V

DDD

10 kΩ

OEN (optional)

(to ADC)

3JB

2JB

SCL

GND

5 V V
5 V V
5 V V

BC848C

V

1

SDA JB

A0/SN

SCL/SN

HD (opt.)

A1/SN

RES

digital ground

analog ground

DDD

DA

CL

FI

IN

18 pF

12 MHz

18 pF

DDA1
DDA2
DDA3

10 kΩ

4.7 µF

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5

P1.6/SCL

P1.7/SDA

RST
P3.0/RxD
P3.1/TxD

P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

P3.6/WR

P3.7/RD

XTAL2
XTAL1

V

V4 V3 V2 V1 H1

VERTICAL

DRIVER BUFFER

−xxV +xxV
SWITCH MODE

POWER SUPPLIES

V

DDD

VD (from PPG)

2
3

MICRO-

4

CONTROLLER

5
6
7
8
9
10

83C54/

11

83C654

13

(OM-XXX)

14
15
16
17
18
19
20
21

SS

22

Horizontal Drive

Electrical

Shutter

Shutter

4.7kΩ4.7

V

DDD

CDAC

CDSPULSE1
CDSPULSE2

CLAMPCDS
CLAMPOPB
CLAMPADC

PreBlank

Vertical Drive

Reset
Pulse

Reset

CCDout

OFD level

(optional)

100 nF

V

DDA1

V

DDD

V

DDD

kΩ

P0
P1

OUT

CLK1
CLK2

Field Id

CLAMPADC

(from PPG)

SDA

SCL
PTC

V

DD

100 nF

P0 (optional, PPG setting)
P1 (optional, PPG settings)
CDAC

(optional, can be used for frequency tuning)

OUT

CLK1 (to ADC and DSP)
CLK2 (to DSP, CLK2 = 2 × CLK1)
CDSPULSE1
CDSPULSE2
CLAMPCDS (CLAMP CDS, OPB, ADC can be the same)
CLAMPOPB
CLAMPADC
PreBlank (optional)
HD (to DSP and µC)

AMPOUT

100 nF

220 nF

220 nF

CLAMPOPB
PreBlank

5
6

PCF8598
PCF8594

7

PCF8582

8

VD (to DSP and µC)
FI (to DSP and µC)

1 µF

CLPOPB

OFDOUT
AMPOUT

AGND1
V

CCA1

AGCOUT

PBOUT

ADCIN

CLPADC

1 nF

4

EPROM

3
2
1

MGK393

PBK

PBIN

V

V

SS
A2
NC
WP

CLK1

CLAMPCDS
CDSPULSE1
CDSPULSE2

V

DDA1

100 nF

AGND3

IN2

IN1

48 47

46 45 3944 43 42 40 373841

1
2
3

ANALOG TO DIGITAL INTERFACE

4
5
6
7
8
9
10
11

ref

12

13 14 15 16 2217 18 19 21 242320

CCA2

V

AGND2

DACOUT

V

DDA1

100

nF

1nF1nF2.2

TDA8786; TDA8786A

100 nF

V

DDA1

OEN (optional)
(from microcontroller)

V

DDD

100 nF

CCA3

V

CDSP2

TDA8786G

TDA8786AG

RT

RB

V

V

CDSP1

or

DEC1

CLPCDS

STGE

nF

CLK

SDATA

DGND2

SCLK

200

nF

CCD2

V

SEN

OE

STBY

CCO

V

CCD1

V

OGND1

36

D9

35

D8

34

D7

33

D6

32

D5

31

D4

30

D3

29

D2

28

D1

27

D0

26

DGND1

25

100 nF

V

DDD

A
B
C
D
E
F
G
H

I

J

K

L
M

Fig.17 SAA8110G system configuration for camera application (continued in Fig.18).

1997 May 20 19

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

handbook, full pagewidth

A1/SN

RES

A0/SN

DA

SDA

SCL/SN

G

A
B
C
D
E
F

H
I
J

K

L
M

CLK1

CDAC

V

100 nF

VD

HD

FI

OUT

digital ground

analog ground

CL

optional

DDD

V

DDD(C1)

VSYNC
HSYNC

V

SSD(C1)

V

SSD(C2)

V

SSA(CD)

CDAC

SMP_CLK (to power supply)

CLK1

CCD9
CCD8
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0

SCLK

10 nF

OUT

IN

X

X

80 79

1
2

IN

3

IN

4

FI

IN

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

OUT

20

21

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

RBIAS

DDA(CD)

V

CDAC

150 kΩ
100 nF

V

DDA2

CL

SSD(C3)

SSD(C4)

V

SCL/SN

V

78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

SMP

SDATA

STROBE

P0
P1

V

DDD

V

DDD

100

nF

RES

DA

DDD(C3)

SSD(P2)

A1/SN

A0/SN

SDA

V

Y0

V

Y2

Y1

DIGITAL SIGNAL PROCESSOR

SAA8110G

SIS

V

RESET

DDD(C2)

V

DDD

RESET_DSP

(from µC)

T2T1T0

100
nF

V

V

P0

P1

Y4

Y3

OUT3

SSA(OB)

DDA3

100 nF

Y5

Y6

DDA(O3)

V

Y7

38 39 40

OUT2

DDA(O2)

V

V

DDD

100 nF

DDD(P2)

V

OUT1

V

V

DDA3

100 nF

UV0

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

DDA(O1)

UV1
UV2

UV3
UV4
UV5
UV6
UV7

V

SSD(P1)
LLC
CREF/PXQ
HREF

VSYNC

OUT

FI

OUT
CLK2
V

DDD(P1)

V

DDA(BG)
RBIAS
DECOUPL

V

SSA(BG)
V

DDA(DC)

(1)

L

(1)

L

(1)

L

(1)

L

(1)

L

(1)

L

CLK2 (from PPG)

47 kΩ

100 nF

V

100 nF

68 Ω

(1)

L

68 Ω

(1)

L

68 Ω

(1)

L

TDA8786; TDA8786A

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

DIGITAL OUTPUT CONNECTOR

4

3

2

V

100 nF

126

3

5

7

4

6

1

11

7

2

12

8

3

13

9

14

4

10

5

15

CVBS-RCA

DDD

1

V

DDD

MGK394

DDA3

Green

U, Blue

CVBS

Y

C

V, Red

V

DDD

V

DDA3

100 nF

SVHS

(1) Values depend on DSP output configuration.

Fig.18 SAA8110G system configuration for camera application (continued from Fig.17).

1997 May 20 20

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

PACKAGE OUTLINE

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

c

y

X

36

37

25

Z

24

E

A

TDA8786; TDA8786A

SOT313-2

e

w M

pin 1 index

48

1

e

DIMENSIONS (mm are the original dimensions)

mm

A

A1A2A3b

max.

0.20

1.60

0.05

1.45

1.35

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

b

p

0.25

w M

D

H

D

p

0.27

0.17

12

Z

D

(1) (1)(1)

cE

D

0.18

7.1

0.12

6.9

b

p

13

v M

B

v M

0 2.5 5 mm

scale

(1)

eH

H

D

7.1

6.9

0.5

9.15

8.85

E

A

B

9.15

8.85

H

E

LLpQZywv θ

E

A

0.75

0.45

A

2

0.69

0.59

A

1

detail X

0.12 0.10.21.0

Q

(A )

3

θ

L

p

L

Z

E

D

0.95

0.55

0.95

0.55

o

7

o

0

OUTLINE

VERSION

SOT313-2

IEC JEDEC EIAJ

REFERENCES

1997 May 20 21

EUROPEAN

PROJECTION

ISSUE DATE

93-06-15
94-12-19

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for
CCD cameras

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

(order code 9398 652 90011).

TDA8786; TDA8786A

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 May 20 22

Philips Semiconductors Preliminary specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1997 May 20 23

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: seeAustria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 547047/1200/02/pp24 Date of release: 1997 May 20 Document order number: 9397 750 01597