Datasheet TDA8785H-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1996 Jan 17
File under Integrated Circuits, IC02

1997 Dec 18

INTEGRATED CIRCUITS

TDA8785

8-bit high-speed analog-to-digital
converter with gain and offset
controls

1997 Dec 18 2

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

FEATURES

• 8-bit analog-to-digital converter (ADC)

• 8-bit digital-to-analog converter (DAC)

• Sampling rate up to 30 Msps for both ADC and DAC

• Binary or two’s complement 3-state TTL outputs

• TTL compatible inputs and outputs

• 100 MHz variable gain amplifier (0 to 20 dB) externally

controlled

• All analog inputs and outputs are differential (can also
be used in single-ended format)

• Analog input signal from 0.1 to 1.0 V (p-p) differential

• Offset amplifier with:

– Slow offset control (±250 mV)
– Fast offset control (±500 mV) eventually driven by

internal DAC.

• ADC output code of 8 (typ.) when analog input signal
and offset correction inputs are 0 V

• Gain, slow offset control inputs and DAC output swing
of 1.5 V (p-p) range (2.75 ±0.75 V)

• 2.75 V reference voltage

• Internal references for ADC and DAC.

APPLICATIONS

• CCD type of systems

• Scanner

• Copier

• Video acquisition.

GENERAL DESCRIPTION

The TDA8785 is an 8-bit analog-to-digital converter with
gain and offset controls for the input signal. An internal
8-bit DAC provides fast offsets control.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA1

analog supply voltage 1 4.75 5.0 5.25 V

V

CCA2

analog supply voltage 2 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

TTL output supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 80 − mA

I

CCD

digital supply current − 30 − mA

I

CCO

TTL output supply current − 9 − mA
INL integral non-linearity 0 to 20 dB gain; ramp input −±0.7 ±1.8 LSB
DNL differential non-linearity 0 to 20 dB gain; ramp input −±0.2 ±0.7 LSB
f

clk(max)

maximum clock frequency ADC and DAC 30 −−MHz
B controlled gain amplifier

bandwidth

− 100 − MHz

P

tot

total power dissipation − 600 − mW

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8785H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2

1997 Dec 18 3

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MBG681

21

43
44
37
38
42
41

OFFSET

AMPLIFIER

GAIN

39
40

ADC

TTL

OUTPUTS

8

8

26 to 33

REGULATORS

6 7 36 5 35 34

9
8

V

CCA

10
11

8

12 to 19

DAC

20 22

CLOCK

DRIVER

CLOCK

DRIVER

23

25
24

1 2 3 4

TDA8785

V

CCA1VCCA2

AGND1

AGND2

DEC2

V

RB

V

DACO(n)

V

DACO(p)

V

FSDAC(p)

V

FSDAC(n)

V

CCD

V

CCO

OGND

OF

B

DEC1

V

ref

V

SOFF(p)

V

SOFF(n)

V

FSAD(p)

V

FSAD(n)

V

FOFF(n)

V

FOFF(p)

V

i(p)

V

i(n)

CLKDACDA7 to DA0

AD0 to AD7

DGNDCLKADC

150 Ω 150 Ω

1997 Dec 18 4

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

PINNING

SYMBOL PIN DESCRIPTION

V

CCA1

1 analog supply voltage 1 (+5 V)

V

CCA2

2 analog supply voltage 2 (+5 V)
AGND1 3 analog ground 1
AGND2 4 analog ground 2
DEC2 5 decoupling input 2
B 6 bandwidth adjustment node input
V

RB

7 ADC reference voltage output

bottom (decoupling)

V

DACO(n)

8 DAC negative voltage output
V

DACO(p)

9 DAC positive voltage output
V

FSDAC(p)

10 DAC full-scale positive control

voltage input

V

FSDAC(n)

11 DAC full-scale negative control

voltage input
DA7 12 DAC TTL input; bit 7 (MSB)
DA6 13 DAC TTL input; bit 6
DA5 14 DAC TTL input; bit 5
DA4 15 DAC TTL input; bit 4
DA3 16 DAC TTL input; bit 3
DA2 17 DAC TTL input; bit 2
DA1 18 DAC TTL input; bit 1
DA0 19 DAC TTL input; bit 0 (LSB)
CLKDAC 20 DAC clock input
DGND 21 digital ground
CLKADC 22 ADC clock input
V

CCD

23 digital supply voltage (+5 V)

OGND 24 output ground
V

CCO

25 output supply voltage (+5 V)
AD0 26 output data; bit 0 (LSB)
AD1 27 output data; bit 1
AD2 28 output data; bit 2
AD3 29 output data; bit 3
AD4 30 output data; bit 4
AD5 31 output data; bit 5
AD6 32 output data; bit 6
AD7 33 output data; bit 7 (MSB)
OF 34 output format input
DEC1 35 decoupling input 1
V

ref

36 reference voltage output (2.75 V)
V

SOFF(p)

37 slow offset amplifier positive

voltage input

V

SOFF(n)

38 slow offset amplifier negative

voltage input

V

FSAD(p)

39 gain control positive voltage input
V

FSAD(n)

40 gain control negative voltage input
V

FOFF(n)

41 fast offset amplifier negative

voltage input

V

FOFF(p)

42 fast offset amplifier positive voltage

input

V

i(p)

43 analog positive voltage input
V

i(n)

44 analog negative voltage input

SYMBOL PIN DESCRIPTION

1997 Dec 18 5

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Fig.2 Pin configuration.

handbook, full pagewidth

TDA8785

MBG680

1
2
3
4
5
6
7
8

9
10
11

33
32
31
30
29
28
27
26
25
24
23

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

V

CCA1

V

CCA2
AGND1
AGND2

DEC2

B

V

RB

V

DACO(n)

V

DACO(p)

V

FSDAC(p)

V

FSDAC(n)

V

CCD

V

CCO

OGND

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

OF

DEC1

V

ref

V

SOFF(p)

V

SOFF(n)

V

FSAD(p)

V

FSAD(n)

V

FOFF(n)

V

FOFF(p)

V

i(p)

V

i(n)

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

CLKDAC

DGND

CLKADC

1997 Dec 18 6

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

FUNCTIONAL DESCRIPTION

The TDA8785 is composed of an 8-bit ADC (30 Msps),
a wide-band gain amplifier, an input offset amplifier and an
8-bit dynamic adjustment DAC.

Input signal

Two input pins are provided to apply a differential input
signal with a wide range (100 to 1000 mV differential).
It is also possible to apply a single signal by setting a DC
voltage on one of the differential pins and supplying the
signal to the other.

Controlled gain amplifier

The gain amplifier is used to adjust the wide input signal
range to the fixed ADC input range of 1 V (p-p).

A large gain of 20 dB can be achieved with low-noise
behaviour and a large bandwidth of 100 MHz to correctly
amplify square type signals with step edges. Using pin 6,
it is possible to reduce the internal bandwidth of the gain
amplifier via an external capacitor and thus improve its
noise behaviour. The gain amplifier is controlled via an
external differential voltage (single input can also be
applied).

Input offset amplifier and adjustment DAC

The Input offset amplifier contains two different control
inputs (which can also be single):

• Slow offset control, for slow variation characteristics
(e.g. temperature, supply voltage, etc.)

• Fast offset control, for correction related to the clock
rate.

Slow offset control is carried out by an external voltage
while fast offset control is digitally carried out via the
internal 8-bit DAC with external connections of the
respective pins V

DACO(n)

, V

DACO(p)

, V

FOFF(n)

and V

FOFF(p)

.

The internal 8-bit DAC operates at the ADC clock rate to
allow dynamic corrections on the input signal chain based
on the signal processing information carried out after the
digital conversion. The output voltage amplitude of the
DAC can be controlled via a different input voltage (which
can also be single) in a range of ±25% with a 150 Ω DAC
output load.

The DAC can also be used for the gain or the slow offset
control with some external DC voltage adaptations and
can be considered as a separate function of the ADC
chain. The DAC can be used independently, for example
as a video DAC.

8-bit ADC

The 8-bit ADC converts a signal of 1 V (p-p) from the
controlled gain amplifier into an 8-bit coded digital word at
a maximum rate of 30 Msps. Its reference voltage is
supplied by the general voltage regulator. The output data
format can either be binary, two’s complement or 3-state
by selecting pin OF.

When all the differential inputs on the offset amplifier
(V

SOFF(p)

, V

SOFF(n)

, V

FOFF(n)

, V

FOFF(p)

, V

i(p)

and V

i(n)

) are at
0 V (equivalent to both inputs short-circuited), the output
code of the ADC is code 8.

Internal voltage regulator

An internal voltage regulator provides all the references for
the different blocks. A stable 2.75 V voltage reference
output is provided for use in the application environment.
One application is to connect all the slow control inputs
(V

FSDAC(p)

, V

FSDAC(n)

, V

SOFF(p)

, V

SOFF(n)

, V

FSAD(p)

and

V

FSAD(n)

) to this reference, either to their two differential
inputs to get the nominal settings or to one of the
differential inputs to have easy single-input control.

All these control inputs have the same control range.

1997 Dec 18 7

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage −0.3 +7.0 V

V

CCD

digital supply voltage −0.3 +7.0 V

V

CCO

output supply voltage −0.3 +7.0 V

∆V

CC

supply voltage difference between

V

CCA

and V

CCD

−1.0 +1.0 V

V

CCD

and V

CCO

−1.0 +1.0 V

V

CCA

and V

CCO

−1.0 +1.0 V

V

i

input voltage referenced to AGND −0.3 +7.0 V

V

clk(p-p)

clock input voltage for switching (peak-to-peak value) referenced to DGND − V

CCD

V

I

o

output current − 6mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature 0 70 °C

T

j

junction temperature − 150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 75 K/W

1997 Dec 18 8

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

CHARACTERISTICS

V

CCA1=VCCA2=VCCD=VCCO

= 4.75 to 5.25 V; AGND, DGND and OGND short-circuited together;

V

CCA

to V

CCD=VCCD

to V

CCO=VCCA

to V

CCO

= −0.25 to +0.25 V; T

amb

=0to70°C;

typical values measured at V

CCA=VCCD=VCCO

= 5 V and T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA1

analog supply voltage 1 4.75 5.0 5.25 V

V

CCA2

analog supply voltage 2 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

TTL output supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 80 − mA

I

CCD

digital supply current − 37 − mA

I

CCO

TTL output supply current − 9 − mA

Reference voltages (pins V

ref

and VRB)

V

o(ref)

output reference voltage 2.60 2.75 2.90 V

V

line

line regulation voltage V

CCA

= 4.75 to 5.25 V − 4 − mV

I

o(L)

output load current −0.5 − +0.5 mA

V

RB

reference voltage output bottom
(decoupling)

− V

CCA

− 2.5 − V

V

offset(B)

offset voltage bottom code 0 − V

RB

− 250 − mV

∆V

ADC

ADC reference voltage difference between

code 0 and 255

− 1 − V

Analog inputs (pins V

i(p)

and V

i(n)

); see Table 1

V

i(diff)(p-p)

differential input voltage V

i(p)

− V

i(n)

(peak-to-peak value)

0 dB gain − 1000 − mV
20 dB gain − 100 − mV

V

I

DC input voltage 2.5 3.0 3.5 V

I

i

input current − 7 −µA

Z

i

input impedance − 20 − kΩ

C

i

input capacitance − 1 − pF

Fast offset amplifier inputs (pins V

FOFF(p)

and V

FOFF(n)

); DC parameters

V

FOFF(p)

positive input voltage 0 dB gain − 500 − mV

20 dB gain − 50 − mV

V

FOFF(n)

negative input voltage 0dB gain − 500 − mV

20 dB gain − 50 − mV

V

I

DC input voltage V

CCA

− 0.75 V

CCA

− 0.25 V

CCA

V

I

i

input current − 4 −µA

Z

i

input impedance − 20 − kΩ

C

i

input capacitance − 1 − pF

1997 Dec 18 9

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Slow offset amplifier inputs (pins V

SOFF(p)

and V

SOFF(n)

) gain amplifier at 0 dB; note 1

V

offset(ADC)

offset voltage at ADC input V

SOFF(p)

=2V;

V

SOFF(n)

= 2.75 V

−−0.25 − V

V

SOFF(p)

= 2.75 V;

V

SOFF(n)

= 2.75 V

− 0 − V

V

SOFF(p)

= 3.5 V;

V

SOFF(n)

= 2.75 V

− 0.25 − V

I

i

input current − 10 −µA

Offset reference code; T

amb

=25°C

OFSRE offset reference (ADC output code) V

i(p)=Vi(n)

;

V

FOFF(p)=VFOFF(n)

;

V

SOFF(p)=VSOFF(n)

;
amplifier gain set at
0dB

− 8 − code

OFSER offset reference error on code 8 −15 0 +15 code

Gain control inputs (pins V

FSAD(p)

and V

FSAD(n)

); see Fig.7

G

v(min)

minimum voltage gain V

FSAD(p)

=2V;

V

FSAD(n)

= 2.75 V

−−0dB

G

v(max)

maximum voltage gain V

FSAD(p)

= 3.5 V;

V

FSAD(n)

= 2.75 V

20 −−dB

I

i

input current − 10 −µA

DAC full-scale control inputs (pins V

FSDAC(p)

and V

FSDAC(n)

) 150 Ω output load on pins V

DACO(p)

and V

DACO(n)

;

see Table 3
V

DACO(n)

DAC negative output voltage (pin 8) code 0 at DAC inputs − V

CCA

− V

code 255 at DAC inputs;
V

FSDAC(p)

=2V;

V

FSDAC(n)

= 2.75 V

− V

CCA

− 0.4 − V

code 255 at DAC inputs;
V

FSDAC(p)

= 2.75 V;

V

FSDAC(n)

= 2.75 V

− V

CCA

− 0.5 − V

code 255 at DAC inputs;
V

FSDAC(p)

= 3.5 V;

V

FSDAC(n)

= 2.75 V

− V

CCA

− 0.6 − V

I

i

input current − 1 −µA
Bandwidth adjustment node input (pin B); see Fig.6
Z

i

input impedance − 500 −Ω

8-bit DAC; f

clk

= 30 MHz, ramp input; T

amb

=25°C

Z

o

output impedance − 150 −Ω
INL integral non-linearity −±0.4 ±0.8 LSB
DNL differential non-linearity −±0.4 ±1.0 LSB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Dec 18 10

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Digital inputs (pins CLKDAC, CLKADC and DA7 to DA0)

V

IL

LOW-level input voltage 0 − 0.8 V
V

IH

HIGH-level input voltage 2.0 − V

CCD

V

I

IL

LOW-level input current VIL= 0.4 V −400 −−µA
I

IH

HIGH-level input current VIH= 2.7 V −−100 µA
Z

i

input impedance f

clk

= 10 MHz − 4 − kΩ

C

i

input capacitance f

clk

= 10 MHz − 4.5 − pF
ADC output format (pin OF); see Table 2
V

IL

LOW-level input voltage 0 − 0.2 V

V

IH

HIGH-level input voltage 2.6 − V

CCD

V

V

i(Z)

input voltage in high impedance
state

− 1.20 − V

I

IL

LOW-level input current VIL= 0.4 V −370 −130 −µA

I

IH

HIGH-level input current V

clk

= 2.7 V − 300 450 µA

ADC digital outputs

V

OL

LOW-level output voltage IOL= 2 mA 0 − 0.6 V

V

OH

HIGH-level output voltage IOH= −0.4 mA 2.4 − V

CCO

V
ADC and DAC switching; see Fig.4
f

clk(max)

maximum clock frequency note 2 30 −−MHz

t

CPH

clock pulse width HIGH 12 −−ns

t

CPL

clock pulse width LOW 12 −−ns
Analog processing; note 3
INL integral non-linearity ramp input (full-scale);

0 to 20 dB gain

−±0.7 ±1.8 LSB

DNL differential non-linearity ramp input (full-scale);

0 to 20 dB gain

±0.2 ±0.7 LSB

S/N signal-to-noise ratio

(without harmonics)

fi= 2 MHz

0 dB gain − 47 − dB
10 dB gain − 45 − dB
20 dB gain − 43 − dB

B bandwidth −3dB − 100 − MHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Dec 18 11

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Notes

1. Vos is proportional to the amplifier gain. For instance, Vos at 20 dB is the one indicated at 0 dB multiplied by 10.

2. It is recommended that the rise and fall times of the clock are >1 ns. In addition a good layout for the digital and
analog grounds is recommended.

3. Analog processing from signal inputs or fast offset amplifier inputs to ADC digital output; f

clk

= 30 MHz; no external

filtering on pin 6 (B).

4. The data set-up time (t

SU; DAT

) is the minimum period preceding the rising edge of the clock, that the input data must
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge and still be recognized. The data set hold time (t

HD; DAT

) is the minimum period following the rising edge
of the clock, that the input data must be stable in order to be correctly registered. A negative hold time indicates that
the data may be released prior to the rising edge and still be recognized.

5. The residual settling accuracy is defined as follows. When a full-scale step is applied to the DAC, the initial settling
shows a fast settling behaviour. For the final part, the DAC analog output shows a slow settling behaviour.
The Residual Settling Accuracy (RSA) is defined as the full-scale error at the cross-over point at time tX.

Timing

ADC

DIGITAL OUTPUTS (C

L

= 15 pF)

t

ds

sampling delay time − 1.5 − ns

t

h

output hold time 7 −−ns

t

d

output delay time −−16 ns

DAC OUTPUTS (PINS V

DACO(p)

AND V

DACO(n)

)

t

SU; DAT

data set-up time note 4 −0.3 −−ns

t

HD; DAT

data hold time note 4 −−2ns

t

S

DAC setting time (10 to 90%) RL= 150 Ω; CL=15pF − 8 − ns

RSA residual setting accuracy note 5; see Fig.8 0.1 2.5 %
3-

STATE OUTPUT DELAY TIMES (see Fig.5)

t

dZH

enable HIGH − 15 20 ns

t

dZL

enable LOW − 15 20 ns

t

dHZ

disable HIGH − 13 20 ns

t

dLZ

disable LOW − 10 20 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Dec 18 12

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Table 1 Output coding and input voltage (typical values; referenced to AGND, V

i(p)

− V

i(n)

= 1 V (p-p), 0 dB gain, no

offset correction

Table 2 OF input coding

Note

1. Use C ≥ 10 pF to DGND.

Table 3 Input coding and DAC output voltages (typical values; referenced to V

CCA

regardless of the offset voltage);

V

FSDAC(p)=VFSDAC(n)

STEP V

i(p)

− V

i(n)

BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Underflow→0.032 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

0 −0.032 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 − 0000000110000001

. − ................

8 0 0000100010001000

. − ................

254 − 1111111001111110
255 0.968 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

Overflow >0.968 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

OF AD0 to AD7

0 active, two’s complement
1 high impedance

open circuit; note 1 active, binary

CODE

BINARY INPUT DATA DAC OUTPUT VOLTAGES (V)

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

Z

L

=10kΩ ZL= 150 Ω

V

DACO(p)VDACO(n)VDACO(p)VDACO(n)

0 00000000−1.0 0 −0.5 0
1 00000001 −−−−

.............

128 10000000−0.5 −0.5 −0.25 −0.25

.............

254 11111110 −−−−
255 11111111 0 −1.0 0 −0.5

1997 Dec 18 13

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Fig.3 Data set-up and hold times (DAC).

The shaded areas indicate when the input data may change and be correctly registered. Data input update must be completed within 0.3 ns, after the
first rising edge of the clock (t

SU; DAT

is negative; −0.3ns). Data must be held at least 2 ns after the rising edge (t

HD; DAT

= +2ns).

handbook, full pagewidth

HD; DAT

t

input data

CLKDAC

MBG682

SU; DAT

t

3.0 V

1.4 V
0 V

3.0 V

1.4 V
0 V

stable

Fig.4 Timing diagram.

handbook, full pagewidth

ds

t

sample N + 1

sample N

CLKADC

MBG683

sample N + 2

1.4 V

V

i(p)

− V

i(n)

DATA

AD0 to AD7

t

d

t

h

CPH

t

CPL

t

2.4 V

0.4 V

1.4 V

DATA

N + 1

DATA

N

DATA

N - 1

DATA

N - 2

1997 Dec 18 14

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Fig.5 Timing diagram and test conditions of 3-state output delay time.

fOF= 100kHz.

handbook, full pagewidth

MBG684

50 %

1.15 V

50 %

HIGH

dZH

t

dHZ

t

50 %

HIGH Z

HIGH Z

LOW

dZL

t

dLZ

t

10 %

90 %

output
data

V

CCD

output
data

3.3 kΩ

15 pF

S1

V

CCD

TDA8785

OF

OF

TEST

dLZ

t

dZL

t

dHZ

t

dZH

S1

CCD

V

CCD

V

GND
GND

t

Fig.6 Gain amplifier bandwidth and acquisition

chain S/N ratio as a function of the external
capacitance on pin 6.

(1) f

−3dB

.
(2) Signal-to-noise ratio.
The controlled gain amplifier is set at 20 dB gain.

handbook, halfpage

MBG691

101

10

2

10

2

10

3

10

1

42

44

46

48

10

−1

10

−1

f

−3 dB

(MHz)

CB (pF)

S/N

(dB)

(1)

(2)

Fig.7 Typical amplifier gain (Gv) as a function of

the differential input voltage;
V

FSAD(p)

− V

FSAD(n)

.

handbook, halfpage

25

−0.75 −0.25 0 0.50−0.50 0.75

0

MBG692

0.25

5

10

15

20

G

v

(dB)

V

FSAD(p)

− V

FSAD(n)

(V)

1997 Dec 18 15

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Fig.8 DAC time response when a full-scale step is applied.

handbook, full pagewidth

100

RSA

V

DACO

(%)

90

0

t

s

t

x

t

10

MBK516

INTERNAL PIN CONFIGURATIONS

Fig.9 TTL data outputs.

handbook, halfpage

MBG685

V

CCO

AD0 to AD7

DGND

Fig.10 Analog inputs.

ok, halfpage

MBG686

V

CCA

AGND

V

FSDAC(p)

, V

SOFF(p)

,

V

FSAD(p)

, V

FOFF(p)

, V

i(p)

or

V

FSDAC(n)

, V

SOFF(n)

,

V

FSAD(n)

, V

FOFF(n)

, V

i(n)

1997 Dec 18 16

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Fig.11 Bandwidth input (B).

book, halfpage

MBG687

500 Ω

V

CCA

B

AGND

Fig.12 VRB.

ndbook, halfpage

MBG688

V

CCA

V

RB

R

LAD

AGND

Fig.13 DAC inputs.

dbook, halfpage

MBG689

200 Ω

DA7 to DA0

or

CLKDAC

or

CLKADC

40 kΩ

V

CCD

DGND

Fig.14 DAC outputs.

handbook, halfpage

MBG690

150 Ω150

Ω

V

DACO(p)

V

DACO(n)

1997 Dec 18 17

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

APPLICATION INFORMATION

Fig.15 Application diagram.

handbook, full pagewidth

MBG693

21

43
44
37
38

42
41

OFFSET

AMPLIFIER

GAIN

39
40

ADC

TTL

OUTPUTS

8

8

26 to 33

REGULATORS

6 7 36 5 35 34

9
8

V

CCA

V

CCA

10
11

8

12 to 19

DAC

20 22

CLOCK

DRIVER

CLOCK

DRIVER

23

25
24

1 2 3 4

TDA8785

V

CCA1VCCA2

AGND1

AGND2

DEC2

V

RB

V

DACO(n)

V

DACO(p)

V

FSDAC(p)

V

FSDAC(n)

V

CCD

V

CCO

OGND

OFB

DEC1

V

CCA1

V

ref

V

SOFF(p)

V

SOFF(n)

V

FSAD(p)

V

FSAD(n)

V

FOFF(n)

V

FOFF(p)

V

i(p)

V

i(n)

CLKDACDA7 to DA0

AD0

to

AD7

DGNDCLKADC

150 Ω 150 Ω

1
nF

10
pF

2 pF

100

nF

100

nF

3.3
nF

150

Ω

150

Ω

1997 Dec 18 18

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

PACKAGE OUTLINE

UNIT A1A2A3bpcE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.25

0.05

1.85

1.65

0.25

0.40

0.20

0.25

0.14

10.1

9.9

0.8 1.3

12.9

12.3

1.2

0.8

10

0

o

o

0.15 0.10.15

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.95

0.55

SOT307-2

95-02-04
97-08-01

D

(1) (1)(1)

10.1

9.9

H

D

12.9

12.3

E

Z

1.2

0.8

D

e

E

B

11

c

E

H

D

Z

D

A

Z

E

e

v M

A

X

1

44

34

33 23

22

12

y

θ

A

1

A

L

p

detail X

L

(A )

3

A

2

pin 1 index

D

H

v M

B

b

p

b

p

w M

w M

0 2.5 5 mm

scale

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

A

max.

2.10

1997 Dec 18 19

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

“Quality

Reference Handbook”

(order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

•A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

•The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Dec 18 20

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1997 Dec 18 21

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

NOTES

1997 Dec 18 22

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

NOTES

1997 Dec 18 23

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1997 SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands 547047/1200/02/pp24 Date of release: 1997 Dec 18 Document order number: 9397750 03005