Datasheet TDA8785H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8785

8-bit high-speed analog-to-digital
converter with gain and offset
controls

Preliminary specification
File under Integrated Circuits, IC02

1996 Jan 17

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital
converter with gain and offset controls

FEATURES

• 8-bit analog-to-digital converter (ADC)

• 8-bit digital-to-analog converter (DAC)

• Sampling rate up to 30 Msps for both ADC and DAC

• Binary or two’s complement 3-state TTL outputs

• TTL compatible inputs and outputs

• 100 MHz variable gain amplifier (0 to 20 dB) externally

controlled

• All analog inputs and outputs are differential (can also
be used in single-ended format)

• Analog input signal from 0.1 to 1.0 V (p-p) differential

• Offset amplifier with:

– slow offset control (±250 mV)
– fast offset control (±500 mV) eventually driven by

internal DAC

• ADC output code of 8 (typ.) when analog input signal
and offset correction inputs are 0 V

TDA8785

• Gain, slow offset control inputs and DAC output swing of

1.5 V (p-p) range (2.75 ±0.75 V)

• 2.75 V reference voltage

• Internal references for ADC and DAC.

GENERAL DESCRIPTION

The TDA8785 is an 8-bit analog-to-digital converter with
gain and offset controls for the input signal. An internal
8-bit DAC provides digital adjustment of the different input
offsets.

APPLICA TIONS

• CCD type of systems

• Scanner

• Copier

• Video acquisition.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
V
V
V
I

CCA

I

CCD

I

CCO

CCA1
CCA2
CCD
CCO

analog supply voltage 1 4.75 5.0 5.25 V
analog supply voltage 2 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
TTL output supply voltage 4.75 5.0 5.25 V
analog supply current − 80 − mA
digital supply current − 30 − mA

TTL output supply current − 9 − mA
INL integral non-linearity 0 to 20 dB gain; ramp input −±0.7 tbf LSB
DNL differential non-linearity 0 to 20 dB gain; ramp input −±0.4 tbf LSB
f

clk(max)

B controlled gain amplifier

maximum clock frequency ADC and DAC 30 −−MHz

− 100 − MHz

bandwidth
P

tot

total power dissipation − 600 − mW

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8785H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2

1996 Jan 17 2

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

BLOCK DIAGRAM

handbook, full pagewidth

V

SOFF(p)

V

SOFF(n)

V

FOFF(p)

V

FOFF(n)

V

FSAD(p)

V

FSAD(n)

V

DACO(p)

V

DACO(n)

V

FSDAC(p)

V

FSDAC(n)

V

i(p)

V

i(n)

43
44
37
38
42
41

39
40

9
8

10
11

V

AMPLIFIER

12 to 19

AGND1

V

CCA

CCA1VCCA2

1 2 3 4

OFFSET

150 Ω 150 Ω

DAC

8

AGND2

GAIN

TDA8785

CLOCK

DRIVER

20 22

CLKDACDA7 to DA0

DEC2

V

V

B

6 7 36 5 35 34

ref

RB

REGULATORS

ADC

DEC1

8

OUTPUTS

CLOCK

DRIVER

OF

TTL

V

CCD

8

23

26 to 33

25
24

21

DGNDCLKADC

TDA8785

AD0 to AD7

V

CCO


OGND

MBG681

Fig.1 Block diagram.

1996 Jan 17 3

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

PINNING

SYMBOL PIN DESCRIPTION

V

CCA1

V

CCA2

AGND1 3 analog ground 1
AGND2 4 analog ground 2
DEC2 5 decoupling input 2
B 6 bandwidth adjustment node input
V

RB

V

DACO(n)

V

DACO(p)

V

FSDAC(p)

V

FSDAC(n)

DA7 12 DAC TTL input; bit 7 (MSB)
DA6 13 DAC TTL input; bit 6
DA5 14 DAC TTL input; bit 5
DA4 15 DAC TTL input; bit 4
DA3 16 DAC TTL input; bit 3
DA2 17 DAC TTL input; bit 2
DA1 18 DAC TTL input; bit 1
DA0 19 DAC TTL input; bit 0 (LSB)
CLKDAC 20 DAC clock input
DGND 21 digital ground
CLKADC 22 ADC clock input
V

CCD

1 analog supply voltage 1 (+5 V)
2 analog supply voltage 2 (+5 V)

7 ADC reference voltage output bottom

(decoupling)
8 DAC negative voltage output
9 DAC positive voltage output

10 DAC full-scale positive control voltage

input

11 DAC full-scale negative control

voltage input

23 digital supply voltage (+5 V)

TDA8785

SYMBOL PIN DESCRIPTION

OGND 24 output ground
V

CCO

AD0 26 output data; bit 0 (LSB)
AD1 27 output data; bit 1
AD2 28 output data; bit 2
AD3 29 output data; bit 3
AD4 30 output data; bit 4
AD5 31 output data; bit 5
AD6 32 output data; bit 6
AD7 33 output data; bit 7 (MSB)
OF 34 output format input
DEC1 35 decoupling input 1
V

ref

V

SOFF(p)

V

SOFF(n)

V

FSAD(p)

V

FSAD(n)

V

FOFF(n)

V

FOFF(p)

V

i(p)

V

i(n)

25 output supply voltage (+5 V)

36 reference voltage output (2.75 V)
37 slow offset amplifier positive voltage

input

38 slow offset amplifier negative voltage

input
39 gain control positive voltage input
40 gain control negative voltage input
41 fast offset amplifier negative voltage

input
42 fast offset amplifier positive voltage

input
43 analog positive voltage input
44 analog negative voltage input

1996 Jan 17 4

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

handbook, full pagewidth

SOFF(n)

FSAD(p)

FSAD(n)

FOFF(n)

FOFF(p)

i(p)

V

CCA1

V

CCA2
AGND1
AGND2

DEC2

V

DACO(n)

V

DACO(p)

V

FSDAC(p)

V

FSDAC(n)

i(n)

V

44

1
2
3
4
5

B

6

V

7

RB

8

9
10
11

V

V

43

42

V

41

V

40

TDA8785

V

V

39

38

SOFF(p)

V

V
37

36

ref

DEC1

35

OF
34

TDA8785

33

AD7

32

AD6

31

AD5
AD4

30

AD3

29
28

AD2
AD1

27

AD0

26

V

25

CCO

OGND

24

V

23

CCD

12

DA7

13

14

15

16

17

DA6

DA5

DA4

DA3

DA2

Fig.2 Pin configuration.

18

DA1

19

DA0

20

21

DGND

CLKDAC

MBG680

22

CLKADC

1996 Jan 17 5

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

FUNCTIONAL DESCRIPTION

The TDA8785 is composed of an 8-bit ADC (30 Msps), a
wide-band gain amplifier, an input offset amplifier and an
8-bit dynamic adjustment DAC.

Input signal

Two input pins are provided to apply a differential input
signal with a wide range (100 to 1000 mV differential). It is
also possible to apply a single signal by setting a DC
voltage on one of the differential pins and supplying the
signal to the other.

Controlled gain amplifier

The gain amplifier is used to adjust the wide input signal
range to the fixed ADC input range of 1 V (p-p).

A large gain of 20 dB can be achieved with low-noise
behaviour and a large bandwidth of 100 MHz to correctly
amplify square type signals with step edges. Using pin 6,
it is possible to reduce the internal bandwidth of the gain
amplifier via an external capacitor and thus improve its
noise behaviour. The gain amplifier is controlled via an
external differential voltage (single input can also be
applied).

TDA8785

The internal 8-bit DAC operates at the ADC clock rate to
allow dynamic corrections on the input signal chain based
on the signal processing information carried out after the
digital conversion. The output voltage amplitude of the
DAC can be controlled via a different input voltage (which
can also be single) in a range of ±25% with a 150 Ω DAC
output load.

The DAC can also be used for the gain or the slow offset
control with some external DC voltage adaptations and
can be considered as a separate function of the ADC
chain. The DAC can be used independently, for example
as a video DAC.

8-bit ADC

The 8-bit ADC converts a signal of 1 V (p-p) from the
controlled gain amplifier into an 8-bit coded digital word at
a maximum rate of 30 Msps. Its reference voltage is
supplied by the general voltage regulator. The output data
format can either be binary, two’s complement or 3-state
by selecting pin OF.

When all the differential inputs on the offset amplifier
(V
0 V (equivalent to both inputs short-circuited), the output
code of the ADC is code 8.

SOFF(p)

, V

SOFF(n)

, V

FOFF(n)

, V

FOFF(p)

, V

i(p)

and V

) are at

i(n)

Input offset amplifier and adjustment DAC

The Input offset amplifier contains two different control
inputs (which can also be single):

• Slow offset control, for slow variation characteristics
(e.g. temperature, supply voltage, etc.)

• Fast offset control, for correction related to the clock
rate.

Slow offset control is carried out by an external voltage
while fast offset control is digitally carried out via the
internal 8-bit DAC with external connections of the
respective pins V

DACO(n)

, V

DACO(p)

, V

FOFF(n)

and V

FOFF(p)

Internal voltage regulator

An internal voltage regulator provides all the references for
the different blocks. A stable 2.75 V voltage reference
output is provided for use in the application environment.
One application is to connect all the slow control inputs
(V

FSDAC(p)

V

FSAD(n)

, V

FSDAC(n)

) to this reference, either to their two differential

, V

SOFF(p)

, V

SOFF(n)

, V

FSAD(p)

inputs to get the nominal settings or to one of the
differential inputs to have easy single-input control.

All these control inputs have the same control range.

.

and

1996 Jan 17 6

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter

TDA8785

with gain and offset controls

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V

CC

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
output supply voltage −0.3 +7.0 V
supply voltage difference between

V
V
V

CCA
CCD
CCA

and V
and V
and V

CCD

CCO

CCO

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

input voltage referenced to AGND −0.3 +7.0 V
clock input voltage for switching (peak-to-peak value) referenced to DGND − V

CCD

V
output current − 6mA
storage temperature −55 +150 °C
operating ambient temperature 0 70 °C
junction temperature − 150 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 75 K/W

1996 Jan 17 7

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter

TDA8785

with gain and offset controls

CHARACTERISTICS

V

CCA1=VCCA2=VCCD=VCCO

V

CCA

to V

CCD=VCCD

to V

typical values measured at V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
V
V
V
I

CCA

I

CCD

I

CCO

CCA1
CCA2
CCD
CCO

analog supply voltage 1 4.75 5.0 5.25 V
analog supply voltage 2 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
TTL output supply voltage 4.75 5.0 5.25 V
analog supply current − 80 − mA
digital supply current − 30 − mA
TTL output supply current − 9 − mA

Reference voltages (pins V

V

ref

V

line

I

LO

V

RB

output reference voltage 2.60 2.75 2.90 V
line regulation voltage V
output load current −1 −−mA
reference voltage output bottom

(decoupling)
V
∆V

osB

ADC

offset voltage bottom code 0 − V

ADC reference voltage difference between code 0 and 255 − 1 − V

Analog inputs (pins V

V

i(p-p)

V

I

I

i

Z

i

C

i

differential input voltage

V

− V

i(p)

i(n)

DC input voltage − 3.0 − V

input current − 10 −µA

input impedance − 20 − kΩ

input capacitance − 1 − pF

Fast amplifier inputs (pins V

V

FOFF(p)

V

FOFF(n)

V

I

I

i

Z

i

C

i

input voltage 0 dB gain − 500 − mV

input voltage 0 dB gain − 500 − mV

DC input voltage − V

input current − 10 −µA

input impedance − 20 − kΩ

input capacitance − 1 − pF

= 4.75 to 5.25 V; AGND, DGND and OGND short-circuited together;

CCO=VCCA

CCA=VCCD=VCCO

ref

to V

and VRB)

=−0.25 to +0.25 V; T

CCO

= 5 V and T

CCA

= 0 to 70 °C;

amb

=25°C; unless otherwise specified.

amb

= 4.75 to 5.25 V − 4 − mV

− V

− 250 − mV

I(p)

and V

); see Table 1

I(n)

RB

0 dB gain − 1000 − mV

(peak-to-peak value)

and V

FOFF(p)

20 dB gain − 100 − mV

); DC parameters

FOFF(n)

20 dB gain − 50 − mV

20 dB gain − 50 − mV

− 2.5 − V

CCA

0.25 − V

CCA −

1996 Jan 17 8

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter

TDA8785

with gain and offset controls

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Slow offset amplifier inputs (pins V

V

os

I

i

Offset reference code; T

offset voltage at ADC input V

input current − 10 −µA

=25°C

amb

OFSRE offset reference (ADC output code) V
OFSER offset reference error on code 8 tbf 0 tbf code

Gain control inputs (pins V

G

v(min)

G

v(max)

I

i

minimum voltage gain V

maximum voltage gain V

input current − 10 −µA

FSAD(p)

and V

DAC full-scale control inputs (pins V

see Table 3
V

DACO(n)

I

i

DAC output voltage (pin 8) code 0 at DAC inputs − V

input current − 2 −µA
Bandwidth adjustment node input (pin B); see Fig.6
Z

i

8-bit DAC; f

Z

o

input impedance − 500 −Ω

= 30 MHz, ramp input; T

clk

output impedance − 150 −Ω
INL integral non-linearity −±0.4 tbf LSB
DNL differential non-linearity −±0.4 tbf LSB

SOFF(p)

FSAD(n)

FSDAC(p)

amb

and V

V
V

V
V

V

V
V

) gain amplifier at 0 dB; note 1

SOFF(n)

SOFF(p)
SOFF(n)

SOFF(p)
SOFF(n)

SOFF(p)
SOFF(n)

i(p)=Vi(n)
FOFF(p)=VFOFF(n)
SOFF(p)=VSOFF(n)

=2V;
= 2.75 V

= 2.75 V;
= 2.75 V

= 3.5 V;
= 2.75 V

;

amplifier gain set at 0 dB

); see Fig.7

FSAD(p)

V

FSAD(n)
FSAD(p)

V

FSAD(n)

and V

=2V;
= 2.75 V

= 3.5 V;
= 2.75 V

FSDAC(n)

code 255 at DAC inputs;
V

FSDAC(p)

V

FSDAC(n)

=2V;
= 2.75 V

code 255 at DAC inputs;
V

FSDAC(p)

V

FSDAC(n)

= 2.75 V;
= 2.75 V

code 255 at DAC inputs;
V

FSDAC(p)

V

FSDAC(n)

= 3.5 V;
= 2.75 V

=25°C

−−0.25 − V

− 0 − V

− +0.25 − V

− 8 − code

;

;

−− 0dB

20 −−dB

) 150 Ω output load on pins V

CCA

− V

− V

− V

CCA

CCA

CCA

and V

DACO(p)

DACO(n)

− V

− 0.4 − V

− 0.5 − V

− 0.6 − V

;

1996 Jan 17 9

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter

TDA8785

with gain and offset controls

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital inputs (pins CLKDAC, CLKADC and DA7 to DA0)

V

IL

V

IH

I

IL

I

IH

Z

i

C

i

ADC output format (pin OF); see Table 2
V

IL

V

IH

V

I

I

IL

I

IH

ADC digital outputs

V

OL

V

OH

ADC and DAC switching; see Fig.4
f

clk(max)

t

CPH

t

CPL

Analog processing; note 3
INL integral non-linearity ramp input (full scale);

DNL differential non-linearity ramp input (full scale);

S/N signal-to-noise ratio

B bandwidth −3dB − 100 − MHz
t

S

LOW level input voltage 0 − 0.8 V

HIGH level input voltage 2.0 − V

LOW level input current V

HIGH level input current V

input impedance f

input capacitance f

= 0.4 V −400 −−µA

clk

= 2.7 V −− 100 µA

clk

= 10 MHz − 4 − kΩ

clk

= 10 MHz − 4.5 − pF

clk

CCD

V

LOW level input voltage 0 − 0.2 V

HIGH level input voltage 2.6 − V

input voltage in high impedance

− 1.15 − V

CCD

V

state

LOW level input current V

HIGH level input current V

= 0.4 V −370 −300 −µA

clk

= 2.7 V − 300 450 µA

clk

LOW level output voltage IOL= 2 mA 0 − 0.6 V

HIGH level output voltage IOH= −0.4 mA 2.4 − V

CCO

V

maximum clock frequency note 2 30 −−MHz

clock pulse width HIGH 12 −−ns

clock pulse width LOW 12 −−ns

−±0.7 tbf LSB

0 to 20 dB gain

±0.4 tbf LSB

0 to 20 dB gain

= 4.43 MHz

f

i

(without harmonics)

0 dB gain − 47 − dB
10 dB gain − 45 − dB
20 dB gain − 43 − dB

settling time note 4 − 2 − code

1996 Jan 17 10

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter

TDA8785

with gain and offset controls

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing

ADC

DIGITAL OUTPUTS (C

t

ds

t

h

t

d

sampling delay time − 1.5 − ns

output hold time 7 −−ns

output delay time −− 16 ns
DAC OUTPUTS (PINS V
t

SU; DAT

t

HD; DAT

t

S

data set-up time note 5 −0.3 −−ns

data hold time note 5 −− 2ns

DAC settling time (1% accuracy) RL= 150 Ω; CL=15pF − 8 − ns
3-STATE OUTPUT DELAY TIMES (see Fig.5)
t

dZH

t

dZL

t

dHZ

t

dLZ

enable HIGH − 12 14 ns

enable LOW − 10 12 ns

disable HIGH − 58 62 ns

disable LOW − 70 74 ns

Notes

1. Vos is proportional to the amplifier gain. For instance, Vos at 20 dB is the one indicated at 0 dB multiplied by 10.

2. It is recommended that the rise and fall times of the clock are >1 ns. In addition a good layout for the digital and
analog grounds is recommended.

3. Analog processing from signal inputs or fast offset amplifier inputs to ADC digital output; f
filtering on pin 6 (B).

4. Settling time is the number of code variations at the ADC output, after one clock period settling. A full-scale jump is
applied at the DAC inputs, with the DAC output (square signal) connected to the fast offset amplifier input. ADC and
DAC clock signals (CLKADC and CLKDAC) are in phase.

5. The data set-up time (t
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge and still be recognized. The data set hold time (t
of the clock, that the input data must be stable in order to be correctly registered. A negative hold time indicates that
the data may be released prior to the rising edge and still be recognized.

= 15 pF)

L

DACO(p)

SU; DAT

AND V

DACO(n)

)

= 30 MHz; no external

clk

) is the minimum period preceding the rising edge of the clock, that the input data must

) is the minimum period following the rising edge

HD; DAT

1996 Jan 17 11

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter

TDA8785

with gain and offset controls

Table 1 Output coding and input voltage (typical values; referenced to AGND, V

offset correction

BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS

STEP V

i(p) −Vi(n)

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Underflow <−0.032 0000000010000000

0 −0.032 0000000010000000
1 − 0000000110000001

. − ................

8 0 0000100010001000

. − ................

254 − 1111111001111110
255 0.968 1111111101111111

Overflow >0.968 1111111101111111

Table 2 OF input coding

OF AD0 to AD7

0 active, two’s complement
1 high impedance

open circuit

(1)

active, binary

i(p)

− V

= 1 V (p-p), 0 dB gain, no

i(n)

Note

1. Use C ≥ 10 pF to DGND.

Table 3 Input coding and DAC output voltages (typical values; referenced to V

V

FSDAC(p)=VFSDAC(n)

regardless of the offset voltage);

CCA

BINARY INPUT DATA DAC OUTPUT VOLTAGES (V)

CODE

ZL=10kΩ ZL= 150 Ω

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

V

DACO(p)VDACO(n)VDACO(p)VDACO(n)

000000000−1.0 0 −0.5 0
100000001−−−−

. ........ . . . .

12810000000−0.5 −0.5 −0.25 −0.25

. ........ . . . .

25411111110 −−−−
25511111111 0 −1.0 0 −0.5

1996 Jan 17 12

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

t

handbook, full pagewidth

input data

CLKDAC

SU; DAT

stable

t

HD; DAT

MBG682

TDA8785

3.0 V

1.4 V
0 V

3.0 V

1.4 V
0 V

The shaded areas indicate when the input data may change and be correctly registered. Data input update must be completed within 0.3 ns, after the
first rising edge of the clock (t

is negative; −0.3 ns). Data must be held at least 2 ns after the rising edge (t

SU; DAT

HD; DAT

= +2 ns).

Fig.3 Data set-up and hold times (DAC).

t

handbook, full pagewidth

CLKADC

V

− V

i(p)

i(n)

DATA

AD0 to AD7

t

sample N

DATA

N - 2

CPH

CPL

1.4 V

sample N + 1

t

ds

DATA

N - 1

t

d

sample N + 2

t

h

DATA

N

DATA

N + 1

2.4 V

1.4 V

0.4 V

MBG683

Fig.4 Timing diagram

1996 Jan 17 13

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

handbook, full pagewidth

V

CCD

OF

output
data

output
data

LOW

t

dLZ

10 %

TDA8785

HIGH Z

OF

t

dZL

50 %

15 pF

HIGH

3.3 kΩ

t

90 %

dHZ

HIGH Z

V

CCD

S1

50 %

t

dZH

50 %

TEST

t

dLZ

t

dZL

t

dHZ

t

dZH

1.15 V

S1

V

CCD

V

CCD

GND
GND

MBG684

TDA8785

fOF= 100 kHz.

Fig.5 Timing diagram and test conditions of 3-state output delay time.

10

handbook, halfpage

f

−3 DB

(MHz)

10

10

(1) f

.

−3dB

(2) Signal-to-noise ratio.
The controlled gain amplifier is set at 20 dB gain.

10

2

CB (pF)

MBG691

48

S/N

(dB)

46

44

42

3

10

2

(1)

(2)

1

−1

−1

10

101

Fig.6 Gain amplifier bandwidth and acquisition chain S/N ratio as a function of the external capacitance on pin 6.

1996 Jan 17 14

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

25

handbook, halfpage

G

v

(dB)

20

15

10

5

0

−0.75 −0.25 0 0.50−0.50 0.75
V

FSAD(p)

0.25

− V

MBG692

FSAD(n)

TDA8785

(V)

Fig.7 Typical amplifier gain (Gv) as a function of the differential input voltage; V

FSAD(p)

− V

FSAD(n)

.

1996 Jan 17 15

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

INTERNAL PIN CONFIGURATIONS

handbook, halfpage

V

CCO

AD0 to AD7

DGND

MBG685

book, halfpage

V

FSDAC(p)

V

FSAD(p)

V

FSDAC(n)

V

FSAD(n)

, V

FOFF(p)

or

, V

FOFF(n)

, V

SOFF(p)

, V

SOFF(n)

V

CCA

, V

i(p)

, V

i(n)

AGND

TDA8785

,



,

MBG686

handbook, halfpage

Fig.8 TTL data outputs.

V

CCA

500 Ω

B

AGND

MBG687

handbook, halfpage

Fig.9 Analog inputs.

V

CCA

V

RB

AGND

R

LAD

MBG688

Fig.10 Bandwidth input (B).

1996 Jan 17 16

Fig.11 VRB.

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

handbook, halfpage

V

CCD

DA7 to DA0

or

CLKDAC

or

CLKADC

DGND

40 kΩ

200 Ω

MBG689

handbook, halfpage

V

DACO(p)

150 Ω150 

Ω

TDA8785

V

DACO(n)

MBG690

Fig.12 DAC inputs.

Fig.13 DAC outputs.

1996 Jan 17 17

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

APPLICATION INFORMATION

andbook, full pagewidth

AGND2

CCA

CLKDACDA7 to DA0

V

CCA

150

Ω

150

Ω

V

SOFF(p)

V

SOFF(n)

V

FOFF(p)

V

FOFF(n)

V

FSAD(p)

V

FSAD(n)

V

DACO(p)

V

DACO(n)

V

FSDAC(p)

V

FSDAC(n)

V

CCA1VCCA2

1 2 3 4

i(p)
i(n)

43
44
37
38

42
41

39
40

9
8

10
11

OFFSET

AMPLIFIER

150 Ω 150 Ω

DAC

8

V
V

AGND1

V

12 to 19

V

CCA1

V

3.3 
nF

RB

ref

100

REGULATORS

ADC

V

2 pF

6 7 36 5 35 34

GAIN

TDA8785

CLOCK

DRIVER

20 22

nF

DEC2

8

DEC1

10
pF

OUTPUTS

CLOCK

DRIVER

100 

nF

TTL

TDA8785

OFB

1
nF

26 to 33

8

23

V

CCD

AD0

to

AD7

25

V

CCO



24

OGND

21

MBG693

DGNDCLKADC

Fig.14 Application diagram.

1996 Jan 17 18

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

22

Z

E

TDA8785

SOT307-2

e

w M

b

p

pin 1 index

44

1

w M

b

0.25

p

H

0.40

0.20

D

D

D

0.25

10.1

0.14

9.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

12

11

Z

D

B

v M

0 2.5 5 mm

scale

(1)

(1) (1)(1)

eH

H

10.1

9.9

12.9

0.8 1.3

12.3

v M

D

H

E

E

A

B

LLpQZywv θ

E

12.9

12.3

0.95

0.55

A

2

A

A

1

detail X

0.85

0.75

0.15 0.10.15

Q

(A )

3

θ

L

p

L

Z

E

D

1.2

0.8

1.2

0.8

o

10

o

0

OUTLINE
VERSION

SOT307-2

IEC JEDEC EIAJ

REFERENCES

1996 Jan 17 19

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17
95-02-04

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

TDA8785

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Jan 17 20

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter

TDA8785

with gain and offset controls

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Jan 17 21

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

NOTES

TDA8785

1996 Jan 17 22

Philips Semiconductors Preliminary specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

NOTES

TDA8785

1996 Jan 17 23

Philips Semiconductors – a worldwide company

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BUENOS AIRES, Tel. [phone], Fax. [phone]

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Piazza IV Novembre 3, 20124 MILANO,
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th

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Tel. [phone], Fax. [phone]

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Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
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Tel. [phone], Fax. [phone]

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252148 KIEV, Tel.[phone], Fax. [phone]

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276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. [phone], Fax. [phone]

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CA 94088-3409, Tel. [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCDS47 © Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

537021/1100/01/pp24 Date of release: 1996 Jan 17
Document order number: 9397 750 00575