Datasheet tda8784 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8784

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

Product specification
Supersedes data of 1998 Aug 05
File under Integrated Circuits, IC02

1999 Sep 21

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

FEATURES

• Correlated Double Sampling (CDS), AGC, 10-bit ADC
and reference regulator included,adjustable bandwidth
(CDS and AGC)

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 18 MHz

• AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps)

• CDS programmable bandwidth from 4 to 120 MHz

• AGC programmable bandwidth from 4 to 54 MHz

• Standby mode available for each block for power saving

applications (20 mW typical)

• 6 dB fixed gain analog output for analog iris control

• 8-bit and 10-bit DAC included for analog settings

• Low power consumption of only 483 mW typical

• 5 V operation and 2.5 to 5.25 V operation for the digital

outputs

• TTL compatible inputs, TTL and CMOS compatible
outputs.

TDA8784

APPLICATIONS

• CCD camera systems.

GENERAL DESCRIPTION

The TDA8784 is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, AGC and a low-power 10-bit
Analog-to-Digital Converter (ADC) together with its
reference voltage regulator.

The AGC and CDS have a bandwidth circuit controlled by
on-chip DACs via a serial interface.

A 10-bit DAC controls the ADC input clamp level.
An additional 8-bit DAC is provided for additional system

controls; its output voltage range is 1.4 V (p-p) which is
available at pin OFDOUT.

ORDERING INFORMATION

TYPE

NUMBER

TDA8784HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

NAME DESCRIPTION VERSION

PACKAGE

1999 Sep 21 2

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

ADC

res

V

i(CDS)(p-p)

G

CDS

f

CLK(max)

AGC

dyn

N

tot(rms)

E

in(rms)

P

tot

analog supply voltage 4.75 5 5.25 V
digital supply voltage 4.75 5 5.25 V
digital outputs supply voltage 2.5 3 5.25 V
analog supply current − 78 85 mA
digital supply current − 18 20 mA
digital outputs supply current f

= 18 MHz;

CLK

− 1 − mA

CL= 20 pF; ramp input
ADC resolution − 10 − bits
CDS input voltage (peak-to-peak value) − 400 1200 mV
CDS output amplifier gain − 6 − dB
maximum clock frequency f

cut(CDS)

f

cut(AGC)

= 120 MHz;
= 54 MHz

18 −−MHz

AGC dynamic range − 30 − dB
total output noise from CDS input to

ADC output (RMS value)

gain = 4.5 dB;

f

cut(CDS)

f

cut(AGC)

= 120 MHz;
= 40 MHz

− 0.125 − LSB

equivalent input noise (RMS value) gain = 34.5 dB − 125 −µV
total power consumption − 483 550 mW

1999 Sep 21 3

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

BLOCK DIAGRAM

V

handbook, full pagewidth

CPCDS
AGND1

IND INP AGND3 SHD SHP CLPDM CLK

47

TRACK-

AND-HOLD

8
5

4-BIT DAC

CUT-OFF

CCA3

454846

TRACK-

AND-HOLD

TRACK-

AND-HOLD

CLAMP

CLAMP

ref1

CLPOB

1

DGND2

CLOCK

GENERATOR

V

CCD2

OE

TDA8784

V

CCO

3738394041424344

36

35

34

33

32

OGND

D9

D8

D7

D6

AMPOUT

AGND4

AGCOUT

V

CCA1

AGND5

ADCIN

V

ref

CLPADC

31

30

29

28

27

26

25

3

D5

D4

D3

D2

D1

D0

DGND1

OFDOUT

MGM505

4
2

6 dB

10-BIT ADC

OUTPUTS

BUFFER

TDA8784

7

6
9
10

12

11

1

1

4-BIT DAC

CUT-OFF

10-BIT DAC

14

13 15 16 17 18

AGND2

V

CCA2

DACOUT

AGC

9-BIT DAC

REGULATOR

V

RT

V

RB

DEC1

STDBY

INTERFACE

2319

SENAGND6

SERIAL

21

22

SDATA

SCLK

20

8-BIT DAC

V

CCD1

24

Fig.1 Block diagram.

1999 Sep 21 4

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

PINNING

SYMBOL PIN DESCRIPTION

CLPOB 1 clamp pulse input at optical black
AGND4 2 analog ground 4
OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface)
AMPOUT 4 CDS amplifier output (fixed gain = 6 dB)
AGND1 5 analog ground 1
V

CCA1

AGCOUT 7 AGC amplifier signal output
CPCDS 8 clamp storage capacitor pin
AGND5 9 analog ground5
ADCIN 10 ADC analog signal input from AGCOUT via a short circuit
CLPADC 11 clamp control input for ADC analog input signal clamp (used with a capacitor from V
V

ref

DACOUT 13 DAC output for ADC clamp level
AGND2 14 analog ground 2
V

CCA2

V

RB

V

RT

DEC1 18 decoupling 1 (decoupled to ground via a capacitor)
AGND6 19 analog ground 6
SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off;

SCLK 21 serial clock input for the control DACs and their serial interface; see Table 1
SEN 22 enable input for the serial interface shift register (active when SEN = logic 0); see Table 1
STDBY 23 standby control pin (active HIGH); all the output bits are logic 0 when standby is enabled
V

CCD1

DGND1 25 digital ground 1
D0 26 ADC digital output 0 (LSB)
D1 27 ADC digital output 1
D2 28 ADC digital output 2
D3 29 ADC digital output 3
D4 30 ADC digital output 4
D5 31 ADC digital output 5
D6 32 ADC digital output 6
D7 33 ADC digital output 7
D8 34 ADC digital output 8
D9 35 ADC digital output 9 (MSB)
OGND 36 digital output ground
V

CCO

6 analog supply voltage 1

to ground)

ref

12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or shorted to

ground via a capacitor)

15 analog supply voltage 2
16 ADC reference voltage (BOTTOM) code 0
17 ADC reference voltage (TOP) code 1023

additional 8-bit DAC for OFD output voltage; 10-bit DACforADC clamp level and the standby mode
per block and edge pulse control); see Table 1

24 digital supply voltage 1

37 digital output supply voltage

1999 Sep 21 5

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

SYMBOL PIN DESCRIPTION

OE 38 output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance)
V

CCD2

DGND2 40 digital ground 2
CLK 41 ADC clock input
CLPDM 42 clamp pulse input at dummy pixel
SHP 43 pre-set sample-and-hold pulse input
SHD 44 data sample-and-hold pulse input
V

CCA3

INP 46 pre-set input signal from CCD
IND 47 data input signal from CCD
AGND3 48 analog ground 3

39 digital supply voltage 2

45 analog supply voltage 3

CLPOB

AGND4
OFDOUT
AMPOUT

AGND1

V

CCA1

AGCOUT

CPCDS
AGND5

ADCIN

CLPADC

V

ref

CCA3

INP

IND
47

46

14

15

V

AGND2

CCA2

V

SHD

45

44

TDA8784H

16

17

RT

RB

V

V

AGND3
48

1
2
3
4
5
6
7
8

9
10
11
12

13

DACOUT

SHP
43

18

DEC1

CLK

CLPDM

42

41

19

20

AGND6

DGND2
40

21

SCLK

SDATA

CCD2

V

39

22

SEN

OE

V

38

24 37

23

STDBY

V

CCO

CCD1

36
35
34
33
32
31
30
29
28
27
26
25

MGM506

OGND
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DGND1

Fig.2 Pin configuration.

1999 Sep 21 6

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V

CC

V

i

V

CLK(p-p)

I

o

T

stg

T

amb

T

j

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output stages supply voltage note 1 −0.3 +7.0 V
supply voltage difference

between V
between V
between V

CCA
CCA
CCD

and V
and V
and V

CCD
CCO
CCO

−1.0 +1.0 V

−1.0 +4.0 V

−1.0 +4.0 V

input voltage referenced to AGND −0.3 +7.0 V
AC input voltage for switching

referenced to DGND − V

CCD

V

(peak-to-peak value)
output current − 10 mA
storage temperature −55 +150 °C
ambient temperature −20 +75 °C
junction temperature − 150 °C

Note

1. The supply voltages V

CCA

, V

CCD

and V

may have any value between −0.3 and +7.0 V provided that the supply

CCO

voltage difference ∆VCC remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 76 K/W

1999 Sep 21 7

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

CHARACTERISTICS

V

CCA=VCCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Digital inputs

LOCK INPUT: CLK (REFERENCED TO DGND)

C
V

IL

V

IH

I

IL

I

IH

Z

i

C

i

INPUTS: SHP AND SHD
V

IL

V

IH

I

IL

I

IH

INPUTS: SEN, SCLK, SDATA, OE, STDBY, CLPDM, CLPOB AND CLPADC
V

IL

V

IH

I

i

Correlated Double Sampling (CDS)

V

i(CDS)(p-p)

I

CPCDS,INP,IND

t

CDS(min)

t

hd1

=5V; V

CCO

=3V; f

= 18 MHz; T

CLK

=25°C; unless otherwise specified.

amb

analog supply voltage 4.75 5 5.25 V
digital supply voltage 4.75 5 5.25 V
digital outputs supply voltage 2.5 3 5.25 V
analog supply current − 78 85 mA
digital supply current − 18 20 mA
digital outputs supply current CL= 20 pF on all data outputs;

− 1 − mA

ramp input

LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2.0 − V
LOW-level input current V
HIGH-level input current V
input impedance f
input capacitance f

= 0.8 V −1 − +1 µA

CLK

= 2.0 V −−20 µA

CLK

= 18 MHz − 46 − kΩ

CLK

= 18 MHz − 1 − pF

CLK

CCD

LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2.0 − V

CCD

LOW-level input current VIL= 0.6 V −−6−µA
HIGH-level input current VIH= 2.2 V − 0 −µA

LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2.0 − V

CCD

input current −2 − +2 µA

CDS input amplitude

− 400 1200 mV

(peak-to-peak value)
input current pins 8, 46

−2 − +2 µA

and 47
CDS control pulses minimum

active time

f

i(CDS1,2)=fCLK(pix);

V

= 1200 mV (p-p)

i(CDS)

12 −−ns

black-to-white transition in
1 pixel (±1 LSB typ.);

hold time INP compared to

f

cut(CDS)

f

cut(AGC)

see Fig.5 − 1 − ns

= 40 MHz;
= 40 MHz

control pulse SHP

V

V

V

1999 Sep 21 8

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

hd2

t

set(CDS)

Amplifier outputs

G

AMPOUT

Z

AMPOUT

V

AMPOUT(p-p)

V

AMPOUT(bl)

V

AGCOUT(p-p)

V

AGCOUT

Z

AGCOUT

I

AGCOUT

G

AGC(min)

G

AGC(max)

f

cut(AGC)

hold time of IND compared to

see Fig.5 − 1 − ns

control pulse SHD
CDS settling time see Fig.12; control DAC 4 bits

input code; AGC gain=0dB;
f

cut(AGC)

V

= 54 MHz;

= 1200 mV (p-p)

i(CDS)

black-to-white transition in 1
pixel (1 LSB typ.)

0000 − 12 − ns
0001 − 25 − ns
0010 − 45 − ns
0011 − 55 − ns
0100 − 105 − ns
0111 − 140 − ns
1000 − 270 − ns
1011 − 300 − ns
1111 − 365 − ns

output amplifier gain − 6 − dB
output amplifier impedance − 300 −Ω
output amplifier dynamic

− 2.4 − V

voltage (peak-to-peak value)
output amplifier black level

− 1.5 − V

voltage
AGCoutputamplifierdynamic

− 2000 − mV
voltage level (peak-to-peak
value)

AGC output amplifier

V

connected to DACOUT − V

ref

ref

− V

black level voltage
AGC output amplifier output

at 10 kHz − 5 −Ω

impedance
AGC output static drive

static −−1mA

current
minimum gain of AGC circuit AGC DAC input code = 00

− 4.5 − dB

(9-bit control)

maximum gain of AGC circuit AGC DAC input code≥319

− 34.5 − dB

(9-bit control)

cut-off frequency AGC control DAC 4-bit

input code = 00 − 54 − MHz
input code = 01 − 40 − MHz
input code = 15 − 4 − MHz

1999 Sep 21 9

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clamps

g

m(ADC)

g

m(CDS)

Analog-to-Digital Converter (ADC)

f

CLK(max)

t

CPH

t

CPL

SR

CLK

V

i(ADC)(p-p)

V

RB

V

RT

I

ADCIN

INL integral non-linearity ramp input −±0.6 ±1.5 LSB
DNL differential non-linearity ramp input −±0.2 ±0.75 LSB
t

d(s)

Total chain characteristics (CDS + AGC + ADC)

t

d

N

tot(rms)

V

offset(fl-d)

V

n(i)(eq)(rms)

Digital-to-analog converter (OFDOUT)

V

OFDOUT(p-p)

V

OFDOUT(0)

V

OFDOUT(255)

ADC clamp transconductance at clamp level − 7 − mS
CDS clamp transconductance at clamp level − 1.5 − mS

maximum clock frequency 18 −−MHz
clock pulse width HIGH 15 −−ns
clock pulse width LOW 15 −−ns
clock input slew rate (rising

10% to 90% 0.5 −−V/ns

and falling edge)
ADC input voltage level

− 2 − V
(peak-to-peak value)

ADC reference voltage output

− 1.5 − V
code 0

ADC reference voltage output

− 3.5 − V
code 1023

input current pin 10 −2 − +120 µA

sampling delay time −−5ns

time delay between
SHD and CLK

see Fig.5; 50% at rising
edges CLK and SHP: transition

− 40 − ns

full scale code 0 to 1023;

total output noise (RMS
value)

maximum offset between

f

cut(CDS)

f

cut(AGC)

V
f

cut(CDS)

f

cut(AGC)

= 40 MHz;
= 40 MHz;

= 1200 mV

i(CDS)

= 120 MHz;
= 40 MHz; note 1

= 4.5 dB − 0.125 − LSB

G

AGC

G

= 34.5 dB − 1.6 − LSB

AGC

−200 − +200 mV
CCD floating level and CCD
dark pixel level

equivalent input noise voltage
(RMS value)

additional 8-bit control DAC

AGC gain = 34.5 dB − 125 −µV
AGC gain = 4.5 dB − 150 −µV

− 1.4 − V
(OFD) output voltage
(peak-to-peak value)

DC output voltage for code 0 − 2.3 − V
DC output voltage for

− 3.7 − V
code 255

1999 Sep 21 10

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Z

OFDOUT

I

OFDOUT

ADC clamp control DAC (see Fig.8)
V

DACOUT(p-p)

V

DACOUT

Z

DACOUT

I

DACOUT

OFE

LOOP

Digital outputs (f

V

OH

V

OL

I

OZ

t

o(h)

t

o(d)

Serial interface

f

SCLK(max)

additional 8-bit control DAC

− 2000 −Ω
(OFD) output impedance

OFD output current drive static −−50 µA

ADC clamp 10-bit control

− 1 − V
DAC output voltage
(peak-to-peak value)

DC output voltage code 0 − 1.5 − V

code 1023 − 2.5 − V

ADC clamp control DAC

−−250 Ω
output impedance

DAC output current drive static −−50 µA
maximum offset error of

DAC+ ADC clamp loop

= 18 MHz; CL=20pF)

CLK

HIGH-level output voltage IOH= −1mA V

code 0 −±5−LSB
code 1023 −±5−LSB

− 0.5 − V

CCO

CCO

V
LOW-level output voltage IOL=1mA 0 − 0.5 V
output current in 3-state mode 0V<Vo<V

CCO

−20 − +20 µA
output hold time see Fig.5 8 −−ns
output delay time Ci= 20 pF; V

=10pF − 15 21 ns

C

i

C

= 20 pF; V

i

C

=10pF − 17 25 ns

i

= 20 pF; V

C

i

C

=10pF − 18 28 ns

i

maximum frequency of serial

=5V − 17 23 ns

CCO

=3V − 20 29 ns

CCO

= 2.5 V − 22 33 ns

CCO

5 −−MHz

interface

Note

1. Noisemeasurementat ADC outputs: the coupling capacitor at the input is connectedtoground, so that only the noise
contributionofthefront-endisevaluated.Thefront-endoperatesat18 Mpix with a line of 1024 pixels. The first 40 are
used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels.
The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise
is taken into account as no signal is input.

1999 Sep 21 11

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

handbook, full pagewidth

SDATA

SCLK

SEN

8
(D7 to D0)

OFD

LATCHES

8-bit DAC 10-bit DAC

D0
LSB MSB

AGC GAIN

LATCHES

AGC control frequency

SHIFT REGISTER

D1 D2 D3 D4 D510D6

8
(D7 to D0)

8
(D7 to D0)

FREQUENCY

LATCHES

control

CDS and AGC

D7 D8 D9 A0 A1 A2

LATCH

SELECTION

7
(D6 to D0)

PARTIAL

STANDBY

AND EDGE

standby

control

or edge clocks

CLAMP

REFERENCE

LATCHES

10
(D9 to D0)

MGM515

TDA8784

handbook, full pagewidth

SCLK

SEN

Fig.3 Serial interface block diagram.

t

su2

t

MSB LSB

A1 A0 D9 D7 D6 D5 D4 D3

A2SDATA

t

su1

hd4

D8

D2 D1 D0

t

su3

t

hd3

MGE373

t

su1=tsu2

= 4 ns (min.); t

hd3=thd4

= 4 ns (min.).

Fig.4 Loading sequence of control DACs input data via the serial interface.

1999 Sep 21 12

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

Table 1 Serial interface programming

ADDRESS BITS

A2 A1 A0

0 0 0 OFD output control (D7 to D0).
0 0 1 Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for

CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0.
0 1 0 AGC gain control (D8 to D0).
0 1 1 Partial standby controls for power consumption optimization. Only the 4 LSBs

(D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and

clock ADC:

D0 = 1: CDS + AGC in standby; I
D1 = 1: OFD DAC in standby; I
D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby;

I

CCA+ICCD

D3 = 1: SHP and SHD activated with falling edge (for positive pulse)
D4 = 1: CLPDM, CLPOB and CLPADC activated on HIGH level; note 1
D5 = 0: CLKADC activated with falling edge
D6 must be set to logic 0.

1 0 0 Clamp reference DAC (D9 to D0).

= 98.5 mA

DATA BITS D9 to D0

CCA+ICCD

CCA+ICCD

=48mA

=98mA

Note

1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level V
V

is connected to ground via a capacitance.

ref

Table 2 Standby selection

STDBY DATA BITS D9 to D0 I

1LOW4mA
0 active 99 mA

CCA+ICCD

ref

.

(TYP.)

1999 Sep 21 13

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

handbook, full pagewidth

INP
and
IND

SHP 1.4 V

SHD

CLK

ADC

DATA

N

1.4 V

t

hd1

t

t

d(s)

hd2

t

CDS

N

t

CPH

t

d

10%

90%

t

N − 1

t

o(h)

TDA8784

N + 3N + 2N + 1

1.4 V

o(d)

N

MGR395

Fig.5 Pixel frequency timing diagram.

1999 Sep 21 14

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

handbook, full pagewidth

CLPOB
(active HIGH)

CLPDM
(active HIGH)

1 pixel

OPTICAL BLACK HORIZONTAL FLYBLACK DUMMY VIDEOVIDEOAGCOUT

CLPDM2
CLPADC

WINDOW

CLPDB

WINDOW

TDA8784

1 pixel

CLPDMR

CLPADC

WINDOW

(1)

CLPADC
(active HIGH)

(1) When dummy pixels are not available.

(1)

MGR396

Fig.6 Line frequency timing diagram.

1999 Sep 21 15

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

handbook, halfpage

34.5

G

AGC

(dB)

4.5
0 319

TDA8784

MGM507

511

AGC control DAC input code

handbook, full pagewidth

ADC CLAMP DAC

voltage

output

(V)

2.5

1.5

Fig.7 AGC gain as a function of DAC input code.

0

ADC CLAMP control DAC input code

1023

3.4

OFD DAC

voltage

output

(V)

2.0

MGM508

0

OFD control DAC input code

255

Fig.8 DAC voltage output as a function of DAC input code.

Fig.8 DAC voltage output as a function of DAC input code.

1999 Sep 21 16

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

I

handbook, halfpage

(µA)

+100

0

−100

Fig.9 Typical clamp current for pin CPCDS.

2.85

200 mV

TDA8784

V (V)

MGR397

I

handbook, halfpage

(µA)

+300

0

−300

2.85

400 mV

Fig.10 Typical clamp current for pins IND and INP.

I

handbook, halfpage

(µA)

+200

0

V

ref

V (V)

MGR398

V (V)

−200

Fig.11 Typical clamp current for pin V

Fig.11 Typical clamp current for pin V

1999 Sep 21 17

400 mV

ref

ref

MGR399

.

.

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

160

handbook, full pagewidth

f

cut

(MHz)

120

80

(1)

40

TDA8784

MGR400

400

t

set

(ns)

(3)

(2)

(4)

300

200

100

(1) f
(2) t
(3) t
(4) t

0

cut
set
set
set

.
(10b).
(9b).
(8b).

Fig.12 CDS settling time and bandwidth.

4-bit control DAC input code

0

F05A16B27C38D49E

1999 Sep 21 18

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

60

handbook, full pagewidth

f

cut

(MHz)

40

20

0

05A16B27C38D49E

TDA8784

MGR401

F

4-bit control DAC input code

1.6

handbook, full pagewidth

V

o(CDS)(p-p)

(V)

1.2

0.8

0.4

0

0 0.4 1.2

t

=12ns.

t

=12ns.

set(CDS)

set(CDS)

Fig.13 AGC bandwidth.

Fig.13 AGC bandwidth.

0.80.2 0.6 1.41.0
V

i(CDS)(p-p)

MGR402

1.6

(V)

Fig.14 CDS output.

Fig.14 CDS output.

1999 Sep 21 19

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

N

tot(rms)
(LSB)

3

2

1

0

00 40 80 C0 100

handbook, full pagewidth

G

(1)

(2)

(3)

(4)

(5)

code

AGC

(dB)

TDA8784

MGR403

13F

(34.5)(4.5) (10.5) (16.5) (22.5) (28.5)

(1) f

= 18 MHz; control DAC = 10H; f

pix

(2) f

= 10 MHz; control DAC = 31H; f

pix

(3) f

= 5 MHz; control DAC = 43H; f

pix

(4) f

= 1 MHz; control DAC = F8H; f

pix

(5) f

= 375 kHz; control DAC = FFH; f

pix

cut(CDS)
cut(CDS)

cut(CDS)

cut(CDS)

cut(CDS)

= 120 MHz; f

= 80 MHz; f
= 35 MHz; f
= 6 MHz; f

cut(AGC)

cut(AGC)

= 4 MHz; f

Fig.15 Output noise (RMS value).

Fig.15 Output noise (RMS value).

cut(AGC)

cut(AGC)

cut(AGC)

= 40 MHz.

= 30 MHz.

= 12 MHz.

= 4 MHz.

= 4 MHz.

1999 Sep 21 20

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

APPLICATION INFORMATION

handbook, full pagewidth

5.0 V

1 µF

1 µF

CLPOB
AGND4

OFDOUT

AMPOUT

(3)

AGND1

V

AGCOUT

CPCDS
AGND5

CLPADC

CCA1

ADCIN

V

ref

1
2
3
4
5
6
7

8

9
10
11
12

CCD

AGND3

48 47 46 45 44 43 42 41 40 39 38 37

5.0 V 5.0 V

(3)

CCA3

V

from timing

generator

SHD

SHP

1 µF

IND

INP

CLK

CLPDM

DGND2

CCD2

V

2.5 to 5.25 V

(3)

OE

V

TDA8784

13 14 15 16 17 18 19 20 21 22 23 24

CCO

(3)

36
35
34
33
32
31
30
29
28
27
26
25

TDA8784

OGND
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DGND1

RT

RB

V

V

CCA2

V

AGND2

(2)

(1)

Depending on the application, the following connections must be made:
(1) The clamp level of the signal input at ADCIN can be tuned from code 00 to code 511 in 0.5 LSB steps of ADC via the serial interface

(clamp ADC activated).
(2) Clamp ADC not activated, direct connection from DACOUT to V
(3) All supply pins must be decoupled with 100 nF capacitors as close as possible to the device.

DACOUT

100

nF

5.0 V

(3)

ref

DEC1

AGND6

2.2
nF

1

1

nF

nF

.

SCLK

SDATA

serial

interface

SEN

CCD1

STDBY

V

5.0 V

(3)

MGM516

Fig.16 Application diagram.

1999 Sep 21 21

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

Power and grounding recommendations

When designing a printed-circuit board for applications
such as PC cameras, surveillance cameras, camcorders
and digital still cameras, care should be taken to minimize
the noise.

For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of
analogue components (such as classical operational
amplifiers) must be respected, particularly with respect to
power and ground connections.

The following additional recommendation is given for the
CDS input pin(s) which is/are internally connected to the
programmable gain amplifier:

• The connections between CCD interfaceandCDS input
should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analogue and digital supplies providethe best
solution. If it is not possible to do this on the board then
the analogue supply pins must be decoupled effectively
from the digital supply pins. If the same power supply
and ground are used for all the pins then the decoupling
capacitors must be placed as close as possible to the IC
package.

TDA8784

• In a two-ground system, in order to minimize the noise
though package and die parasitics, the following
recommendations must be implemented:

– All the analogue and digital supply pins must be

decoupled to the analogue ground plane. Only the
groundpinassociatedwiththe digital outputs must be
connected to the digital ground plane. All the other
ground pins should be connected to the analogue
ground plane. The analogue and digital ground
planes must be connected together at one point as
close as possible to the ground pin associated with
the digital outputs.

– The digital output pins and their associated lines

should be shielded by the digital ground plane which
can be used then as return path for digital signals.

1999 Sep 21 22

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

PACKAGE OUTLINE

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

c

y

X

36

37

25

Z

24

E

A

TDA8784

SOT313-2

e

w M

pin 1 index

48

1

e

DIMENSIONS (mm are the original dimensions)

mm

A

A1A2A3b

max.

0.20

1.60

0.05

1.45

1.35

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

b

p

0.25

w M

D

H

D

p

0.27

0.17

12

Z

D

(1) (1)(1)

cE

D

0.18

7.1

0.12

6.9

b

p

13

v M

B

v M

0 2.5 5 mm

scale

(1)

eH

H

7.1

6.9

0.5

9.15

8.85

D

E

A

B

9.15

8.85

H

E

LL

E

A

0.75

0.45

p

A

2

A

1

L

detail X

Z

D

0.12 0.10.21.0

0.95

0.55

(A )

3

L

p

Zywv θ

E

0.95

0.55

θ

o

7

o

0

OUTLINE

VERSION

SOT313-2

IEC JEDEC EIAJ

REFERENCES

1999 Sep 21 23

EUROPEAN

PROJECTION

ISSUE DATE

94-12-19
97-08-01

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesaverybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboard by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

TDA8784

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Sep 21 24

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital

TDA8784

interface for CCD cameras

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

SOLDERING METHOD

suitable

(3)(4)
(5)

suitable
suitable

(1)

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Sep 21 25

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

TDA8784

NOTES

1999 Sep 21 26

Philips Semiconductors Product specification

18 Msps, 10-bit analog-to-digital
interface for CCD cameras

TDA8784

NOTES

1999 Sep 21 27

Philips Semiconductors – a w orldwide compan y

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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
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5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545004/25/02/pp28 Date of release:1999 Sep 21 Document order number: 9397 750 06032