Datasheet TDA8783HL-C3, TDA8783HL-C2, TDA8783HL-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1998 Jul 31
File under Integrated Circuits, IC02

1999 Jun 25

INTEGRATED CIRCUITS

TDA8783

40 Msps, 10-bit analog-to-digital
interface for CCD cameras

1999 Jun 25 2

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

FEATURES

• Correlated Double Sampling (CDS), AGC, 10-bit ADC
and reference regulator included, adjustable bandwidth
(CDS and AGC)

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 40 MHz

• AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps)

• CDS programmable bandwidth from 4 to 120 MHz

• AGC programmable bandwidth from 4 to 54 MHz

• Standby mode available for each block for power saving

applications 20 mW (typ.)

• 6 dB fixed gain analog output for analog iris control

• 8-bit and 10-bit DAC included for analog settings

• Low power consumption of only 483 mW (typ.)

• 5 V operation and 2.5 to 5.25 V operation for the digital

outputs

• TTL compatible inputs, TTL and CMOS compatible
outputs.

APPLICATIONS

• CCD camera systems.

GENERAL DESCRIPTION

The TDA8783 is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, AGC and a low-power 10-bit
Analog-to-Digital Converter (ADC) together with its
reference voltage regulator.

The AGC and CDS have a bandwidth circuit controlled by
on-chip DACs via a serial interface.

A 10-bit DAC controls the ADC input clamp level.
An additional 8-bit DAC is provided for additional system

controls; its output voltage range is 1.4 V (p-p) which is
available at pin OFDOUT.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8783HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

1999 Jun 25 3

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.75 5 5.25 V

V

CCD

digital supply voltage 4.75 5 5.25 V

V

CCO

digital outputs supply voltage 2.5 3 5.25 V

I

CCA

analog supply current − 78 85 mA

I

CCD

digital supply current − 18 20 mA

I

CCO

digital outputs supply current f

CLK

= 27 MHz;

CL= 20 pF; ramp input

− 1 − mA

ADC

res

ADC resolution − 10 − bits

V

i(CDS)(p-p)

CDS input voltage (peak-to-peak value) − 400 1200 mV

G

CDS

CDS output amplifier gain − 6 − dB

f

CLK(max)

maximum clock frequency f

cut(CDS)

= 120 MHz;

f

cut(AGC)

= 54 MHz

40 −−MHz

AGC

dyn

AGC dynamic range − 30 − dB

N

tot(rms)

total noise from CDS input to ADC output
(RMS value)

gain = 4.5 dB;
f

cut(CDS)

= 120 MHz;

f

cut(AGC)

= 54 MHz

− 0.125 − LSB

P

tot

total power consumption − 483 550 mW

1999 Jun 25 4

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGM491

TRACK-

AND-HOLD

TRACK-

AND-HOLD

TRACK-

AND-HOLD

CLAMP

ref1

CLAMP

8-BIT DAC

10-BIT DAC

9-BIT DAC

6 dB

AGC

CLOCK

GENERATOR

10-BIT ADC

REGULATOR

SERIAL

INTERFACE

4-BIT DAC

CUT-OFF

OUTPUTS

BUFFER

5

4
2

7

6
9
10

14

11

12

13 15 16 17 18

20

21

22

2319

24

36

3

25

26

27

28

29

30

31

32

33

34

35

3738394041424344

454846

47

IND INP AGND3 SHD SHP CLPDM CLK

DGND2

V

CCO

V

CCD2

V

CCA3

OE

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DGND1

OFDOUT

OGND

V

CCD1

STDBY

SENAGND6

SCLK

SDATA

DEC1

V

RT

V

RB

V

CCA2

DACOUT

V

ref

CLPADC

AGND2

ADCIN

AGND5

V

CCA1

AGCOUT

AGND4

AGND1

8

CPCDS

AMPOUT

TDA8783

4-BIT DAC

CUT-OFF

1

CLPOB

+

-

1

1

1999 Jun 25 5

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

PINNING

SYMBOL PIN DESCRIPTION

CLPOB 1 clamp pulse input at optical black
AGND4 2 analog ground 4
OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface)
AMPOUT 4 CDS amplifier output (fixed gain = 6 dB)
AGND1 5 analog ground 1
V

CCA1

6 analog supply voltage 1
AGCOUT 7 AGC amplifier signal output
CPCDS 8 clamp storage capacitor pin
AGND5 9 analog ground 5
ADCIN 10 ADC analog signal input from AGCOUT via a short circuit
CLPADC 11 clamp control input for ADC analog input signal clamp (used with a capacitor from V

ref

to ground)

V

ref

12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or shorted to

ground via a capacitor)
DACOUT 13 DAC output for ADC clamp level
AGND2 14 analog ground 2
V

CCA2

15 analog supply voltage 2

V

RB

16 ADC reference voltage (BOTTOM) code 0

V

RT

17 ADC reference voltage (TOP) code 1023
DEC1 18 decoupling 1 (decoupled to ground via a capacitor)
AGND6 19 analog ground 6
SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off,

additional 8-bit DAC for OFD output voltage and 10-bit DAC for ADC clamp level and standby

mode per block and edge pulse control; see Table 1
SCLK 21 serial clock input for the control DACs and their serial interface; see Table 1
SEN 22 enable input for the serial interface shift register (active when SEN = logic 0); see Table 1
STDBY 23 standby control (active HIGH); all the output bits are logic 0 when standby is enabled
V

CCD1

24 digital supply voltage 1
DGND1 25 digital ground 1
D0 26 ADC digital output 0 (LSB)
D1 27 ADC digital output 1
D2 28 ADC digital output 2
D3 29 ADC digital output 3
D4 30 ADC digital output 4
D5 31 ADC digital output 5
D6 32 ADC digital output 6
D7 33 ADC digital output 7
D8 34 ADC digital output 8
D9 35 ADC digital output 9 (MSB)
OGND 36 digital output ground
V

CCO

37 digital output supply voltage

1999 Jun 25 6

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

OE 38 output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance)
V

CCD2

39 digital supply voltage 2
DGND2 40 digital ground 2
CLK 41 ADC clock input
CLPDM 42 clamp pulse input at dummy pixel
SHP 43 pre-set sample-and-hold pulse input
SHD 44 data sample-and-hold pulse input
V

CCA3

45 analog supply voltage 3
INP 46 pre-set input signal from CCD
IND 47 data input signal from CCD
AGND3 48 analog ground 3

SYMBOL PIN DESCRIPTION

Fig.2 Pin configuration.

1
2
3
4
5
6
7
8

9
10
11

36
35
34
33
32
31
30
29
28
27
26

13

14

15

16

17

18

19

20

21

22

23

48

47

46

45

44

43

42

41

40

39

38

12

24 37

25

TDA8783H

MGM492

OGND
D9
D8
D7

D5
D4
D3
D2
D1
D0
DGND1

CLPOB

AGND4
OFDOUT
AMPOUT

AGND1

V

CCA1

CPCDS

AGND5

CLPADC

V

ref

D6

IND

INP

V

CCA3

SHD

SHP

CLPDM

DGND2

V

CCD2

OE

V

CCO

AGND3

CLK

AGCOUT

ADCIN

AGND2

V

CCA2

V

RB

V

RT

DEC1

AGND6

SDATA

SEN

STDBY

V

CCD1

DACOUT

SCLK

1999 Jun 25 7

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

CCA

, V

CCD

and V

CCO

may have any value between −0.3 and +7.0 V provided that the supply

voltage difference ∆VCC remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage note 1 −0.3 +7.0 V

V

CCD

digital supply voltage note 1 −0.3 +7.0 V

V

CCO

output stages supply voltage note 1 −0.3 +7.0 V

∆V

CC

supply voltage difference

between V

CCA

and V

CCD

−1.0 +1.0 V

between V

CCA

and V

CCO

−1.0 +4.0 V

between V

CCD

and V

CCO

−1.0 +4.0 V

V

i

input voltage referenced to AGND −0.3 +7.0 V

V

CLK(p-p)

AC input voltage for switching
(peak-to-peak value)

referenced to DGND − V

CCD

V

I

o

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature −20 +75 °C

T

j

junction temperature − 150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 76 K/W

1999 Jun 25 8

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

CHARACTERISTICS

V

CCA=VCCD

=5V; V

CCO

=3V; f

CLK

= 27 MHz; T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

analog supply voltage 4.75 5 5.25 V

V

CCD

digital supply voltage 4.75 5 5.25 V

V

CCO

digital outputs supply voltage 2.5 3 3.6 V

I

CCA

analog supply current − 78 85 mA

I

CCD

digital supply current − 18 20 mA

I

CCO

digital outputs supply current CL= 20 pF on all data

outputs; ramp input

− 1 − mA

Digital inputs

C

LOCK INPUT: CLK (REFERENCED TO DGND)

V

IL

LOW-level input voltage 0 − 0.8 V

V

IH

HIGH-level input voltage 2.0 − V

CCD

V

I

IL

LOW-level input current V

CLK

= 0.8 V −1 − +1 µA

I

IH

HIGH-level input current V

CLK

= 2.0 V −−20 µA

Z

i

input impedance f

CLK

= 27 MHz − 46 − kΩ

C

i

input capacitance f

CLK

= 27 MHz − 1 − pF
INPUTS: SHP AND SHD
V

IL

LOW-level input voltage 0 − 0.8 V

V

IH

HIGH-level input voltage 2.0 − V

CCD

V

I

IL

LOW-level input current VIL= 0.6 V −−6−µA

I

IH

HIGH-level input current VIH= 2.2 V − 0 −µA
INPUTS: SEN, SCLK, SDATA,OE,STDBY, CLPDM, CLPOB AND CLPADC
V

IL

LOW-level input voltage 0 − 0.8 V
V

IH

HIGH-level input voltage 2.0 − V

CCD

V

I

i

input current −2 − +2 µA

Correlated Double Sampling; CDS

V

i(CDS)(p-p)

CDS input amplitude

(peak-to-peak value)

− 400 1200 mV

I

CPCDS,INP,IND

input current pins 8, 46 and 47 −2 − +2 µA
t

CDS(min)

CDS control pulses minimum

active time

f

i(CDS1,2)=fCLK(pix)

;

V

i(CDS)(p-p)

= 600 mV
black-to-white transition in
1 pixel (±1 LSB typ.);
f

cut(CDS)

= 120 MHz;

f

cut(AGC)

= 54 MHz

8 −−ns

t

hd1

hold time INP compared to control
pulse SHP

see Fig.5 − 1 − ns

t

hd2

hold time of IND compared to
control pulse SHD

see Fig.5 − 1 − ns

1999 Jun 25 9

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

t

set(CDS)

CDS setting time control DAC 4 bits input

code; AGC gain = 0 dB;
f

cut(AGC)

= 54 MHz;

V

i(CDS)

= 600 mV (p-p)
black-to-white transition in
1 pixel (±1 LSB typ.)

0000 − 8 − ns
0001 − 21 − ns
0010 − 42 − ns
0011 − 52 − ns
0100 − 82 − ns
0111 − 94 − ns
1000 − 195 − ns
1011 − 219 − ns
1111 − 280 − ns

Amplifier outputs

G

AMPOUT

output amplifier gain − 6 − dB

Z

AMPOUT

output amplifier impedance − 300 −Ω

V

AMPOUT(p-p)

output amplifier dynamic voltage
(peak-to-peak value)

− 2.4 − V

V

AMPOUT(bl)

output amplifier black level
voltage

− 1.5 − V

V

AGCOUT(p-p)

AGC output amplifier dynamic
voltage level (peak-to-peak value)

− 2000 − mV

V

AGCOUT(bl)

AGC output amplifier black level
voltage

V

ref

connected to DACOUT − V

ref

− V

Z

AGCOUT(bl)

AGC output amplifier output
impedance

at 10 kHz − 5 −Ω

I

AGCOUT

AGC output static drive current static −−1mA

G

AGC(min)

minimum gain of AGC circuit AGC DAC input code = 00

(9-bit control)

− 4.5 − dB

G

AGC(max)

maximum gain of AGC circuit AGC DAC input code ≥ 319

(9-bit control)

− 34.5 − dB

f

cut(AGC)

cut-off frequency AGC 4-bit control DAC

input code = 00 − 54 − MHz
input code = 15 − 4 − MHz

Clamps

g

m(ADC)

ADC clamp transconductance at clamp level − 7 − mS

g

m(CDS)

CDS clamp transconductance at clamp level − 1.5 − mS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Jun 25 10

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Analog-to-Digital Converter; ADC

f

CLK(max)

maximum clock frequency 40 −−MHz

t

CPH

clock pulse width HIGH 12 −−ns

t

CPL

clock pulse width LOW 12 −−ns

SR

CLK

clock input slew rate (rising and
falling edge)

10% to 90% 0.5 −−V/ns

V

i(ADC)(p-p)

ADC input voltage level
(peak-to-peak value)

− 2 − V

V

RB

ADC reference voltage output
code 0

− 1.5 − V

V

RT

ADC reference voltage output
code 1023

− 3.5 − V

I

ADCIN

ADC input current −2 − +120 µA
INL integral non-linearity ramp input −±0.6 ±1.5 LSB
DNL differential non-linearity ramp input −±0.2 ±0.75 LSB
t

d(s)

sampling delay time −−5ns

Total chain characteristics (CDS + AGC + ADC)

t

d

time delay between SHD and

CLK

50% at rising edges
CLK and SHD: transition full
scale code 0 to 1023;
f

cut(CDS)

= 120 MHz;

f

cut(AGC)

= 54 MHz;

V

i(CDS)

= 600 mV

− 30 − ns

N

o(rms)

output noise (RMS value) f

cut(CDS)

= 120 MHz;

f

cut(AGC)

= 40 MHz; note 1

G

AGC

= 4.5 dB − 0.125 − LSB

G

AGC

= 34.5 dB − 1.6 − LSB

V

offset(h-d)

maximum offset between CCD

heating level and CCD dark pixel

level

−200 − +200 mV

V

n(i)(eq)(rms)

equivalent input noise voltage

(RMS value)

AGC gain = 34.5 dB − 125 −µV
AGC gain = 4.5 dB − 150 −µV

Digital-to-Analog Converters (OFDOUT DAC)

V

OFDOUT(p-p)

additional 8-bit control DAC

(OFD) output voltage

(peak-to-peak value)

− 1.4 − V

V

OFDOUT(0)

DC output voltage for code 0 − 2.3 − V
V

OFDOUT(255)

DC output voltage for code 255 − 3.7 − V
Z

OFDOUT

additional 8-bit control DAC

(OFD) output impedance

− 2000 −Ω

I

OFDOUT

OFD output current drive static −−50 µA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Jun 25 11

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Notes

1. Noise measurement at ADC outputs: the coupling capacitor at the input is connected to ground, so that only the noise
contribution of the front-end is evaluated. The front-end operates at 18 Mpix with a line of 1024 pixels. The first 40 are
used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels.
The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise
is taken into account as no signal is input.

2. Depending on operating pixel frequency, the output voltage and capacitance must be determined according to the
output delay timings (t

o(d)

).

ADC clamp control DAC (see Fig.8)
V

DACOUT(p-p)

ADC clamp 10-bit control DAC
output voltage (peak-to-peak
value)

− 1 − V

V

DACOUT

DC output voltage code 0 − 1.5 − V

code 1023 − 2.5 − V

Z

DACOUT

ADC clamp control DAC output
impedance

−−250 Ω

I

DACOUT

DAC output current drive static −−50 µA

OFE

LOOP

maximum offset error of
DAC + ADC clamp loop

code 0 −±5−LSB
code 1023 −±5−LSB

Digital outputs (f

CLK

= 40 MHz; CL= 20 pF); note 2

V

OH

HIGH-level output voltage IOH= −1mA V

CCO

− 0.5 − V

CCO

V

V

OL

LOW-level output voltage IOL=1mA 0 − 0.5 V

I

OZ

output current in 3-state mode 0V<Vo<V

CCO

−20 − +20 µA

t

o(h)

output hold time 8 −−ns

t

o(d)

output delay time Ci= 20 pF; V

CCO

=5V − 17 23 ns

C

i

=10pF − 15 21 ns

C

i

= 20 pF; V

CCO

=3V − 20 29 ns

C

i

=10pF − 17 25 ns

C

i

= 20 pF; V

CCO

= 2.5 V − 22 33 ns

C

i

=10pF − 18 28 ns

Serial interface

f

SCLK(max)

maximum frequency of serial
interface

5 −−MHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Jun 25 12

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Fig.3 Serial interface block diagram.

handbook, full pagewidth

OFD

LATCHES

AGC GAIN

LATCHES

FREQUENCY

LATCHES

PARTIAL

STANDBY

AND EDGE

CLAMP

REFERENCE

LATCHES

LATCH

SELECTION

D0
LSB MSB

SDATA

SCLK

SEN

8-bit DAC 10-bit DAC

MGM515

AGC control frequency

control

CDS and AGC

standby

control

or edge clocks

D1 D2 D3 D4 D510D6

SHIFT REGISTER

D7 D8 D9 A0 A1 A2

8
(D7 to D0)

8
(D7 to D0)

8
(D7 to D0)

7
(D6 to D0)

10
(D9 to D0)

Fig.4 Loading sequence of control DACs input data via the serial interface.

handbook, full pagewidth

MGE373

A2SDATA

SCLK

SEN

A1 A0 D9 D7 D6 D5 D4 D3

MSB LSB

D2 D1 D0

t

hd3

t

su3

t

su1

t

hd4

t

su2

D8

t

su1=tsu2

= 4 ns (min.); t

hd3=thd4

= 4ns (min.).

1999 Jun 25 13

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Table 1 Serial interface programming

Note

1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level V

ref

.

V

ref

is connected to ground via a capacitor.

ADDRESS BITS

DATA BITS D9 to D0

A2 A1 A0

0 0 0 OFD output control (D7 to D0).
0 0 1 Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for

CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0.
0 1 0 AGC gain control (D8 to D0).
0 1 1 Partial standby controls for power consumption optimization. Only the 4 LSBs

(D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and

clock ADC:

D0 = 1: CDS + AGC in standby; I

CCA+ICCD

=48mA

D1 = 1: OFD DAC in standby; I

CCA+ICCD

=98mA

D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby;
I

CCA+ICCD

= 98.5 mA
D3 = 1: SHP and SHD activated with falling edge (for positive pulse)
D4 = 1: CLPDM, CLPOB and CLPADC activated on high level; note 1
D5 = 0: CLKADC activated with falling edge
D6 must be set to logic 0.

1 0 0 Clamp reference DAC (D9 to D0).

Table 2 Standby selection

STDBY DATA BITS D9 to D0 I

CCA+ICCD

(TYP.)

1 LOW 4 mA
0 active 99 mA

1999 Jun 25 14

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Fig.5 Pixel frequency timing diagram.

handbook, full pagewidth

MGR395

N

INP
and
IND

SHP 1.4 V

SHD

CLK

ADC

DATA

N + 3N + 2N + 1

N − 1

N

N

t

CDS

t

CPH

t

d(s)

t

d

t

o(d)

t

o(h)

t

hd1

t

hd2

90%

10%

1.4 V

1.4 V

1999 Jun 25 15

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Fig.6 Line frequency timing diagram.

(1) When dummy pixels are not available.

handbook, full pagewidth

MGR396

CLPADC
(active HIGH)

CLPDM
(active HIGH)

CLPOB
(active HIGH)

OPTICAL BLACK HORIZONTAL FLYBLACK DUMMY VIDEOVIDEOAGCOUT

CLPDM2
CLPADC

WINDOW

CLPDB

WINDOW

(1)

(1)

1 pixel

CLPDMR

CLPADC

WINDOW

1 pixel

1999 Jun 25 16

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Fig.7 AGC gain as a function of DAC input code.

handbook, halfpage

MGM507

G

AGC

(dB)

34.5

4.5
0 319

511

AGC control DAC input code

Fig.8 DAC voltage output as a function of DAC input code.

handbook, full pagewidth

0

ADC CLAMP DAC

voltage

output

(V)

2.5

1.5
1023

ADC CLAMP control DAC input code

MGM508

0

OFD DAC

voltage

output

(V)

3.4

2.0
255

OFD control DAC input code

1999 Jun 25 17

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Fig.9 Typical clamp current for pin CPCDS.

handbook, halfpage

MGR397

+100

0

−100

I

(µA)

V (V)

200 mV

2.85

Fig.10 Typical clamp current for pins IND and INP.

handbook, halfpage

MGR398

+300

0

−300

I

(µA)

V (V)

400 mV

2.85

Fig.11 Typical clamp current for pin V

ref

.

handbook, halfpage

MGR399

+200

0

−200

I

(µA)

V (V)

400 mV

V

ref

1999 Jun 25 18

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Fig.12 CDS setting time and bandwidth.

(1) f

cut

.

(2) t

set

(10 bits accuracy).

(3) t

set

(9 bits accuracy).

(4) t

set

(8 bits accuracy).

handbook, full pagewidth

160

120

40

0

80

MGR441

F05A16B27C38D49E

4-bit control DAC input code

f

cut

(MHz)

300

250

50

0

150

100

200

t

set

(ns)

(2)

(4)

(1)

(3)

1999 Jun 25 19

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Fig.13 AGC bandwidth.

handbook, full pagewidth

F

60

40

20

0

05A16B27C38D49E

MGR401

4-bit control DAC input code

f

cut

(MHz)

Fig.14 CDS output.

handbook, full pagewidth

1.6

1.6

1.2

0.4

0

0 0.4 1.2

0.8

0.80.2 0.6 1.41.0

MGR442

V

i(CDS)(p-p)

(V)

V

o(CDS)(p-p)

(V)

(2)

(3)

(4)

(6)

(5)

(1)

(1) t

set(CDS)

=12ns

(2) t

set(CDS)

=10ns

(3) t

set(CDS)

=8ns

(4) t

set(CDS)

=7ns

(5) t

set(CDS)

=6ns

(6) t

set(CDS)

=5ns

1999 Jun 25 20

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Fig.15 Output noise (RMS value).

(1) f

pix

= 27MHz; control DAC= 00H; f

cut(CDS)

= 120MHz; f

cut(AGC)

= 54MHz.

(2) f

pix

= 18MHz; control DAC= 10H; f

cut(CDS)

= 120MHz; f

cut(AGC)

= 40MHz.

(3) f

pix

= 10MHz; control DAC= 31H; f

cut(CDS)

= 80MHz; f

cut(AGC)

= 30MHz.

(4) f

pix

= 5MHz; control DAC= 43H; f

cut(CDS)

= 35MHz; f

cut(AGC)

= 12MHz.

(5) f

pix

= 1MHz; control DAC= F8H; f

cut(CDS)

= 6MHz; f

cut(AGC)

= 4MHz.

(6) f

pix

= 375kHz; control DAC= FFH; f

cut(CDS)

= 4MHz; f

cut(AGC)

= 4MHz.

handbook, full pagewidth

13F

code

3

2

1

0

00 40 80 C0 100

(34.5)(4.5) (10.5) (16.5) (22.5) (28.5)

MGR443

G

AGC

(dB)

N

tot(rms)
(LSB)

(3)

(2)

(5)

(4)

(6)

(1)

1999 Jun 25 21

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

APPLICATION INFORMATION

Fig.16 Application diagram.

Depending on the application, the following connections must be made:
(1) The clamp level of the signal input at ADCIN can be tuned from code 00 to code 511 in 0.5 LSB steps of ADC via the serial interface

(clamp ADC activated).

(2) Clamp ADC not activated, direct connection from DACOUT to V

ref

.

(3) All supply pins must be decoupled with 100 nF capacitors as close as possible to the device.

handbook, full pagewidth

MGM504

1
2
3
4
5
6
7

8

9
10
11

36

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

35
34
33
32
31
30
29
28
27
26

12

25

TDA8783

OGND
D9
D8
D7

D5
D4
D3
D2
D1
D0
DGND1

CLPOB

AGND4

OFDOUT

AMPOUT

AGND1

V

CCA1

CPSDS
AGND5

CLPADC

V

ref

D6

IND

INP

V

CCA3

SHD

SHP

CLPDM

DGND2

V

CCD2

OE

V

CCO

AGND3

CLK

AGCOUT

ADCIN

AGND2

V

CCA2

V

RB

V

RT

DEC1

AGND6

SDATA

SEN

STDBY

V

CCD1

DACOUT

SCLK

from timing

generator

serial

interface

5.0 V 5.0 V

5.0 V

5.0 V

CCD

2.5 to 5.25 V

(3)

1 µF

1 µF

(3)

(3)

(2)

(1)

(3)

5.0 V

(3)

100

nF

1

nF

2.2
nF

1

nF

(3)

220

nF

1999 Jun 25 22

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Power and grounding recommendations

When designing a printed-circuit board for applications
such as PC cameras, surveillance cameras, camcorders
and digital still cameras, care should be taken to minimize
the noise.

For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of
analogue components (such as classical operational
amplifiers) must be respected, particularly with respect to
power and ground connections.

The following additional recommendation is given for the
CDS input pin(s) which is/are internally connected to the
programmable gain amplifier:

• The connections between CCD interface and CDS input
should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analogue and digital supplies provide the best
solution. If it is not possible to do this on the board then
the analogue supply pins must be decoupled effectively
from the digital supply pins. If the same power supply
and ground are used for all the pins then the decoupling
capacitors must be placed as close as possible to the IC
package.

• In a two-ground system, in order to minimize the noise
though package and die parasitics, the following
recommendations must be implemented:

– All the analogue and digital supply pins must be

decoupled to the analogue ground plane. Only the
ground pin associated with the digital outputs must be
connected to the digital ground plane. All the other
ground pins should be connected to the analogue
ground plane. The analogue and digital ground
planes must be connected together at one point as
close as possible to the ground pin associated with
the digital outputs.

– The digital output pins and their associated lines

should be shielded by the digital ground plane which
can be used then as return path for digital signals.

1999 Jun 25 23

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

PACKAGE OUTLINE

UNIT

A

max.

A1A2A3b

p

cE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

1.60

0.20

0.05

1.45

1.35

0.25

0.27

0.17

0.18

0.12

7.1

6.9

0.5

9.15

8.85

0.95

0.55

7
0

o
o

0.12 0.10.21.0

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2

94-12-19
97-08-01

D

(1) (1)(1)

7.1

6.9

H

D

9.15

8.85

E

Z

0.95

0.55

D

b

p

e

E

B

12

D

H

b

p

E

H

v M

B

D

Z

D

A

Z

E

e

v M

A

1

48

37

36

25

24

13

θ

A

1

A

L

p

detail X

L

(A )

3

A

2

X

y

c

w M

w M

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

1999 Jun 25 24

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Jun 25 25

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1999 Jun 25 26

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

NOTES

1999 Jun 25 27

Philips Semiconductors Product specification

40 Msps, 10-bit analog-to-digital interface
for CCD cameras

TDA8783

NOTES

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999 66

Philips Semiconductors – a worldwide company

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Tel. [phone], Fax. [phone]
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Romania: see Italy
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Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

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For all other countries apply to: Philips Semiconductors,
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Argentina: see South America
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Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

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Hungary: seeAustria
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Printed in The Netherlands 545004/25/02/pp28 Date of release: 1999 Jun 25 Document order number: 9397 750 06031