Datasheet tda8779h DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8779H

10-bit converter interface
(ADC/DAC) for quadrature
transceiver

Product specification
Supersedes data of 1999 Jan 18
File under Integrated Circuits, IC02

1999 Sep 16

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

FEATURES

• Two 10-bit ADCs with multiplexed outputs

• Two 10-bit DACs with multiplexed inputs

• Sampling rate for the ADCs and DACs up to 20 MHz

• Digital outputs (for the ADC) and inputs (for the DAC)

are TTL/CMOS compatible

• Internal reference voltage regulator

• Power dissipation 520 mW

• Standby mode.

APPLICATIONS

• Wireless communication.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA1

analog supply voltage for
the ADC part

V

CCD1

digital supply voltage for the
ADC part

V

CCA2

analog supply voltage for
the DAC part

V

CCD2

digital supply voltage for the
DAC part

V

CCO

I

CCA

I

CCD

I

CCO

f

CLK(ADC)max

output stage supply voltage 2.7 3.0 3.3 V
analog supply current 59 74 85 mA
digital supply current 15 23 35 mA
output stage supply current ramp input;

f

=20MHz

CLK

maximum clock frequency
for the ADC part

INLA integral non linearity for the

ADC part

DNLA differential non linearity for

the ADC part

f

CLK(DAC)max

maximum clock frequency

full-scale; ramp input;
f

=20MHz

CLK

full-scale; ramp input;

=20MHz

f

CLK

for the DAC part

INLD integral non linearity for the

DAC part

DNLD differential non linearity for

the DAC part

P

tot

total power dissipation − 520 745 mW

full-scale; ramp input;

=20MHz

f

CLK

full-scale; ramp input;
f

=20MHz

CLK

GENERAL DESCRIPTION

The TDA8779 contains two 10-bit high speed ADCs and
two 10-bit DACs for wireless communication (for use in
transceiver modules). This device converts two analog
input signals (channels I and Q) and digital inputs
(D0 to D9) at a maximum sampling rate of 20 MHz.
The input bias voltages for the analog input voltages are
provided internally at the middle code. The analog input
and output voltages are AC coupled.

The data sampling is performed on the rising edge of the
clock for ADCs and DACs.

All reference voltages are generated internally.

4.75 5.0 5.5 V

4.75 5.0 5.5 V

4.75 5.0 5.5 V

4.75 5.0 5.5 V

− 7 − mA

20 −−MHz

−±2.25 ±4 LSB

− +1.55 to −0.9 +2.8 to −1.1 LSB

20 −−MHz

−±0.4 ±1.25 LSB

−±0.35 ±1.5 LSB

1999 Sep 16 2

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8779H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);

body 10 × 10 × 1.75 mm

BLOCK DIAGRAM

4

6

V

CCA1

INPUT

BIAS

DEC2 DEC3

DEC1

7

23

REFERENCE
REGULATOR

10-BIT

ADC

10-BIT

ADC

10

10

5

LATCHES

handbook, full pagewidth

INI

INQ

PACKAGE

V

CCD1

31

DGND1

28

TDA8779

10 10

MUX

STDBYA

BUFFER

TDA8779H

SOT307-2

29

32

OE

34-43

44

D0A to D9A

V

CCO

AGND1

OUTI

OUTQ

AGND2

30

1

BUFFER

9

BUFFER

11

13

8

V

CCA2

10-BIT

DAC

10-BIT

DAC

REFERENCE
REGULATOR

10

DEC5

DEC4

12

10

10

LATCHES

V

14

CCD2

10 10

BUFFER

25

DGND2

15-24

27

STDBYD

26

33

CLKA
CLKD

OGND

D0D to D9D

MGG075

Fig.1 Block diagram.

1999 Sep 16 3

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

PINNING

SYMBOL PIN DESCRIPTION

AGND1 1 analog ground 1
DEC1 2 decoupling input 1
DEC2 3 decoupling input 2
INI 4 I channel ADC input
DEC3 5 decoupling input 3
INQ 6 Q channel ADC input
V

CCA1

V

CCA2

OUTI 9 I channel DAC analog output
DEC4 10 decoupling input 4
OUTQ 11 Q channel DAC analog output
DEC5 12 decoupling input 5
AGND2 13 analog ground 2
V

CCD2

D0D 15 multiplexed input for the DACs; bit 0
D1D 16 multiplexed input for the DACs; bit 1
D2D 17 multiplexed input for the DACs; bit 2
D3D 18 multiplexed input for the DACs; bit 3
D4D 19 multiplexed input for the DACs; bit 4
D5D 20 multiplexed input for the DACs; bit 5
D6D 21 multiplexed input for the DACs; bit 6
D7D 22 multiplexed input for the DACs; bit 7
D8D 23 multiplexed input for the DACs; bit 8
D9D 24 multiplexed input for the DACs; bit 9
DGND2 25 digital ground 2
CLKD 26 transmission block clock
STDBYD 27 power standby for the DAC part (active HIGH)
DGND1 28 digital ground 1
STDBYA 29 power standby for the ADC part (active HIGH)
CLKA 30 reception block clock
V

CCD1

OE 32 ADCs digital output enable (3-state output); (active LOW)
OGND 33 input/output ground
D0A 34 I and Q digital outputs; bit 0
D1A 35 I and Q digital outputs; bit 1
D2A 36 I and Q digital outputs; bit 2
D3A 37 I and Q digital outputs; bit 3
D4A 38 I and Q digital outputs; bit 4
D5A 39 I and Q digital outputs; bit 5
D6A 40 I and Q digital outputs; bit 6

7 analog supply voltage 1 for ADC part (5 V)
8 analog supply voltage 2 for DAC part (5 V)

14 digital supply voltage 2 for DAC part (5 V)

31 digital supply voltage 1 for ADC part (5 V)

TDA8779H

1999 Sep 16 4

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

SYMBOL PIN DESCRIPTION

D7A 41 I and Q digital outputs; bit 7
D8A 42 I and Q digital outputs; bit 8
D9A 43 I and Q digital outputs; bit 9
V

CCO

handbook, full pagewidth

44 output supply voltage (2.7 to 3.3 V)

CCO

D8A

AGND1

DEC1
DEC2

INI

DEC3

INQ

V

CCA1

V

CCA2

OUTI

DEC4

OUTQ

D9A
43

42

D7A
41

TDA8779H

V
44

1
2
3
4
5
6
7
8

9
10
11

D6A
40

D5A
39

D4A
38

D3A
37

D2A
36

D1A
35

D0A
34

33
32
31
30
29
28
27
26
25
24
23

OGND
OE
V

CCD1

CLKA
STDBYA
DGND1
STDBYD
CLKD
DGND2
D9D
D8D

TDA8779H

12

13

14

15

16

D0D

CCD2

V

D1D

DEC5

AGND2

Fig.2 Pin configuration.

17

D2D

18

D3D

19

D4D

20

D5D

21

D6D

22

D7D

MGG074

1999 Sep 16 5

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA1

V

CCA2

V

CCD1

V

CCD2

V

CCO

∆V

I

o

V

i

V

clk(p-p)

T

stg

T

amb

T

j

CC

analog supply voltage for the ADC part −0.3 +6.0 V
analog supply voltage for the DAC part −0.3 +6.0 V
digital supply voltage for the ADC part −0.3 +6.0 V
digital supply voltage for the DAC part −0.3 +6.0 V
output stage supply voltage −0.3 +6.0 V
voltage difference between

V
V
V

CCA
CCA
CCD

− V

− V

− V

CCD
CCO
CCO

−1.0 +1.0 V

−1.0 +4.0 V

−1.0 +4.0 V

output current − 10 mA
input voltage with respect to AGND −0.3 +6.0 V
AC input switching voltage

with respect to DGND − V

CCD

V

(peak-to-peak value)
storage temperature −55 +150 °C
ambient temperature −20 +75 °C
junction temperature − 150 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 75 K/W

CHARACTERISTICS

V

CCA=V7

V

CCO=V44

T

amb

and V8 to V1and V13= 4.75 to 5.5 V; V

to V33= 2.7 to 3.3 V; AGND1, AGND2, OGND, DGND1 and DGND2 are shorted together;

= −20 to +75 °C; measured typically at V

CCD=V31

CCA=VCCD

and V14 to V28and V25= 4.75 to 5.5 V;

= 5 V and V

= 3.0 V; CL= 15 pF; T

CCO

=25°C; unless

amb

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA1

analog supply voltage for

4.75 5.0 5.5 V

the ADC part

V

CCD1

digital supply voltage for the

4.75 5.0 5.5 V

ADC part

V

CCA2

analog supply voltage for

4.75 5.0 5.5 V

the DAC part

V

CCD2

digital supply voltage for the

4.75 5.0 5.5 V

DAC part

V

CCO

output stage supply voltage 2.7 3.0 3.3 V

1999 Sep 16 6

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆V

CC

I

CCA

I

CCD

I

CCO

I

CCA1(stb)

I

CCA2(stb)

ADC part

CLOCK INPUT
V

IL

V

IH

I

IL

I

IH

DIGITAL INPUTS: PINS OE AND STDBYA
V

IL

V

IH

I

IL

I

IH

ANALOG INPUTS
I

IL

I

IH

V

i(p-p)

V

i(p-p)over

Z

I

C

I

DIGITAL OUTPUTS: D0A TO D9A
V

OL

V

OH

I

oZ

SWITCHING CHARACTERISTICS;T
f

CLK(max)

t

CH

voltage difference between T

V

− V
V
V

CCA
CCA
CCD

− V

− V

CCD
CCO
CCO

amb

=25°C

−0.2 − +0.2 V
0 − 2.8 V

0 − 2.8 V
analog supply current 59 74 85 mA
digital supply current 15 23 35 mA
output stage supply current ramp input;

f

=20MHz

CLK

analog standby current for

− 715mA

− 0.7 3 mA

the ADC part
analog standby current for

− 2.5 5 mA

the DAC part

LOW-level input voltage T
HIGH-level input voltage T

=25°C0−0.8 V

amb

=25°C 2.0 − V

amb

CCD1

V
LOW-level input current −10 − +10 µA
HIGH-level input current −10 − +10 µA

LOW-level input voltage T
HIGH-level input voltage T

=25°C0−0.8 V

amb

=25°C 2.0 − V

amb

CCD1

V
LOW-level input current −10 − +10 µA
HIGH-level input current −10 − +10 µA

LOW-level input current for code 0 −−91 −µA
HIGH-level input current for code 1023 − 80 −µA
analog input voltage

full-scale 1.52 1.57 1.62 V

(peak-to-peak value)
maximum analog input

overvoltage
(peak-to-peak value)

overvoltage for
fi= 4.43 MHz;
T

=25°C

amb

−− 3.0 V

input impedance − 10 − kΩ
input capacitance − 3 − pF

LOW-level output voltage Io=1mA 0 − 0.5 V
HIGH-level output voltage Io= −1mA V
output current in 3-state

0.5V<Vo<V

− 0.5 V −20 − +20 µA

CCO

− 0.5 − V

CCO

CCO

V

mode

=25°C (see Fig.3)

amb

maximum clock frequency 20 −−MHz
clock pulse width HIGH 20 −−ns

1999 Sep 16 7

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

CL

t

r

t

f

ANALOG SIGNAL PROCESSING

Linearity

INLA integral non linearity ramp input;

DNLA differential non linearity

Noise floor;

NF noise floor f

Harmonics;

THD total harmonic distortion f

Spurious free dynamic range

SFDR spurious free dynamic

Matching between the I and Q channels

∆V amplitude matching fi= 4.43 MHz;

∆ϕ phase matching f

Bandwidth

B bandwidth (maximum

TIMING (THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME td); CL= 15 pF; T
t

ds

t

h

t

d

3-STATE OUTPUT DELAY TIMES;T
t

dZH

t

dZL

t

dHZ

t

dLZ

clock pulse width LOW 20 −−ns
clock rise time − 4 − ns
clock fall time − 4 − ns

−±2.25 ±4 LSB

f

=20MHz

CLK

− +1.55 to −0.9 +2.8 to −1.1 LSB

maximum missing codes

full-scale; ramp input;

=20MHz

f

CLK

guaranteed: 20

note 1

= 4.43 MHz; 20 Msps −55 −71 − dB

i

note 2

= 4.43 MHz; 20 Msps −50 −58 − dB

i

fi= 4.43 MHz; 20 Msps 50 58 − dB

range

− 0.1 6 %

f

= 20 MHz;

CLK

T

=25°C

amb

attenuation of −0.3 dB)

= 4.43 MHz;

i

f

= 20 MHz;

CLK

T

=25°C

amb

full-scale sine wave;
T

=25°C

amb

50% full-scale sine wave;
T

=25°C

amb

− 0.05 2 deg

30 −−MHz

30 −−MHz

=25°C (see Fig.3)

amb

sampling delay time −− 11 ns
output hold time 5 −−ns
output delay time V

=25°C (see Fig.4)

amb

= 3.3 V − 12 − ns

CCO

V

= 2.7 V − 13 − ns

CCO

output delay enable HIGH − 10 − ns
output delay enable LOW − 7.7 − ns
output delay disable HIGH − 15.5 − ns
output delay disable LOW − 14.9 − ns

1999 Sep 16 8

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

STANDBY MODE OUTPUT DELAY TIMES; STDBYA; T
t

d(stb)LH

standby delay
(LOW-to-HIGH transition)

t

d(stb)HL

start-up delay
(HIGH-to-LOW transition)

CROSSTALK ON THE ADC

α

ct

crosstalk on the ADC f

CLK(DAC)

f

CLK(ADC)

T

amb

switching between input
codes 0 and 1023; one
ADC 1 V (p-p) sine wave
at 4 MHz and the other
ADC set at the middle
code

DAC part

DIGITAL INPUTS: D0D TO D9D AND CLKD
V

IL

V

IH

I

IL

I

IH

LOW-level input voltage T
HIGH-level input voltage T

amb
amb

LOW-level input current −200 − 0 µA
HIGH-level input current −10 − +10 µA

DIGITAL INPUT; STDBYD
V

IL

V

IH

I

IL

I

IH

TIMING;T
f

CLK(max)

t

CH

t

CL

t

r

t

f

t

s

t

h

LOW-level input voltage T
HIGH-level input voltage T

amb
amb

LOW-level input current −10 − +10 µA
HIGH-level input current −10 − +10 µA

=25°C (see Fig.5)

amb

maximum clock frequency 20 −−MHz
clock pulse width HIGH 20 −−ns
clock pulse width LOW 20 −−ns
clock rise time − 4 − ns
clock fall time − 4 − ns
input data set-up time 11 −−ns
input data hold time 0 −−ns

ANALOG OUTPUTS; note 3
V

o(p-p)

output voltage

full-scale 0.9 1 1.1 V

(peak-to-peak value)

Z

oL

output load impedance see Fig.6 − 15 − pF

=25°C

amb

−− 100 µs

−− 100 µs

= 16.384 MHz;

−50 −55 − dB

= 8.192 MHz;

=25°C; both DACs

=25°C0−0.8 V
=25°C 2.0 − V

CCD2

=25°C0−0.8 V
=25°C 2.0 − V

CCD2

− 0.3 − kΩ

V

V

1999 Sep 16 9

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

T

RANSFER FUNCTION

INLD integral non linearity ramp input;

f

=20MHz

CLK

DNLD differential non linearity ramp input;

f

=20MHz

CLK

t

st

settling time 10% to 90% full-scale;

T

=25°C

amb

10% to 90% for 10%
full-scale; T

MATCHING BETWEEN CHANNEL I AND Q

∆V amplitude matching f

∆ϕ phase matching f

= 4.43 MHz;

o

f

= 20 MHz;

CLK

T

=25°C

amb

= 4.43 MHz;

o

f

= 20 MHz;

CLK

T

=25°C

amb

DYNAMIC RANGE; note 1
NF noise floor f

= 4.43 MHz;

o

f

=20MHz

CLK

SPURIOUS FREE DYNAMIC RANGE
SFDR spurious free dynamic

range

STANDBY MODE OUTPUT DELAY; STDBYD; T
t

d(stb)LH

standby delay

fo= 4.43 MHz;
f

=20MHz

CLK

=25°C

amb

(LOW-to-HIGH transition)

t

d(stb)HL

start-up delay
(HIGH-to-LOW transition)

CROSSTALK ON THE DAC

α

ct

crosstalk on the DAC f

CLK(DAC)

f

CLK(ADC)

T

amb

= 16.384 MHz;
= 8.192 MHz;

=25°C; one DAC
switching between input
codes 0 and 1023 the
other DAC set at the
middle code; both ADCs
1 V (p-p) sine wave at
4 MHz; incoherent

amb

=25°C

−±0.4 ±1.25 LSB

−±0.35 ±1.5 LSB

− 8.0 − ns

− 7 − ns

− 0.2 6 %

−− 2 deg

−56 −61 − dB

− 55 − dB

−− 100 µs

−− 100 µs

−60 −75 − dB

Notes

1. The noisefloor is the maximum value ofthe output spectrum without taking into account fundamentaland harmonics
of the input signal up to the 6th harmonic.

2. Harmonics are obtained via a Fast Fourier Transformer (FFT) treatment taking 8k acquisition points per period.

3. It is recommended that the DAC output voltage is AC coupled in order to achieve optimum performance.

1999 Sep 16 10

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

Table 1 Output coding and input voltage (typical value, with respect to AGND)

V

− V

i

STEP

underflow <−0.75 0000000000

0 −0.75 0000000000

... ... ... ... ... ... ... ... ... ... ... ...

512 0 1000000000

... ... ... ... ... ... ... ... ... ... ... ...

1023 0.75 1111111110

overflow >0.75 1111111111

Table 2 Input coding and output voltage (typical value, with respect to DGND)

STEP

D9D D8D D7D D6D D5D D4D D3D D2D D1D D0D

0 0000000000 −0.5

... ... ... ... ... ... ... ... ... ... ... ...

512 1000000000 0

... ... ... ... ... ... ... ... ... ... ... ...

1023 1111111110 0.5

(V)

512

D9A D8A D7A D6A D5A D4A D3A D2A D1A D0A

BINARY INPUT BITS

BINARY OUTPUT BITS

V

− V

o

512

(V)

Table 3 Mode selection

OE D0ATO D9A

1 high impedance
0 active; binary

Table 4 Standby selection (ADC part)

STDBYA D0 TO D9 I

1 − 5mA
0 ADC active 64 mA

Table 5 Standby selection (DAC part)

STDBYD OUTI AND OUTQ I

1 − 5mA
0 DAC active 38 mA

CCA+ICCD

CCA+ICCD

(typ.)

(typ.)

1999 Sep 16 11

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

I

n − 2

Q

n − 2

t

CH

n

I

n − 1

Q

Q

n − 2

I

n − 2

Q

n − 2

handbook, full pagewidth

CLKA

I CHANNEL

ADC OUTPUT

Q CHANNEL

ADC OUTPUT

Q CHANNEL

LATCHED DATA

MULTIPLEXED

OUTPUTS

n − 1

t

TDA8779H

t

CL

1.4 V

I

n

Q

n

Q

n − 1

I

n − 1

ds

Q

n − 1

Q

n

I

n

t

d

t

I

n + 1

Q

n + 1

Q

n + 1

HIGH

Q

n

h

I

n + 1

LOW

ViI or V

iQ

sample N

MGG078

Fig.3 Timing diagram for the ADC.

1999 Sep 16 12

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

OE

output

data

output

data

V

CCO

t

dLZ

LOW

10%

high−Z

t

dZL

50%

t

dHZ

HIGH

handbook, full pagewidth

90%

high−Z

TDA8779

1.4 V

t

dZH

50%

3.3 kΩ

HIGH

LOW

TDA8779H

S1

V

CCO

fOE= 100 kHz.

Fig.4 Timing diagram and test conditions of the 3-state output delay time.

Table 6 Test conditions for Fig.4

TEST SWITCH S1

t

dLZ

t

dZL

t

dHZ

t

dZH

V

CCO

V

CCO

OGND
OGND

OE

15 pF

MGG077

1999 Sep 16 13

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

handbook, full pagewidth

CLKD

MULTIPLEXED

INPUTS

I CHANNEL

LATCHED DATA

I CHANNEL

DAC OUTPUT

Q CHANNEL

DAC OUTPUT

t

h

n

t

s

I

n

I

n

I

n − 1

Q

n − 1

t

CH

Q

n

I

n + 1

I

I

Q

n + 1

n

n

Q

n + 1

I

n + 2

Q

I

I

n + 1

n + 1

t

CL

n + 2

Q

n + 2

TDA8779H

1.4 V

I

n + 3

I

n + 3

I

n + 2

Q

n + 2

MGG079

HIGH

LOW

HIGH

LOW

Fig.5 DACs multiplexed inputs timing diagram.

Fig.5 DACs multiplexed inputs timing diagram.

handbook, halfpage

TDA8779

1 µF

I, Q9,11

300 Ω

15 pF

MGG076

Fig.6 Equivalent DACs output load.

1999 Sep 16 14

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

APPLICATION INFORMATION

handbook, full pagewidth

100 nF

100 nF

INI

INQ

V

CCA1

INPUT

BIAS

4

6

100

nF

DEC1

7

23

REFERENCE
REGULATOR

10-BIT

10-BIT

10
nF

DEC2 DEC3

10

ADC

10

ADC

47

V

nF

5

LATCHES

CCD1

31

DGND1

28

TDA8779

10 10

MUX

BUFFER

STDBYA

29

TDA8779H

32

OE

34-43

44

D0A to D9A

V

CCO

15
pF

15
pF

AGND1

1 µF

300 Ω

1 µF

300 Ω

AGND2

OUTI

OUTQ

30

1

BUFFER

9

BUFFER

11

13

8

V

CCA2

10-BIT

DAC

10-BIT

DAC

REFERENCE
REGULATOR

10

DEC5

DEC4

10 nF 22 nF

LATCHES

10

10 10

BUFFER

10

12

V

CCD2

14

25

DGND2

STDBYD

15-24

27

26

33

CLKA
CLKD

OGND

D0D to D9D

MBH581

Fig.7 Application diagram.

1999 Sep 16 15

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

22

Z

E

TDA8779H

SOT307-2

e

w M

b

p

pin 1 index

44

1

w M

b

0.25

p

D

H

D

cE

p

0.40

0.25

0.20

0.14

D

10.1

9.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

12

11

Z

D

B

v M

0 2.5 5 mm

scale

(1)

(1) (1)(1)

eH

H

10.1

9.9

12.9

0.8 1.3

12.3

v M

D

H

E

A

B

E

12.9

12.3

E

LL

0.95

0.55

A

p

A

2

A

1

detail X

Z

D

0.15 0.10.15

1.2

0.8

(A )

L

p

L

Zywv θ

E

1.2

0.8

3

θ

o

10

o

0

OUTLINE
VERSION

SOT307-2

IEC JEDEC EIAJ

REFERENCES

1999 Sep 16 16

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesavery brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wavesoldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing,stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

TDA8779H

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Sep 16 17

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

HLQFP, HSQFP, HSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SQFP not suitable suitable
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)

(5)

SOLDERING METHOD

(1)

suitable

suitable

suitable

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Sep 16 18

Philips Semiconductors Product specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

NOTES

TDA8779H

1999 Sep 16 19

Philips Semiconductors – a w orldwide compan y

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252042 KIEV, Tel. [phone], Fax. [phone]

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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545004/25/04/pp20 Date of release: 1999 Sep 16 Document order number: 9397 750 06124