Datasheet TDA8779 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8779

10-bit converter interface
(ADC/DAC) for quadrature
transceiver

Objective specification
Supersedes data of 1996 Sep 05
File under Integrated Circuits, IC02

1996 Sep 18

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for

TDA8779

quadrature transceiver

FEATURES

• Two 10-bit ADCs with multiplexed outputs

• Two 10-bit DACs with multiplexed inputs

• Sampling rate for the ADCs and DACs up to 20 MHz

• Digital outputs (for the ADC) and inputs (for the DAC)

are TTL/CMOS compatible (2.7 to 5.5 V)

• Internal reference voltage regulator

• Power dissipation 520 mW

• Standby mode.

APPLICATIONS

Wireless communication.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA1

analog supply voltage for the
ADC part

V

CCD1

digital supply voltage for the
ADC part

V

CCA2

analog supply voltage for the
DAC part

V

CCD2

digital supply voltage for the
DAC part

V

CCO

I

CCA

I

CCD

I

CCO

f

CLK(ADC)max

output stage supply voltage 2.7 3.0 5.5 V
analog supply current − 71 − mA
digital supply current − 31 − mA
output stage supply current ramp input; f
maximum clock frequency for

the ADC part

INLA integral non linearity for the

ADC part

DNLA differential non linearity for

the ADC part

f

CLK(DAC)max

maximum clock frequency for

full-scale; ramp input;
f

=20MHz

CLK

50% full-scale; ramp input;

=20MHz

f

CLK

the DAC part

INLD integral non linearity for the

DAC part

DNLD differential non linearity for

the DAC part

P

tot

total power dissipation − 520 − mW

full-scale; ramp input;

=20MHz

f

CLK

full-scale; ramp input;

=20MHz

f

CLK

GENERAL DESCRIPTION

The TDA8779 contains two 10-bit high speed ADCs and
two 10-bit DACs for wireless communication (for use in
transceiver modules). This device converts two analog
input signals (channels I and Q) and digital inputs
(D0 to D9) at a maximum sampling rate of 20 MHz.
The input bias voltages for the analog input voltages are
provided internally at the middle code. The analog input
and output voltages are AC coupled.

The data sampling is performed on the rising edge of the
clock for ADCs and DACs.

All reference voltages are generated internally.

4.75 5.0 5.5 V

4.75 5.0 5.5 V

4.75 5.0 5.5 V

4.75 5.0 5.5 V

=20MHz − 2 − mA

CLK

20 −−MHz

−±2−LSB

−±0.3 − LSB

20 −−MHz

−±2−LSB

−±0.75 − LSB

1996 Sep 18 2

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

ORDERING INFORMATION

TYPE

NUMBER

TDA8779H QFP44

BLOCK DIAGRAM

handbook, full pagewidth

NAME DESCRIPTION VERSION

plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm

INI

INQ

4

6

V

CCA1

INPUT

BIAS

7

DEC2 DEC3

DEC1

23

REFERENCE
REGULATOR

10-BIT

ADC

10-BIT

ADC

10

10

5

LATCHES

PACKAGE

V

CCD1

31

DGND1

28

TDA8779

10 10

MUX

BUFFER

STDBYA

29

32

34-43

44

TDA8779

SOT307-2

OE

D0A to D9A

V

CCO

AGND1

OUTI

OUTQ

AGND2

30

1

BUFFER

9

BUFFER

11

13

8

V

CCA2

10-BIT

DAC

10-BIT

DAC

REFERENCE
REGULATOR

10

DEC5

DEC4

12

10

10

LATCHES

V

14

CCD2

10 10

BUFFER

25

DGND2

15-24

27

STDBYD

26

33

CLKA
CLKD

OGND

D0D to D9D

MGG075

Fig.1 Block diagram.

1996 Sep 18 3

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

PINNING

SYMBOL PIN DESCRIPTION

AGND1 1 analog ground 1
DEC1 2 decoupling input 1
DEC2 3 decoupling input 2
INI 4 I channel ADC input
DEC3 5 decoupling input 3
INQ 6 Q channel ADC input
V

CCA1

V

CCA2

OUTI 9 I channel DAC analog output
DEC4 10 decoupling input 4
OUTQ 11 Q channel DAC analog output
DEC5 12 decoupling input 5
AGND2 13 analog ground 2
V

CCD2

D0D 15 multiplexed input for the DACs; bit 0
D1D 16 multiplexed input for the DACs; bit 1
D2D 17 multiplexed input for the DACs; bit 2
D3D 18 multiplexed input for the DACs; bit 3
D4D 19 multiplexed input for the DACs; bit 4
D5D 20 multiplexed input for the DACs; bit 5
D6D 21 multiplexed input for the DACs; bit 6
D7D 22 multiplexed input for the DACs; bit 7
D8D 23 multiplexed input for the DACs; bit 8

7 analog supply voltage 1 for ADC part

(+5 V)

8 analog supply voltage 2 for DAC part

(+5 V)

14 digital supply voltage 2 for DAC part

(+5 V)

TDA8779

SYMBOL PIN DESCRIPTION

D9D 24 multiplexed input for the DACs; bit 9
DGND2 25 digital ground 2
CLKD 26 transmission block clock
STDBYD 27 power standby for the DAC part

(active HIGH)
DGND1 28 digital ground 1
STDBYA 29 power standby for the ADC part

(active HIGH)
CLKA 30 reception block clock
V

CCD1

OE 32 ADCs digital output enable

OGND 33 input/output ground
D0A 34 I and Q digital outputs; bit 0
D1A 35 I and Q digital outputs; bit 1
D2A 36 I and Q digital outputs; bit 2
D3A 37 I and Q digital outputs; bit 3
D4A 38 I and Q digital outputs; bit 4
D5A 39 I and Q digital outputs; bit 5
D6A 40 I and Q digital outputs; bit 6
D7A 41 I and Q digital outputs; bit 7
D8A 42 I and Q digital outputs; bit 8
D9A 43 I and Q digital outputs; bit 9
V

CCO

31 digital supply voltage 1 for ADC part

(+5 V)

(3-state output); (active LOW)

44 output supply voltage (2.7 to 5.5 V)

1996 Sep 18 4

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

handbook, full pagewidth

AGND1

DEC1
DEC2

INI

DEC3

INQ

V

CCA1

V

CCA2

OUTI

DEC4

OUTQ

1
2
3
4
5
6
7
8

9
10
11

CCO

V
44

D9A
43

D8A
42

D7A

D6A

41

40

TDA8779H

D5A
39

D4A
38

D3A
37

D2A
36

D1A
35

D0A
34

33
32
31
30
29
28
27
26
25
24
23

OGND
OE
V

CCD1

CLKA
STDBYA
DGND1
STDBYD
CLKD
DGND2
D9D
D8D

TDA8779

12

13

14

15

16

D0D

CCD2

D1D

DEC5

V

AGND2

Fig.2 Pin configuration.

17

D2D

18

D3D

19

D4D

20

D5D

21

D6D

22

D7D

MGG074

1996 Sep 18 5

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for

TDA8779

quadrature transceiver

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA1

V

CCA2

V

CCD1

V

CCD2

V

CCO

∆V

I

o

V

i

V

clk(p-p)

T

stg

T

amb

T

j

CC

analog supply voltage for ADC part −0.3 +7.0 V
analog supply voltage for DAC part −0.3 +7.0 V
digital supply voltage for ADC part −0.3 +7.0 V
digital supply voltage for DAC part −0.3 +7.0 V
output stage supply voltage −0.3 +7.0 V
voltage difference between:

V
V
V

CCA
CCA
CCD

− V

− V

− V

CCD
CCO
CCO

−1.0 +1.0 V

−1.0 +4.0 V

−1.0 +4.0 V

output current − 10 mA
input voltage referenced to AGND −0.3 +7.0 V
AC input switching voltage (peak-to-peak value) referenced to DGND − V

CCD

storage temperature −55 +150 °C
operating ambient temperature −20 +75 °C
junction temperature − 150 °C

V

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 75 K/W

CHARACTERISTICS

V

CCA=V7

V

CCO=V44

T

amb

and V8 to V1and V13= 4.75 to 5.5 V; V

CCD=V31

and V14 to V28and V25= 4.75 to 5.5 V;

to V33= 2.7 to 5.5 ; AGND1, AGND2, OGND, DGND1 and DGND2 are shorted together;

= −20 to +70 °C; measured typically at V

CCA=VCCD

= 5 V and V

=3V; CL= 15 pF; T

CCO

=25°C; unless

amb

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
V
V
V
V
∆V

I

CCA

I

CCD

CCA1
CCD1
CCA2
CCD2
CCO

CC

analog supply voltage for ADC part 4.75 5.0 5.5 V
digital supply voltage for ADC part 4.75 5.0 5.5 V
analog supply voltage for DAC part 4.75 5.0 5.5 V
digital supply voltage for DAC part 4.75 5.0 5.5 V
output stage supply voltage 2.7 3.0 5.5 V
voltage difference between

V
V
V

CCA
CCA
CCD

− V

− V

− V

CCD
CCO

CCO

−0.2 − +0.2 V

−0.2 − +2.5 V

−0.2 − +2.5 V

analog supply current − 71 − mA
digital supply current − 31 − mA

1996 Sep 18 6

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for

TDA8779

quadrature transceiver

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

CCO

I

CCA1(stb)

I

CCA2(stb)

ADC PART

LOCK INPUT

C
V

IL

V

IH

I

IL

I

IH

DIGITAL INPUTS: PINS OE AND STDBYA
V

IL

V

IH

I

IL

I

IH

ANALOG INPUTS
I

IL

I

IH

V

i(p-p)

V

i(p-p)over

Z

I

C

I

DIGITAL OUTPUTS: D0A TO D9A
V

OL

V

OH

I

oZ

SWITCHING CHARACTERISTICS (see Fig.3)
f

CLKmax

t

CH

t

CL

t

r

t

f

output stage supply current ramp input; f

=20MHz − 2 − mA

CLK

analog standby current for ADC part − 5 − mA
analog standby current for DAC part − 5 − mA

LOW level input voltage 0 − 0.6 V
HIGH level input voltage 2.2 − V

CCD1

V
LOW level input current −10 − +10 µA
HIGH level input current −10 − +10 µA

LOW level input voltage 0 − 0.6 V
HIGH level input voltage 2.2 − V

CCD1

V
LOW level input current −10+1µA
HIGH level input current −−1µA

LOW level input current for code 0 − tbf −µA
HIGH level input current for code 1023 − tbf −µA
analog input voltage

full-scale tbf 1.5 tbf V

(peak-to-peak value)
maximum analog input over voltage

overvoltage −−4.5 V

(peak-to-peak value)
input impedance − 10 − kΩ
input capacitance − 3 − pF

LOW level output voltage Io= 1 mA 0 − 0.5 V
HIGH level output voltage Io= −1mA V
output current in 3-state mode 0.5 V < Vo<V

− 0.5 V −20 − +20 µA

CCO

− 0.5 − V

CCO

CCO

V

maximum clock frequency 20 −−MHz
clock pulse width HIGH 20 −−ns
clock pulse width LOW 20 −−ns
clock rise time − 4 − ns
clock fall time − 4 − ns

1996 Sep 18 7

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for

TDA8779

quadrature transceiver

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ANALOG SIGNAL PROCESSING

Linearity

INLA integral non linearity ramp input; f
DNLA differential non linearity full-scale; ramp input;

=20MHz

f

CLK

50% full-scale; ramp input;

=20MHz

f

CLK

Noise floor;

NF noise floor f

Harmonics;

THD total harmonic distortion f

note 2

note 3

= 5.1 MHz; 20 Msps −−60 − dB

in

= 5.1 MHz; 20 Msps −−54 − dB

i

Spurious free dynamic range

SFDR spurious free dynamic range fi= 5.1 MHz; 20 Msps 45 56 − dB

Matching between the I and Q channels

∆V amplitude matching fin= 5.1 MHz;

f

= 20 MHz;

CLK

T

=25°C

amb

∆ϕ phase matching f

= 5.1 MHz;

in

f

= 20 MHz;

CLK

T

=25°C

amb

Bandwidth

B bandwidth maximum attenuation of

−0.3 dB

full-scale sine wave;
T

=25°C;

amb

50% full-scale sine wave;

=25°C;

T

amb

TIMING:(THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME td); CL= 15 pF; see Fig.3
t

ds

t

h

t

d

sampling delay time −−5ns
output hold time 5 −−ns
output delay time V

= 4.75 V − 12 15 ns

CCO

= 3.15 V − 17 20 ns

V

CCO

= 2.7 V − 21 24 ns

V

CCO

3-STATE OUTPUT DELAY TIMES; see Fig.4
t

dZH

t

dZL

t

dHZ

t

dLZ

output delay enable HIGH − 14 18 ns
output delay enable LOW − 16 20 ns
output delay disable HIGH − 16 20 ns
output delay disable LOW − 14 18 ns

=20MHz −±2−LSB

CLK

−±0.5 − LSB

−±0.3 − LSB

−−6%

−−2 Deg

5.5 −−MHz

tbf −−MHz

1996 Sep 18 8

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for

TDA8779

quadrature transceiver

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

STANDBY MODE OUTPUT DELAY TIMES; STDBYA
t

d(stb)LH

t

d(stb)HL

CROSSTALK ON THE ADC

α

ct

DAC PART

D

IGITAL INPUTS: D0D TO D9D AND CLKD

V

IL

V

IH

I

IL

I

IH

DIGITAL INPUT; STDBYD
V

IL

V

IH

I

IL

I

IH

TIMING: see Fig.5
f

CLK(max)

t

CH

t

CL

t

r

t

f

t

s

t

h

ANALOG OUTPUTS; note 1
V

o(p-p)

Z

oL

RANSFER FUNCTION

T
INLD integral non linearity ramp input; f

DNLD differential non linearity ramp input; f
B maximum bandwidth full scale; T

standby (LOW-to-HIGH transition) −−100 µs
start-up (HIGH-to-LOW transition) −−100 µs

crosstalk into the ADC f

CLK(DAC)

f

CLK(ADC)

T

amb

= 16.384 MHz;
= 8.192 MHz;

=25°C; both DACs

−−−55 dB

switching between input
codes 0 and 1023; one
ADC 1 V (p-p) sine wave at
4 MHz and the other ADC
set at the middle code

LOW level input voltage 0 − 0.6 V
HIGH level input voltage 2.2 − V

CCD2

V
LOW level input current −200 −120 0 µA
HIGH level input current −10 − +10 µA

LOW level input voltage 0 − 0.6 V
HIGH level input voltage 2.2 − V

CCD2

V
LOW level input current −10+1µA
HIGH level input current −−1µA

maximum clock frequency 20 −−MHz
clock pulse width HIGH 20 −−ns
clock pulse width LOW 20 −−ns
clock rise time − 4 − ns
clock fall time − 4 − ns
input data set-up time 10 tbf − ns
input data hold time 0 tbf − ns

output voltage (peak-to-peak value) full-scale tbf 1 tbf V
output load impedance see Fig.6 − 15 − pF

− 0.3 − kΩ

=20MHz −±3−LSB

CLK

= 20 MHz; −±0.75 − LSB

CLK

=25°C 5.5 −−MHz

amb

1996 Sep 18 9

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for

TDA8779

quadrature transceiver

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Matching between channel I and Q
∆V amplitude matching fo= 5.1 MHz;

f

= 20 MHz;

CLK

T

=25°C

amb

∆ϕ phase matching f

DYNAMIC RANGE; note 2

NF noise floor f

= 5.1 MHz;

o

f

= 20 MHz;

CLK

T

=25°C

amb

= 5.1 MHz;

o

f

=20MHz

CLK

SPURIOUS FREE DYNAMIC RANGE
SFDR spurious free dynamic range fo= 5.1 MHz;

f

=20MHz

CLK

STANDBY MODE OUTPUT DELAY; STDBYD
t

d(stb)LH

t

d(stb)HL

standby (LOW-to-HIGH transition) −−100 µs
start-up (HIGH-to-LOW transition) −−100 µs

CROSSTALK ON THE DAC

α

ct

crosstalk into the DAC f

CLK(DAC)

f

CLK(ADC)

T

amb

= 16.384 MHz;
= 8.192 MHz;

=25°C; one DAC
switching between input
codes 0 and 1023 the other
DAC set at the middle
code; both ADCs 1 V (p-p)
sine wave at 4 MHz;
incoherent

−−6%

−−2 Deg

−−60 − dB

− 50 − dB

−−−55 dB

Notes

1. It is recommended that the DAC output voltage is AC coupled in order to achieve optimum performance.

2. The noise floor is the maximum value of the output spectrum without taking into account fundamental and harmonics
of the input signal.

3. Harmonics are obtained via a Fast Fourier Transformer (FFT) treatment taking 8K acquisition points per period.

1996 Sep 18 10

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for

TDA8779

quadrature transceiver

Table 1 Output coding and input voltage (typical value, referenced to AGND)

Vi− V

STEP

underflow <−0.75 0000000000

0 −0.75 0000000000

... ... ... ... ... ... ... ... ... ... ... ...

512 0 1000000000

... ... ... ... ... ... ... ... ... ... ... ...

1023 0.75 1111111110

overflow >0.75 1111111111

Table 2 Input coding and output voltage (typical value, referenced to DGND)

STEP

D9D D8D D7D D6D D5D D4D D3D D2D D1D D0D

0 0000000000 −0.5

... ... ... ... ... ... ... ... ... ... ... ...

5121000000000 0

... ... ... ... ... ... ... ... ... ... ... ...

1023 1111111110 0.5

(V)

512

D9A D8A D7A D6A D5A D4A D3A D2A D1A D0A

BINARY INPUT BITS

BINARY OUTPUT BITS

− V

V

o

512

(V)

Table 3 Mode selection

OE D0A TO D9A

1 high impedance
0 active; binary

Table 4 Standby selection

STDBYA D0 TO D9 I

1 − 5mA
0 active 64 mA

Table 5 Standby selection

STDBYD OUTI AND OUTQ I

1 − 5mA
0 active 38 mA

CCA+ICCD

CCA+ICCD

(typ.)

(typ.)

1996 Sep 18 11

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

I

n − 2

Q

n − 2

t

CH

Q

I

n − 2

n − 2

Q

n − 2

n

I

n − 1

Q

handbook, full pagewidth

CLKA

I CHANNEL

ADC OUTPUT

Q CHANNEL

ADC OUTPUT

Q CHANNEL

LATCHED DATA

MULTIPLEXED

OUTPUTS

n − 1

Q

I

n − 1

n − 1

TDA8779

t

CL

50%

Q

n − 1

I

n

Q

n

Q

n

I

n

I

n + 1

Q

n + 1

Q

n + 1

Q

n

I

n + 1

ViI or V

t

d

t

ds

iQ

sample N

t

h

MGG078

Fig.3 Timing diagram for the ADC.

1996 Sep 18 12

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

OE

output

data

output

data

V

CCD

t

dLZ

LOW

10%

HIGH

t

dZL

50%

t

dHZ

HIGH

handbook, full pagewidth

90%

LOW

TDA8779

OE

50%

t

dZH

50%

3.3 kΩ

10 pF

S1

TDA8779

V

CCD

MGG077

tOE= 100kHz.

Fig.4 Timing diagram and test conditions of 3-state output delay time.

Table 6 Test conditions for Fig.4

TEST SWITCH S1

t

dLZ

t

dZL

t

dHZ

t

dZH

V

CCD

V

CCD

DGND
DGND

1996 Sep 18 13

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

handbook, full pagewidth

MULTIPLEXED

INPUTS

I CHANNEL

LATCHED DATA

I CHANNEL

DAC OUTPUT

Q CHANNEL

DAC OUTPUT

CLKD

t

h

n

t

s

I

n

I

n

I

n − 1

Q

n − 1

t

CH

Q

n

I

n + 1

I

n + 1

I

n

Q

TDA8779

t

CL

50%

I

Q

I

n + 2

n + 1

n + 1

Q

n + 2

I

n + 3

I

n + 3

I

n + 2

Q

n + 2

MGG079

Q

n + 1

n

I

n + 2

Fig.5 DACs multiplexed inputs timing diagram.

handbook, halfpage

TDA8779

1 µF

I, Q9,11

300 Ω

15 pF

MGG076

Fig.6 Equivalent DACs output load.

1996 Sep 18 14

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

APPLICATION INFORMATION

handbook, full pagewidth

100 nF

100 nF

INI

INQ

V

CCA1

INPUT

BIAS

4

6

100

nF

7

REFERENCE
REGULATOR

10-BIT

10-BIT

10
nF

DEC2 DEC3

DEC1

23

10

ADC

10

ADC

47

V

nF

5

LATCHES

CCD1

31

DGND1

28

TDA8779H

10 10

MUX

BUFFER

STDBYA

29

TDA8779

32

34-43

44

OE

D0A to D9A

V

CCO

15
pF

15
pF

AGND1

1 µF

300 Ω

1 µF

300 Ω

AGND2

OUTI

OUTQ

30

1

BUFFER

9

BUFFER

11

13

8

V

CCA2

10-BIT

DAC

10-BIT

DAC

REFERENCE
REGULATOR

10

DEC4

10 nF 22 nF

10

10

12
DEC5

LATCHES

V

14

CCD2

10 10

BUFFER

25

DGND2

15-24

27

STDBYD

26

33

CLKA

CLKD

OGND

D0D to D9D

MBH581

Fig.7 Application diagram.

1996 Sep 18 15

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

22

Z

E

TDA8779

SOT307-2

e

w M

b

p

pin 1 index

44

1

w M

b

0.25

p

D

H

D

cE

p

0.40

0.25

0.20

0.14

D

10.1

9.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

12

11

Z

D

B

v M

0 2.5 5 mm

scale

(1)

(1) (1)(1)

eH

H

10.1

9.9

12.9

0.8 1.3

12.3

v M

D

H

E

E

A

B

LLpQZywv θ

E

12.9

12.3

0.95

0.55

A

2

A

A

1

detail X

0.85

0.75

0.15 0.10.15

Q

(A )

3

θ

L

p

L

Z

E

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1.2

0.8

1.2

0.8

o

10

o

0

OUTLINE
VERSION

SOT307-2

IEC JEDEC EIAJ

REFERENCES

1996 Sep 18 16

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17
95-02-04

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

TDA8779

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Sep 18 17

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for

TDA8779

quadrature transceiver

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Sep 18 18

Philips Semiconductors Objective specification

10-bit converter interface (ADC/DAC) for
quadrature transceiver

NOTES

TDA8779

1996 Sep 18 19

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Czech Republic: see Austria
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Hungary: seeAustria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

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Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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Spain: Balmes 22, 08007 BARCELONA,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1996 SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 537021/1200/02/pp20 Date of release: 1996 Sep 18 Document order number: 9397 750 01181