Datasheet tda8768 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8768

12-bit high-speed Analog-to-Digital
Converter (ADC)

Preliminary specification
Supersedes data of 1998 Feb 25
File under Integrated Circuits, IC02

1998 Aug 26

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

FEATURES

• 12-bit resolution

• Sampling rate up to 55 MHz

•−3 dB bandwidth of 190 MHz

• 5 V power supplies

• Binary or twos-complement CMOS outputs

• In-range CMOS-compatible output

• TLL-CMOS compatible static digital inputs

• 3 to 5 V CMOS-compatible digital outputs

• Differential clock input; Positive Emitter Coupled Logic

(PECL)-compatible

• Power dissipation 325 mW (typical)

• Low analog input capacitance (typical 2 pF), no buffer

amplifier required

• Integrated sample-and-hold amplifier

• Differential analog input

• External amplitude range control

• Voltage controlled regulator included.

TDA8768

APPLICATIONS

• High-speed analog-to-digital conversion for
– Video signal digitizing
– High Definition TV (HDTV)
– Imaging (camera scanner)
– Medical imaging
– Telecommunication
– Base-station receiver.

GENERAL DESCRIPTION

The TDA8768 is a bipolar 12-bit Analog-to-Digital
Converter (ADC) optimized for telecommunications and
professional imaging. It converts the analog input signal
into 12-bit binary coded digital words at a maximum
sampling rate of 55 MHz. All static digital inputs (SH,
and OTC) are TTL and CMOS compatible and all outputs
are CMOS compatible. A sine wave clock input signal can
also be used.

CE

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

INL integral non-linearity f
DNL differential non-linearity f
f

CLK(max)

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output supply voltage 3.0 3.3 5.25 V
analog supply current − 33 tbf mA
digital supply current − 30 tbf mA
output supply current f

= 4 MHz; fi= 400 kHz − 3.2 tbf mA

CLK

= 4 MHz; fi= 400 kHz −±2.0 ±4.5 LSB

CLK

= 4 MHz; fi= 400 kHz −±0.6 ±1.0 LSB

CLK

maximum clock frequency

TDA8768H/4 40 −−MHz
TDA8768H/5 55 −−MHz

P

tot

total power dissipation − 325 tbf mW

ORDERING INFORMATION

TYPE

NUMBER

TDA8768H/4
TDA8768H/5 55

NAME DESCRIPTION VERSION

QFP44

plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10 × 10 × 1.75 mm

PACKAGE

SOT307-2

SAMPLING

FREQUENCY (MHz)

40

1998 Aug 26 2

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

BLOCK DIAGRAM

V

V

V

handbook, full pagewidth

n.c.

V

ref

V
V

SH

V

CCA1

2

1, 5 to 8, 12 to 14, 16

11

43

I

42

I

sample-

and-hold

39

AMP

CCA2

CCA3

3

9

TDA8768

ANALOG-TO-DIGITAL

CCA4

41

CONVERTER

CLK

35

36

V

CCD1

LATCHES

CLK

CLOCK DRIVER

TDA8768

V

CCD2

15

37

OUTPUTS

18

CMOS

CEOTC

19

D11

21

28
29

32

33

D1022
D923
D824
D725
D626
D527
D4
D3
D230
D131
D0

MSB

data outputs

LSB

V

CCO

44

AGND1

10

AGND2

4

AGND3

40

AGND4

DGND1

Fig.1 Block diagram.

OVERFLOW/

UNDERFLOW

LATCH

38

17

DGND2

CMOS

OUTPUT

OGND

20

34

IR

MGR470

1998 Aug 26 3

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
V

CCA1

V

CCA3

AGND3 4 analog ground 3
n.c. 5 not connected
n.c. 6 not connected
n.c. 7 not connected
n.c. 8 not connected
V

CCA2

AGND2 10 analog ground 2
V

ref

n.c. 12 not connected
n.c. 13 not connected
n.c. 14 not connected
V

CCD2

n.c. 16 not connected
DGND2 17 digital ground 2
OTC 18 control input twos complement

CE 19 chip enable input

IR 20 in-range output
D11 21 data output; bit 11 (MSB)
D10 22 data output; bit 10

2 analog supply voltage 1 (+5 V)
3 analog supply voltage 3 (+5 V)

9 analog supply voltage 2 (+5 V)

11 reference voltage input

15 digital supply voltage 2 (+5 V)

output; active HIGH

(CMOS level; active LOW)

TDA8768

SYMBOL PIN DESCRIPTION

D9 23 data output; bit 9
D8 24 data output; bit 8
D7 25 data output; bit 7
D6 26 data output; bit 6
D5 27 data output; bit 5
D4 28 data output; bit 4
D3 29 data output; bit 3
D2 30 data output; bit 2
D1 31 data output; bit 1
D0 32 data output; bit 0 (LSB)
V

CCO

OGND 34 output ground
CLK 35 complementary clock input; active

CLK 36 clock input
V

CCD1

DGND1 38 digital ground 1
SH 39 sample-and-hold enable input

AGND4 40 analog ground 4
V

CCA4

V

I

V

I

AGND1 44 analog ground 1

33 output supply voltage (3 to 5.25 V)

LOW

37 digital supply voltage 1 (+5 V)

(CMOS level; active HIGH)

41 analog supply voltage 4 (+5 V)
42 positive analog input voltage
43 negative analog input voltage

1998 Aug 26 4

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

I

VIV

AGND1
44

43

42

n.c.

1
V
V

AGND3

V

AGND2

CCA1
CCA3

n.c.
n.c.

n.c.
n.c.

CCA2

V

ref

2

3

4

5

6

7

8

9

10
11

CCA4

AGND4

V

41

40

TDA8768H

SH
39

DGND1

V

38

37

CCD1

CLK

36

CLK

35

OGND
34

TDA8768

V

33

CCO

D0

32
31

D1

30

D2
D3

29
28

D4
D5

27
26

D6
D7

25
24

D8
D9

23

12
n.c.

13

14

15

16

17

n.c.

n.c.

CCD2

V

n.c.

DGND2

Fig.2 Pin configuration.

18

OTC

19
CE

20

21

22

IR

D11

D10

MGR469

1998 Aug 26 5

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8768

Converter (ADC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V
∆V

V
V

I

O

T
T
T

CCA
CCD
CCO

CC

I
i(p-p)

stg
amb
j

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output supply voltage note 1 −0.3 +7.0 V
supply voltage difference

− V

V
V
V

CCA
CCD
CCA

− V

− V

CCD
CCO
CCO

input voltage at pins 42 and 43 referenced to AGND 0.3 V
input voltage at pins 35 and 36 for

−1.0 +1.0 V

−1.0 +4.0 V

−1.0 +4.0 V

CCA

− V

CCD

differential clock drive (peak-to-peak
value)

output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature −10 +85 °C
junction temperature − 150 °C

V
V

Note

1. The supply voltages V

CCA

, V

CCD

and V

may have any value between −0.3 V and +7.0 V provided that the supply

CCO

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITION VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 75 K/W

1998 Aug 26 6

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8768

Converter (ADC)

CHARACTERISTICS

V

CCA=V2

V

CCO=V33

V

CCA=VCCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Inputs

CLK
V

IL

V

IH

I

IL

I

IH

Z

i

C

i

∆V

OTC, SH AND CE (REFERENCED TO DGND); see Tables 1 and 2
V

IL

V

IH

I

IL

I

IH

V

AND V

I

I

IL

I

IH

R

i

C

i

V

I(CM)

to V44, V9to V10, V3to V4 and V41to V40= 4.75 to 5.25 V; V

to V34= 3.0 to 5.25 V; AGND and DGND shorted together; T

= 5 V and V

CCO

= 3.3 V, T

=25°C, V

amb

I(p-p)

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output supply voltage 3.0 3.3 5.25 V
analog supply current − 33 45 mA
digital supply current − 30 37 mA
output supply current f

AND CLK (REFERENCED TO DGND)

LOW-level input voltage V
HIGH-level input voltage V
LOW-level input current V
HIGH-level input current V
input impedance f
input capacitance f

CLK(p-p)

differential AC input voltage

= 4 MHz; fi= 400 kHz − 3.2 tbf mA

CLK

= 40 MHz; fi= 4.43 MHz − 11 tbf mA

f

CLK

= 5 V; note 1 3.19 − 3.52 V

CCD

= 5 V; note 1 3.83 − 4.12 V

CCD

or V

CLK

or V

CLK

= 40 MHz 2 −− kΩ

CLK

= 40 MHz −−2pF

CLK

DC voltage level = 2.5 V 0.5 − 2.0 V
(peak-to-peak value) for
switching (V

CLK

− V

CLK

)

LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2.0 − V
LOW-level input current VIL= 0.8 V −20 −− µA
HIGH-level input current VIH= 2.0 V −−+20 µA

(REFERENCED TO AGND); V

I

REF

=V

− 1.825 V; see Table 1

CCA

LOW-level input current − 10 −µA
HIGH-level input current − 10 −µA
input resistance fi= 4.43 MHz 100 −− kΩ
input capacitance fi= 4.43 MHz −−2pF
common mode input voltage VI= VI; output code 2047

V

CCA

V

CCA

V

CCA

CCD=V37

amb

− V

CLK
CLK

= 2.0 V and CL= 10 pF; unless otherwise specified.

I(p-p)

= 3.19 V −10 −− µA
= 3.83 V −−10 µA

to V38and V15to V17= 4.75 to 5.25 V;

= 0 to 70 °C; typical values measured at

CCD

= 5 V tbf 3.6 tbf V
= 4.75 V tbf 3.35 tbf V
= 5.25 V tbf 3.85 tbf V

V

1998 Aug 26 7

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8768

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Voltage controlled regulator input V

V

ref(FS)

I

ref

V

I(p-p)

− V

full-scale fixed voltage V
input current − 0.5 10 µA
input voltage amplitude

I(p-p)

(peak-to-peak value)

Outputs (referenced to OGND)

D

IGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND)

V

OL

V

OH

I

o

LOW-level output voltage IOL= 2 mA 0 − 0.5 V
HIGH-level output voltage IOH= −0.4 mA V
output current in 3-state output level between 0.5 V

Switching characteristics

LOCK FREQUENCY f

C
f

CLK(min)

f

CLK(max)

minimum clock frequency SH = HIGH −−2 MHz
maximum clock frequency

; see Fig.3

CLK

TDA8768H/4 40 −− MHz
TDA8768H/5 55 −− MHz

t

CLKH

t

CLKL

clock pulse width HIGH 8.5 −− ns
clock pulse width LOW 8.5 −− ns

Analog signal processing; 50% clock duty factor; V

(referenced to AGND); note 2

ref

=5V − 3.175 − V

CCA

V

ref=VCCA

and V

− 1.825 V − 2.0 − V

CCO

− VI= 2.0 V; V

I

− 0.5 − V

CCO

−20 − +20 µA

ref=VCCA

− 1.825 V; see Table 1

CCO

V

INEARITY

L
INL integral non-linearity f

DNL differential non-linearity f

= 4 MHz; fi= 400 kHz −±2.0 ±4.5 LSB

CLK

= 4 MHz; fi= 400 kHz;

CLK

−±0.6 ±1.0 LSB

no missing code

E

offset

offset error V

CCA=VCCD=VCCO

T

=25°C; VI= VI;

amb

=5V;

tbf −11 tbf mV

output code = 2047

E

G(FS)

BANDWIDTH (f

gain error amplitude
(full scale); spread from
device to device

= 55 MHz); note 3

CLK

V

CCA=VCCD=VCCO

T

=25°C;

amb

V

I(p-p)

− V

I(p-p)

= 2.0 V

=5V;

−5 − +5 %

B analog bandwidth −3 dB; full scale input tbf 190 − MHz
H

ARMONICS (f

h

fund(FS)

= 40 MHz)

CLK

fundamental harmonics

fi= 4.43 MHz −−0dB
(full scale)

h

tot(FS)

harmonics (full scale);

fi= 4.43 MHz
all components

second harmonic −−75 − dB
third harmonic −−70 − dB

THD total harmonic distortion f

= 4.43 MHz; note 4 −−66 − dB

i

1998 Aug 26 8

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8768

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

THERMAL NOISE
N

th(rms)

SPURIOUS FREE DYNAMIC RANGE
DR

sf

SIGNAL-TO-NOISE RATIO; note 5
S/N signal-to-noise ratio without harmonics;

EFFECTIVE NUMBER OF BITS; note 5
N

bit

INTERMODULATION; note 6
TTIR two-tone intermodulation

d

3

BIT ERROR RATE
BER bit error rate f

thermal noise (RMS value) grounded input;

f

= 40 MHz

CLK

− 0.25 tbf LSB

spurious free dynamic range fi= 4.43 MHz tbf 69 − dB

f

= 10 MHz tbf tbf − dB

i

f

= 20 MHz tbf tbf − dB

i

− 67 − dB

f

= 40 MHz; fi= 4.43 MHz

CLK

effective number of bits
TDA8768H/4 (f

= 40 MHz)

CLK

effective number of bits
TDA8768H/5 (f

= 55 MHz)

CLK

fi= 4.43 MHz − 10.3 − bits

f

=10MHz − tbf − bits

i

f

=15MHz − tbf − bits

i

fi= 4.43 MHz − 9.9 − bits

f

=10MHz − tbf − bits

i

f

=15MHz − tbf − bits

i

f

=20MHz − tbf − bits

i

f

= 40 MHz tbf 66 − dB

CLK

rejection
third order intermodulation

f

= 40 MHz tbf 67 − dB

CLK

distortion

= 40 MHz;

CLK

fi= 4.43 MHz;

− 10

−15

tbf times/

sample

VI= ±16 LSB at code 2047

Timing (C

t

d(s)

t

h

t

d

= 10 pF); see Fig.3 and note 7

L

sampling delay time −−2ns
output hold time 4 −− ns
output delay time V

= 5.25 V − 10 15 ns

CCO

V

= 3.0 V 13 18 ns

CCO

3-state output delay times; see Fig.4
t

dZH

t

dZL

t

dHZ

t

dLZ

enable HIGH − 14 18 ns
enable LOW − 16 20 ns
disable HIGH − 16 20 ns
disable LOW − 14 18 ns

1998 Aug 26 9

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8768

Converter (ADC)

Notes

1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:
a) PECL mode 1: (DC level varies 1 : 1 with V
b) PECL mode 2: (DC level varies 1 : 1 with V

edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF
capacitor.

c) PECL mode 3: (DC level varies 1 : 1 with V

edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF
capacitor.

d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (peak-to-peak

value) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.

2. It is possible with an external reference connected to pin V
referenced to V

CCA

. For V

− 1.825 V, the differential input voltage amplitude is 2 V (peak-to-peak value).

CCA

3. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
full-scale sine wave.

4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
THD 20 log

---------------------------------------------------------------------------------------------------------------=
(2nd)2(3rd)2(4th)2(5th)2(6th)

++++

F

where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.

5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all
harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:
SNR = N

× 6.02 + 1.76 dB.

bit

6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6dB
below full-scale for each input signal).
d3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation
product.

7. Output data acquisition: the output data is available after the maximum delay of td.

) CLK and CLK inputs are at differential PECL levels.

CCD

) CLK input is at PECL level and sampling is taken on the falling

CCD

) CLK input is at PECL level and sampling is taken on the rising

CCD

to adjust the ADC input range. This voltage has to be

ref

2

1998 Aug 26 10

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8768

Converter (ADC)

Table 1 Output coding with differential inputs (typical values to AGND); V

CODE V

Underflow <3.1 >4.1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

0 3.1 4.1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 00
1 −−1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1

↓−−↓ ↓ ↓

2047 3.6 3.6 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

↓−−↓ ↓ ↓

4094 −−1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0
4095 4.1 3.1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

Overflow >4.1 <3.1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

Table 2 Mode selection

OTC

I(p-p)

0 0 binary; active
1 0 twos complement; active

(1)

X

V

I(p-p)

IR

CE D0 TO D11 AND IR

1 high impedance

BINARY OUTPUTS

D11 TO D0 D11 TO D0

I(p-p)

− V

I(p-p)

= 2.0 V; V

TWOS COMPLEMENT

ref=VCCA

OUTPUTS

− 1.825 V

Note

1. X = don’t care.

Table 3 Sample-and-hold selection

SH SAMPLE-AND-HOLD

1 active
0 inactive; tracking mode

1998 Aug 26 11

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

t

CLKH

t

CLKL

t

ds

handbook, full pagewidth

CLK

V

I

DATA
D0 to D11

sample N

DATA

N − 2

sample N + 1

DATA
N − 1

TDA8768

HIGH
50 %
LOW

sample N + 2

t

h

DATA

N

t

d

DATA

N + 1

HIGH
50 %
LOW

MGR472

handbook, full pagewidth

fCE= 100kHz.

V

CE

output
data

output
data

CCD

0 V

LOW

Fig.3 Timing diagram.

HIGH

t

dZL

t

dLZ

10 %

TDA8768

CE

50 %

15 pF

HIGH

3.3 kΩ

t

dHZ

90 %

LOW

V

S1

CCD

50 %

t

dZH

50 %

TEST

t

dLZ

t

dZL

t

dHZ

t

dZH

S1

V

CCD

V

CCD

DGND
DGND

MBG856

Fig.4 Timing diagram and test conditions of 3-state output delay time.

1998 Aug 26 12

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

APPLICATION INFORMATION

handbook, full pagewidth

220 nF

input

100 Ω 100 Ω

4.7 µF

1 : 1

10
nF

R1

R2

V

CCA

5 V

(2)

100

nF

100

nF

5 V

100

nF

V

ref

TDA8768

5 V5 V SH

100 nF

V

I

V

I

n.c.

n.c.
n.c.
n.c.
n.c.

(3)

44 43 42 41 40 39 38 37 36 35 34

1
2

3
4
5
6
7
8
9
10
11

12

13 14 15 16 17 18 19 20 21 22

mode

TDA8768

100 nF

CLK

(1)

CLK

5 V

33
32
31
30
29
28
27
26
25
24
23

100 nF

D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9

n.c.

n.c. n.c.

n.c.
5 V

100

nF

The analog, digital and output supplies should be separated and decoupled.
(1) Single-ended clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain a middle voltage of 3.6 V; see common mode input voltage.

In addition, to ensure a sufficient analog input stability, the minimum current into these resistors must be approximately 1 mA.

must be decoupled to V

(3) V

ref

CCA

.

IR

D10

D11

(MSB)

chip select input
output format select

Fig.5 Application diagram.

MGR471

1998 Aug 26 13

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

R2

220 Ω

100 nF

270 Ω

(1)

TTL

input

If the clock lines are more than 1 inch long they must be matched. In fact, the 27 Ω resistor will be changed
by the series connection of R1 and R2, with R1 = Z

(1) 50 Ω matched line (Zo, L).

D
TRANSLATOR

270 Ω

o

R1

500 Ω

Z0 = 50 Ω

PECL

Z0 = 50 Ω

100 nF

placed close to pins CLK and CLK.

CLK

CLK

R1
500 Ω

R2
220 Ω

35

36

TDA8768

TDA8768

MGL474

Fig.6 Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator.

V

handbook, full pagewidth

(1)

TTL

input

The value of R1 and R2 must be chosen in order to meet the following relations:

V

R2×

CCD

3V

= Z0

---------------------------- ­R1 R2+

(1) 50 Ω matched line (Z

and

o

=

, L).

R1 R2×

---------------------­R1 R2+

CCD

D

TRANSLATOR

R1

82 Ω

PECL

R2

120 Ω

100 nF

R1
82 Ω

CLK

CLK

R2
120 Ω

35

36

TDA8768

MGL473

Fig.7 Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator

and Thevenin parallel terminations.

1998 Aug 26 14

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

22

Z

E

TDA8768

SOT307-2

e

w M

b

p

pin 1 index

44

1

w M

b

0.25

p

D

H

0.40

0.20

D

D

0.25

10.1

0.14

9.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

12

11

Z

D

B

v M

0 2.5 5 mm

scale

(1)

(1) (1)(1)

eH

H

10.1

9.9

12.9

0.8 1.3

12.3

v M

D

H

E

A

B

E

12.9

12.3

E

LL

0.95

0.55

A

p

A

2

A

1

detail X

Z

D

0.15 0.10.15

1.2

0.8

(A )

3

L

p

L

Zywv θ

E

1.2

0.8

θ

o

10

o

0

OUTLINE

VERSION

SOT307-2

IEC JEDEC EIAJ

REFERENCES

1998 Aug 26 15

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details,
refer to the Drypack information in the

IC26; Integrated Circuit Packages; Section: Packing
Methods”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

.

“Data Handbook

TDA8768

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Aug 26 16

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8768

Converter (ADC)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Aug 26 17

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

NOTES

1998 Aug 26 18

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

NOTES

1998 Aug 26 19

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© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545104/750/02/pp20 Date of release: 1998 Aug 26 Document order number: 9397 750 03378