Datasheet TDA8766G-C1-S2, TDA8766G-C1, TDA8766G-C1-S1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1995 Mar 22
File under Integrated Circuits, IC02

1996 Mar 20

INTEGRATED CIRCUITS

TDA8766

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

1996 Mar 20 2

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

FEATURES

• 10-bit resolution

• 2.7 to 5.25 V operation

• Sampling rate up to 20 MHz

• DC sampling allowed

• High signal-to-noise ratio over a large analog input

frequency range (9.3 effective bits at 1.0 MHz full-scale
input at f

clk

= 20 MHz)

• In range (IR) CMOS output

• CMOS/TTL compatible digital inputs and outputs

• External reference voltage regulator

• Power dissipation only 53 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• Standby mode

• No sample-and-hold circuit required.

APPLICATIONS

High-speed analog-to-digital conversion for:

• Video data digitizing

• Camera

• Camcorder

• Radio communication.

GENERAL DESCRIPTION

The TDA8766 is a 10-bit high-speed analog-to-digital
converter (ADC) for professional video and other
applications. It converts with 2.7 to 5.25 V operation the
analog input signal into 10-bit binary-coded digital words at
a maximum sampling rate of 20 MHz. All digital inputs and
outputs are CMOS compatible. A standby mode allows
reduction of the device power consumption down to 4 mW.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

analog supply voltage 2.7 3.3 5.25 V

V

DDD1

digital supply voltage 1 2.7 3.3 5.25 V

V

DDD2

digital supply voltage 2 2.7 3.3 5.25 V

V

DDO

output stages supply voltage 2.5 3.3 5.25 V

I

DDA

analog supply current − 7.5 10 mA

I

DDD

digital supply current − 7.5 10 mA

I

DDO

output stages supply current f

clk

= 20 MHz; CL= 20 pF;

ramp input

− 12mA

INL integral non-linearity f

clk

= 20 MHz; ramp input −±1±2 LSB

DNL differential non-linearity f

clk

= 20 MHz; ramp input −±0.25 ±0.7 LSB

f

clk(max)

maximum clock frequency 20 −−MHz

P

tot

total power dissipation V

DDA=VDDD=VDDO

= 3.3 V − 53 73 mW

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8766G LQFP32 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1

1996 Mar 20 3

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

19

10

14

R

LAD

11

15

V

RB

V

SSA

V

SSD2

V

SSOVSSD1

V

RM

V

RT

V

I

18

V

DDD2

7

2

V

DDA

28

29

30

31

27 D4

D5

D6

D7

D8

26
25

1

6

D3

D2
23 D1
22

D0

D9

IN RANGE LATCH

CMOS

OUTPUTS

LATCHES

ANALOG -TO - DIGITAL

CONVERTER

CLOCK DRIVER

MLC853

CMOS

OUTPUT

5

CLK

16

OE

STDBY

TDA8766

20

V

DDO

9

analog
ground

digital

ground 2

321

output

ground

digital

ground 1

analog

voltage input

data outputs

LSB

MSB

4

V

DDD1

IR
output

1996 Mar 20 4

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

PINNING

SYMBOL PIN DESCRIPTION

D9 1 data output; bit 9 (MSB)
IR 2 in range data output
V

SSD1

3 digital ground 1

V

DDD1

4 digital supply voltage 1 (2.7 to 5.25 V)
CLK 5 clock input
STDBY 6 standby mode input
V

DDA

7 analog supply voltage (2.7 to 5.25 V)
n.c. 8 not connected
V

SSA

9 analog ground
V

RB

10 reference voltage BOTTOM input

V

RM

11 reference voltage MIDDLE
n.c. 12 not connected
n.c. 13 not connected
V

I

14 analog input voltage
V

RT

15 reference voltage TOP input
OE 16 output enable input
n.c. 17 not connected

V

DDD2

18 digital supply voltage 2 (2.7 to 5.25 V)

V

SSD2

19 digital ground 2

V

DDO

20 positive supply voltage for output

stage (2.5 to 5.25 V)

V

SSO

21 digital output ground
D0 22 data output; bit 0 (LSB)
D1 23 data output; bit 1
n.c. 24 not connected
D2 25 data output; bit 2
D3 26 data output; bit 3
D4 27 data output; bit 4
D5 28 data output; bit 5
D6 29 data output; bit 6
D7 30 data output; bit 7
D8 31 data output; bit 8
n.c. 32 not connected

SYMBOL PIN DESCRIPTION

Fig.2 Pin configuration.

handbook, full pagewidth

TDA8766

MLC854

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

index

corner

D9

IR

V

DDD1

V

SSD1

V

CLK

STDBY

DDA

V

DDD2

V

SSD2

V

DDO

V

SSO

n.c.

n.c.
D1
D0

n.c.

n.c.

D8

D7

D6

D5

D4

D3

D2

SSA

n.c.

n.c.

OE

V

RB

V

RM

V

I

V

RT

V

1996 Mar 20 5

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

DDA

, V

DDD

and V

DDO

may have any value between −0.3 V and +7.0 V provided that the supply

voltage differences ∆VDD are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

analog supply voltage note 1 −0.3 +7.0 V

V

DDD1

, V

DDD2

digital supply voltages note 1 −0.3 +7.0 V

V

DDO

output stages supply voltage note 1 −0.3 +7.0 V

∆V

DD

supply voltage difference

V

DDA

− V

DDD

−1.0 +4.0 V

V

DDD

− V

DDO

−1.0 +4.0 V

V

DDA

− V

DDO

−1.0 +4.0 V

V

I

input voltage referenced to V

SSA

−0.3 +7.0 V

V

clk(p-p)

AC input voltage for switching
(peak-to-peak value)

referenced to V

SSD

− V

DDD

V

I

O

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature −20 +75 °C

T

j

junction temperature − +150 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 90 K/W

1996 Mar 20 6

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

CHARACTERISTICS

V

DDA=V7

to V9= 3.3 V; V

DDD=V4

to V3=V18to V19= 3.3 V; V

DDO=V20

to V21= 3.3 V; V

SSA,VSSD

and V

SSO

short-circuited together; V

i(p-p)

= 1.83 V; CL= 20 pF; T

amb

=0to+70°C; typical values measured at T

amb

=25°C;

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA

analog supply voltage 2.7 3.3 5.25 V

V

DDD1

digital supply voltage 1 2.7 3.3 5.25 V

V

DDD2

digital supply voltage 2 2.7 3.3 5.25 V

V

DDO

output stages supply voltage 2.5 3.3 5.25 V

∆V

DD

voltage difference

V

DDA

− V

DDD

−0.2 − +0.2 V

V

DDA

− V

DDO

−0.2 − +3.0 V

V

DDD

− V

DDO

−0.2 − +3.0 V

I

DDA

analog supply current − 7.5 10 mA

I

DDD

digital supply current − 7.5 10 mA

I

DDO

output stages supply current f

clk

= 20 MHz;

ramp input; CL=20pF

− 12 mA

Inputs

C

LOCK INPUT CLK (REFERENCED TO V

SSD

); see note 1

V

IL

LOW level input voltage 0 − 0.3V

DDD

V

V

IH

HIGH level input voltage 0.7V

DDD

− V

DDD

V

V

DDD

≤ 3.6 V 0.6V

DDD

− V

DDD

V

I

IL

LOW level input current V

clk

= 0.3V

DDD

−10+1µA

I

IH

HIGH level input current V

clk

= 0.7V

DDD

−−5µA

Z

I

input impedance f

clk

= 20 MHz − 4 − kΩ

C

I

input capacitance f

clk

= 20 MHz − 3 − pF

INPUTS OE AND STDBY (REFERENCED TO V

SSD

); see Table 3

V

IL

LOW level input voltage 0 − 0.3V

DDD

V

V

IH

HIGH level input voltage 0.7V

DDD

− V

DDD

V

V

DDD

≤ 3.6 V 0.6V

DDD

− V

DDD

V

I

IL

LOW level input current VIL= 0.3V

DDD

−1 −− µA

I

IH

HIGH level input current VIH= 0.7V

DDD

−−+1 µA

VI(ANALOG INPUT VOLTAGE REFERENCED TO V

SSA

)

I

IL

LOW level input current VI=V

RB

− 0 −µA

I

IH

HIGH level input current VI=V

RT

− 35 −µA

Z

I

input impedance fi= 1 MHz − 5 − kΩ

C

I

input capacitance fi= 1 MHz − 8 − pF

1996 Mar 20 7

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

Reference voltages for the resistor ladder; see Table 1
V

RB

reference voltage BOTTOM 1.1 1.2 − V

V

RT

reference voltage TOP V

TOP

≤ V

DDA

2.7 3.3 V

DDA

V

V

diff

differential reference voltage
VRT− V

RB

1.5 2.1 2.7 V

I

ref

reference current − 7.2 − mA

R

LAD

resistor ladder − 290 −Ω

TC

RLAD

temperature coefficient of the resistor
ladder

− 1860 − ppm

− 539 − mΩ/K

V

osB

offset voltage BOTTOM note 2 − 135 − mV

V

osT

offset voltage TOP note 2 − 135 − mV

V

i(p-p)

analog input voltage
(peak-to-peak value)

note 3 1.4 1.83 2.4 V

Outputs

D

IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO V

SSD

)

V

OL

LOW level output voltage IO=1mA 0 − 0.5 V

V

OH

HIGH level output voltage IO= −1mA V

DDO

− 0.5 − V

DDO

V

I

OZ

output current in 3-state mode 0.5V<VO<V

DDO

−20 − +20 µA

Switching characteristics

C

LOCK INPUT CLK; see Fig.4; note 1

f

clk(max)

maximum clock frequency 20 −− MHz

t

CPH

clock pulse width HIGH 15 −− ns

t

CPL

clock pulse width LOW 15 −− ns

Analog signal processing

L

INEARITY

INL integral non-linearity f

clk

= 20 MHz;

ramp input; (see Fig.6)

−±1±2 LSB

DNL differential non-linearity f

clk

= 20 MHz;

ramp input; (see Fig.7)

−±0.25 ±0.7 LSB

INPUT SET RESPONSE (f

clk

= 20 MHz; see Fig.8; note 4)

t

STLH

analog input settling time
LOW-to-HIGH

full-scale square wave − 46 ns

t

STHL

analog input settling time
HIGH-to-LOW

full-scale square wave − 46 ns

HARMONICS;(f

clk

=20MHZ; see Fig.9; note 5)

THD total harmonic distortion f

i

= 1 MHz −−63 − dB
SIGNAL-TO-NOISE RATIO; see Fig.9; note 5
S/N signal-to-noise ratio (full scale) without harmonics;

f

clk

= 20 MHz;

fi= 1 MHz

− 60 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Mar 20 8

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.

2. Analog input voltages producing code 0 up to and including 1023:
a) V

osB

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

the reference voltage BOTTOM (VRB) at T

amb

=25°C.

b) V

osT

(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

produces data outputs equal to 1023 at T

amb

=25°C.

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.

a) The current flowing into the resistor ladder is I

L

= and the full-scale input range at the converter,

to cover code 0 to code 1023, is

b) Since R

L

, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

will be kept reasonably constant from part to part. Consequently variation of the output codes

at a given input voltage depends mainly on the difference V

RT

− VRB and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.

E

FFECTIVE BITS; see Fig.9; note 5

EB effective bits f

clk

= 20 MHz

f

i

= 300 kHz − 9.5 − bits

f

i

= 1 MHz − 9.3 − bits

f

i

= 3.58 MHz − 8.0 − bits

Timing (f

clk

= 20 MHz; CL= 20 pF); see Fig.4; note 6

t

ds

sampling delay time −−5ns

t

h

output hold time 5 −− ns

t

d

output delay time V

DDO

= 4.75 V 8 12 15 ns

V

DDO

= 3.15 V 8 17 20 ns

V

DDO

= 2.7 V 8 21 24 ns
3-state output delay times; see Fig.5
t

dZH

enable HIGH − 14 18 ns

t

dZL

enable LOW − 16 20 ns

t

dHZ

disable HIGH − 16 20 ns

t

dLZ

disable LOW − 14 18 ns

Standby mode output delay times

t

dSTBLH

standby (LOW-to-HIGH transition) −−200 ns

t

dSTBHL

start-up (HIGH-to-LOW transition) −−500 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

RTVRB

–

R

OBRLROT

++

------------------------------------------

V

I

RLIL×

R

L

R

OBRLROT

++

------------------------------------------

V

RTVRB

–()0.871 VRTVRB–()×=×==

R

L

R

OBRLROT

++

-----------------------------------------

1996 Mar 20 9

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.

5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

6. Output data acquisition: the output data is available after the maximum delay time of td.

Fig.3 Explanation of note 3.

handbook, halfpage

R

LAD

R

OT

V

RT

V

RM

V

RB

R

OB

code 1023

code 0

MGD281

I

L

R

L

1996 Mar 20 10

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

Table 1 Output coding and input voltage (typical values; referenced to V

SSA

)

Table 2 Mode selection

Table 3 Standby selection

STEP

V

I(p-p)

(V)

IR

BINARY OUTPUT BITS

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Underflow <1.335 00000000000

0 1.335 10000000000
1 . 10000000001

. . ...........

. . ...........

1022 . 11111111110
1023 3.165 11111111111

Overflow >3.165 01111111111

OE D9 TO D0 IR

1 high impedance high impedance
0 active; binary active

STDBY D9 TO D0 I

DDA+IDDD

(typ.)

1 last logic state 1.2 mA
0 active 15 mA

Fig.4 Timing diagram.

handbook, full pagewidth

ds

t

sample N + 1

sample N

CLK

MGD346

sample N + 2

50%

V

l

DATA
D0 to D9

t

d

t

h

CPH

t

CPL

t

V

DDO

0 V

50%

DATA

N + 1

DATA

N

DATA

N - 1

DATA

N - 2

1996 Mar 20 11

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

Fig.5 Timing diagram and test conditions of 3-state output delay time.

fOE= 100kHz.

handbook, full pagewidth

MLC855

50 %

50 %

HIGH

LOW

dZH

t

dHZ

t

50 %

HIGH

LOW

dZL

t

dLZ

t

10 %

90 %

output
data

V

DDD

output
data

3.3 kΩ

20 pF

S1

V

DDD

TDA8766

OE

OE

TEST

dLZ

t

dZL

t

dHZ

t

dZH

S1

DDD

V

DDD

V

GND
GND

t

1996 Mar 20 12

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

Fig.6 Typical integral non-linearity (INL) performance.

handbook, full pagewidth

1023

−0.6
0 400 600 800 1000 1100200

MLD115

0.4

−0.2

−0.4

0.2

0

0.6

A

(LSB)

f (codes)

Fig.7 Typical differential non-linearity (DNL) performance.

handbook, full pagewidth

1023

−0.25
0 400 600 800 1000 1100200

MLD116

0.25

−0.05

−0.15

0.15

0.05

A

(LSB)

f (codes)

1996 Mar 20 13

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

Fig.8 Analog input settling-time diagram.

handbook, full pagewidth

MBD875

50 %

STLH

t

5 ns

code 0

code 1023

I

50 %

2 ns

50 %

5 ns

STHL

t

50 %

2 ns

CLK

V

Fig.9 Typical Fast Fourier Transform (f

clk

= 20 MHz; fi= 1 MHz).

Effective bits: 9.59; THD =−76.60 dB.
Harmonic levels (dB): 2nd =−81.85; 3rd = −87.56; 4th = −88.81; 5th = −88.96; 6th = −79.58.

handbook, full pagewidth

10

0

120

0 2.5 3.76 5.01 7.51 8.761.25 6.26

MLD117

40

80

100

60

20

A

(dB)

f (MHz)

1996 Mar 20 14

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

INTERNAL PIN CONFIGURATIONS

Fig.10 CMOS data and In Range (IR) outputs.

handbook, halfpage

MLC856

V

DDO

V

D9 to D0

IR

SSO

Fig.11 Analog inputs.

handbook, halfpage

MLC857

V

DDA

V

SSA

V

I

Fig.12 OE (STDBY) input.

handbook, halfpage

MLC858

V

DDO

V

SSO

OE

(STDBY)

Fig.13 VRB, VRM and VRT.

handbook, halfpage

R

MLC859

V

RB

V

RM

V

DDA

V

SSA

V

RT

LAD

1996 Mar 20 15

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

Fig.14 CLK input.

handbook, halfpage

V

DDD

V

SSD

CLK

MLC860

1

/2V

DDD

1996 Mar 20 16

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

APPLICATION INFORMATION

Additional application information will be supplied upon request (please quote number

“AN96012”

).

Fig.15 Application diagram.

The analog and digital supplies should be separated and decoupled.
The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value.

Eventually, the reference ladder voltages can be derived from a well regulated V

DDA

supply through a resistor bridge and a decoupled capacitor.

(1) VRB, VRM and VRT are decoupled to V

SSA

.
(2) Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence.
(3) When VRM is not used, pin 11 can be left open, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded.
(4) When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14).

handbook, full pagewidth

TDA8766

MLC861

1

2

3

4

24

23

22

21

20

19

18

17

9

D9

IR

V

DDD1

V

SSD1

V

CLK

STDBY

DDA

V

SSA

V

SSA

V

DDD2

V

SSD2

V

DDO

V

SSO

n.c.

D1

D0

n.c.

5

6

7

8

10

V

RB

11

V

RM

12

13 14

V

I

15

V

RT

16

OE

(2)

n.c.

(2)

n.c.

(2)

(1)

(3)

(4)

(1) (1)

(2)

n.c.

(2)

100

nF

V

SSA

100

nF

V

SSA

100

nF

32

31 30 29 28 27 26 25

D5 D4 D3n.c.

(2)

D2D8 D7 D6

1996 Mar 20 17

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

PACKAGE OUTLINE

0.2

UNIT

A

max.

A

1A2A3bp

cE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

1.60

0.15

0.05

1.5

1.3

0.25

0.27

0.17

0.18

0.12

5.1

4.9

0.5

7.15

6.85

1.0

0.95

0.55

7
0

o
o

0.12 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT401-1

95-12-19
97-08-04

D

(1) (1)(1)

5.1

4.9

H

D

7.15

6.85

E

Z

0.95

0.55

D

b

p

e

E

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8

D

H

b

p

E

H

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D

Z

D

A

Z

E

e

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A

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32

25

24

17

16

9

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L

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A

2

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w M

0 2.5 5 mm

scale

LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm

SOT401-1

c

pin 1 index

1996 Mar 20 18

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Mar 20 19

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

TDA8766

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211,

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Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS:

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China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

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Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300

COPENHAGEN S, Tel. [phone], Fax. [phone]

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]

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Hungary: see Austria
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Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS,

Piazza IV Novembre 3, 20124 MILANO,
Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO,

TEXAS 79905, Tel. [phone], Fax. [phone]

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC,
MAKATI, Metro MANILA,
Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220 - 5th floor, Suite 51,

CEP: 04552-903-SÃO PAULO-SP, Brazil,
P.O. Box 7383 (01064-970),
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,

Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-16485 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,

Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE,

2A Akademika Koroleva str., Office 165, 252148 KIEV,
Tel.[phone], Fax. [phone]

United Kingdom: Philips Semiconductors LTD.,

276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax. [phone]

Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Fax. [phone]

SCDS48 © Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

537021/1100/02/pp20 Date of release: 1996 Mar 20
Document order number: 9397 750 00746