Datasheet TDA8766 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8766

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

Product specification
Supersedes data of 1995 Mar 22
File under Integrated Circuits, IC02

1996 Mar 20

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

FEATURES

• 10-bit resolution

• 2.7 to 5.25 V operation

• Sampling rate up to 20 MHz

• DC sampling allowed

• High signal-to-noise ratio over a large analog input

frequency range (9.3 effective bits at 1.0 MHz full-scale
input at f

• In range (IR) CMOS output

• CMOS/TTL compatible digital inputs and outputs

• External reference voltage regulator

• Power dissipation only 53 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• Standby mode

• No sample-and-hold circuit required.

= 20 MHz)

clk

TDA8766

APPLICATIONS

High-speed analog-to-digital conversion for:

• Video data digitizing

• Camera

• Camcorder

• Radio communication.

GENERAL DESCRIPTION

The TDA8766 is a 10-bit high-speed analog-to-digital
converter (ADC) for professional video and other
applications. It converts with 2.7 to 5.25 V operation the
analog input signal into 10-bit binary-coded digital words at
a maximum sampling rate of 20 MHz. All digital inputs and
outputs are CMOS compatible. A standby mode allows
reduction of the device power consumption down to 4 mW.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
V
V
V
I

DDA

I

DDD

I

DDO

DDA
DDD1
DDD2
DDO

analog supply voltage 2.7 3.3 5.25 V
digital supply voltage 1 2.7 3.3 5.25 V
digital supply voltage 2 2.7 3.3 5.25 V
output stages supply voltage 2.5 3.3 5.25 V
analog supply current − 7.5 10 mA
digital supply current − 7.5 10 mA
output stages supply current f

= 20 MHz; CL= 20 pF;

clk

− 12mA

ramp input
INL integral non-linearity f
DNL differential non-linearity f
f

clk(max)

P

tot

maximum clock frequency 20 −−MHz
total power dissipation V

= 20 MHz; ramp input −±1±2 LSB

clk

= 20 MHz; ramp input −±0.25 ±0.7 LSB

clk

DDA=VDDD=VDDO

= 3.3 V − 53 73 mW

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8766G LQFP32 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1

1996 Mar 20 2

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

BLOCK DIAGRAM

handbook, full pagewidth

analog

voltage input

V

RT

V

V

RM

V

DDA

7

15

R

LAD

I

14

11

ANALOG -TO - DIGITAL

CONVERTER

CLK

5

CLOCK DRIVER

LATCHES

V

DDD2

18

TDA8766

OE
16

CMOS

OUTPUTS

6

1

D9
D8

31

D7

30

D6

29

D5

28
27 D4
26

D3

25

D2
23 D1
22

D0

TDA8766

STDBY

MSB

data outputs

LSB

V

10

RB

CMOS

OUTPUT

321

SSOVSSD1

digital

ground 1

9

V

analog
ground

SSA

19
V

digital

ground 2

SSD2

IN RANGE LATCH

V

output

ground

20

MLC853

V

DDO

IR

2

4

output

V

DDD1

Fig.1 Block diagram.

1996 Mar 20 3

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

PINNING

SYMBOL PIN DESCRIPTION

D9 1 data output; bit 9 (MSB)
IR 2 in range data output
V

SSD1

V

DDD1

CLK 5 clock input
STDBY 6 standby mode input
V

DDA

n.c. 8 not connected
V

SSA

V

RB

V

RM

n.c. 12 not connected
n.c. 13 not connected
V

I

V

RT

OE 16 output enable input
n.c. 17 not connected

3 digital ground 1
4 digital supply voltage 1 (2.7 to 5.25 V)

7 analog supply voltage (2.7 to 5.25 V)

9 analog ground
10 reference voltage BOTTOM input
11 reference voltage MIDDLE

14 analog input voltage
15 reference voltage TOP input

TDA8766

SYMBOL PIN DESCRIPTION

V

DDD2

V

SSD2

V

DDO

V

SSO

D0 22 data output; bit 0 (LSB)
D1 23 data output; bit 1
n.c. 24 not connected
D2 25 data output; bit 2
D3 26 data output; bit 3
D4 27 data output; bit 4
D5 28 data output; bit 5
D6 29 data output; bit 6
D7 30 data output; bit 7
D8 31 data output; bit 8
n.c. 32 not connected

18 digital supply voltage 2 (2.7 to 5.25 V)
19 digital ground 2
20 positive supply voltage for output

stage (2.5 to 5.25 V)

21 digital output ground

handbook, full pagewidth

index

corner

D9

V

SSD1

V

DDD1

CLK

STDBY

V

DDA

n.c.

n.c.

D8

D7

D6

D5

D4

D3

D2

32

31

30

29

28

27

26

25

1
2

IR

3
4

TDA8766

5
6
7
8

9

10

11

12

13

14

15

16

RT

OE

V

SSA

V

I

RB

RM

V

n.c.

V

n.c.

V

24
23
22
21
20
19
18
17

MLC854

n.c.
D1
D0

V

SSO

V

DDO

V

SSD2

V

DDD2

n.c.

Fig.2 Pin configuration.

1996 Mar 20 4

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

V

DDD1

V

DDO

∆V

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

DD

, V

DDD2

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltages note 1 −0.3 +7.0 V
output stages supply voltage note 1 −0.3 +7.0 V
supply voltage difference

− V

V
V
V

DDA
DDD
DDA

− V

− V

DDD
DDO
DDO

input voltage referenced to V
AC input voltage for switching

referenced to V

SSA
SSD

−1.0 +4.0 V

−1.0 +4.0 V

−1.0 +4.0 V

−0.3 +7.0 V

− V

DDD

(peak-to-peak value)
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature −20 +75 °C
junction temperature − +150 °C

V

Note

1. The supply voltages V

DDA

, V

DDD

and V

may have any value between −0.3 V and +7.0 V provided that the supply

DDO

voltage differences ∆VDD are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 90 K/W

1996 Mar 20 5

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

CHARACTERISTICS

V

DDA=V7

short-circuited together; V
unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA

V

DDD1

V

DDD2

V

DDO

∆V

I

DDA

I

DDD

I

DDO

DD

to V9= 3.3 V; V

DDD=V4

i(p-p)

to V3=V18to V19= 3.3 V; V

= 1.83 V; CL= 20 pF; T

DDO=V20

=0to+70°C; typical values measured at T

amb

to V21= 3.3 V; V

SSA,VSSD

and V

amb

SSO

=25°C;

analog supply voltage 2.7 3.3 5.25 V
digital supply voltage 1 2.7 3.3 5.25 V
digital supply voltage 2 2.7 3.3 5.25 V
output stages supply voltage 2.5 3.3 5.25 V
voltage difference

V
V
V

DDA
DDA
DDD

− V

− V

− V

DDD
DDO
DDO

−0.2 − +0.2 V

−0.2 − +3.0 V

−0.2 − +3.0 V

analog supply current − 7.5 10 mA
digital supply current − 7.5 10 mA
output stages supply current f

= 20 MHz;

clk

− 12 mA

ramp input; CL=20pF

Inputs

C

LOCK INPUT CLK (REFERENCED TO V

V

IL

V

IH

I

IL

I

IH

Z

I

C

I

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V

LOW level input current V
HIGH level input current V
input impedance f
input capacitance f

); see note 1

SSD

INPUTS OE AND STDBY (REFERENCED TO V
V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V

LOW level input current VIL= 0.3V

HIGH level input current VIH= 0.7V
VI(ANALOG INPUT VOLTAGE REFERENCED TO V
I

IL

I

IH

Z

I

C

I

LOW level input current VI=V

HIGH level input current VI=V

input impedance fi= 1 MHz − 5 − kΩ

input capacitance fi= 1 MHz − 8 − pF

); see Table 3

SSD

)

SSA

DDD

DDD

V

≤ 3.6 V 0.6V

DDD

= 0.3V

clk
clk

= 20 MHz − 4 − kΩ

clk

= 20 MHz − 3 − pF

clk

V

DDD

DDD

= 0.7V

DDD

≤ 3.6 V 0.6V

DDD
DDD

RB
RT

DDD

−10+1µA

−−5µA

DDD
DDD

−1 −− µA

−−+1 µA

− 0 −µA

− 35 −µA

− V

− V

− V

− V

DDD
DDD

DDD
DDD
DDD

V
V
V

V
V
V

1996 Mar 20 6

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Reference voltages for the resistor ladder; see Table 1

V

RB

V

RT

V

diff

I

ref

R

LAD

TC

RLAD

V

osB

V

osT

V

i(p-p)

Outputs

D

IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO V

V

OL

V

OH

I

OZ

Switching characteristics

reference voltage BOTTOM 1.1 1.2 − V
reference voltage TOP V
differential reference voltage

VRT− V

RB

TOP

≤ V

DDA

2.7 3.3 V

DDA

1.5 2.1 2.7 V

V

reference current − 7.2 − mA
resistor ladder − 290 −Ω
temperature coefficient of the resistor

ladder

− 1860 − ppm

− 539 − mΩ/K

offset voltage BOTTOM note 2 − 135 − mV
offset voltage TOP note 2 − 135 − mV
analog input voltage

note 3 1.4 1.83 2.4 V

(peak-to-peak value)

)

SSD

LOW level output voltage IO=1mA 0 − 0.5 V
HIGH level output voltage IO= −1mA V
output current in 3-state mode 0.5V<VO<V

DDO

− 0.5 − V

DDO

DDO

V

−20 − +20 µA

C

LOCK INPUT CLK; see Fig.4; note 1

f

clk(max)

t

CPH

t

CPL

maximum clock frequency 20 −− MHz
clock pulse width HIGH 15 −− ns
clock pulse width LOW 15 −− ns

Analog signal processing

L

INEARITY

INL integral non-linearity f

= 20 MHz;

clk

ramp input; (see Fig.6)

DNL differential non-linearity f

= 20 MHz;

clk

ramp input; (see Fig.7)
INPUT SET RESPONSE (f
t

STLH

analog input settling time

= 20 MHz; see Fig.8; note 4)

clk

full-scale square wave − 46 ns

LOW-to-HIGH

t

STHL

analog input settling time

full-scale square wave − 46 ns

HIGH-to-LOW
HARMONICS;(f
THD total harmonic distortion f

=20MHZ; see Fig.9; note 5)

clk

= 1 MHz −−63 − dB

i

SIGNAL-TO-NOISE RATIO; see Fig.9; note 5
S/N signal-to-noise ratio (full scale) without harmonics;

f

= 20 MHz;

clk

fi= 1 MHz

−±1±2 LSB

−±0.25 ±0.7 LSB

− 60 − dB

1996 Mar 20 7

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

E

FFECTIVE BITS; see Fig.9; note 5

EB effective bits f

Timing (f

t

ds

t

h

t

d

= 20 MHz; CL= 20 pF); see Fig.4; note 6

clk

sampling delay time −−5ns

output hold time 5 −− ns

output delay time V

3-state output delay times; see Fig.5
t

dZH

t

dZL

t

dHZ

t

dLZ

enable HIGH − 14 18 ns

enable LOW − 16 20 ns

disable HIGH − 16 20 ns

disable LOW − 14 18 ns

Standby mode output delay times

t

dSTBLH

t

dSTBHL

standby (LOW-to-HIGH transition) −−200 ns

start-up (HIGH-to-LOW transition) −−500 ns

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.

2. Analog input voltages producing code 0 up to and including 1023:
a) V

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

osB

the reference voltage BOTTOM (VRB) at T

b) V

(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

osT

produces data outputs equal to 1023 at T

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.

= 20 MHz

clk

f

= 300 kHz − 9.5 − bits

i

f

= 1 MHz − 9.3 − bits

i

= 3.58 MHz − 8.0 − bits

f

i

= 4.75 V 8 12 15 ns

DDO

= 3.15 V 8 17 20 ns

V

DDO

V

= 2.7 V 8 21 24 ns

DDO

=25°C.

amb

=25°C.

amb

a) The current flowing into the resistor ladder is I

to cover code 0 to code 1023, is

b) Since R

----------------------------------------­R

, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

L

R

L

++

OBRLROT

will be kept reasonably constant from part to part. Consequently variation of the output codes

V

RLIL×

I

= and the full-scale input range at the converter,

------------------------------------------

L

R

OBRLROT

-----------------------------------------­R

OBRLROT

at a given input voltage depends mainly on the difference V
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.

1996 Mar 20 8

V

–

RTVRB

++

R

L

++

RT

V

–()0.871 VRTVRB–()×=×==

RTVRB

− VRB and its variation with temperature and supply

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.

5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

6. Output data acquisition: the output data is available after the maximum delay time of td.

handbook, halfpage

V

V

V

RT

RM

RB

9

R

OT

code 1023

R

7

R

LAD

6

L

I

L

R

OB

MGD281

code 0

Fig.3 Explanation of note 3.

1996 Mar 20 9

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

Table 1 Output coding and input voltage (typical values; referenced to V

STEP

V

I(p-p)

(V)

IR

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

BINARY OUTPUT BITS

Underflow <1.335 00000000000

0 1.335 10000000000
1 . 10000000001

. . ...........

. . ...........

1022 . 11111111110
1023 3.165 11111111111

Overflow >3.165 01111111111

Table 2 Mode selection

OE D9 TO D0 IR

1 high impedance high impedance
0 active; binary active

SSA

)

Table 3 Standby selection

STDBY D9 TO D0 I

1 last logic state 1.2 mA
0 active 15 mA

handbook, full pagewidth

CLK

V

l

DATA
D0 to D9

t

sample N

DATA

N - 2

CPH

DDA+IDDD

t

CPL

sample N + 1

t

ds

DATA

N - 1

t

d

sample N + 2

t

h

DATA

N

DATA

N + 1

MGD346

(typ.)

50%

V

DDO

50%
0 V

Fig.4 Timing diagram.

1996 Mar 20 10

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

handbook, full pagewidth

V

DDD

OE

output
data

output
data

LOW

t

dLZ

10 %

TDA8766

OE

HIGH

TDA8766

50 %

LOW

S1

V

DDD

t

dZH

50 %

TEST

t

dLZ

t

dZL

t

dHZ

t

dZH

S1

V

DDD

V

DDD

GND
GND

MLC855

t

dHZ

HIGH

t

dZL

50 %

3.3 kΩ

20 pF

90 %

fOE= 100kHz.

Fig.5 Timing diagram and test conditions of 3-state output delay time.

1996 Mar 20 11

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

handbook, full pagewidth

0.6

A

(LSB)

0.4

0.2

0

−0.2

−0.4

−0.6

0 400 600 800 1000 1100200

f (codes)

TDA8766

MLD115

1023

0.25

handbook, full pagewidth

A

(LSB)

0.15

0.05

−0.05

−0.15

−0.25

0 400 600 800 1000 1100200

Fig.6 Typical integral non-linearity (INL) performance.

f (codes)

MLD116

1023

Fig.7 Typical differential non-linearity (DNL) performance.

1996 Mar 20 12

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

handbook, full pagewidth

code 1023

V

code 0

CLK

MBD875

I

50 %

5 ns

t

STLH

50 %

2 ns

5 ns

t

STHL

50 %

50 %

TDA8766

2 ns

Fig.8 Analog input settling-time diagram.

handbook, full pagewidth

0

A

(dB)

20

40

60

80

100

120

0 2.5 3.76 5.01 7.51 8.761.25 6.26

Effective bits: 9.59; THD =−76.60 dB.
Harmonic levels (dB): 2nd =−81.85; 3rd = −87.56; 4th = −88.81; 5th = −88.96; 6th = −79.58.

MLD117

10

f (MHz)

Fig.9 Typical Fast Fourier Transform (f

1996 Mar 20 13

= 20 MHz; fi= 1 MHz).

clk

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

INTERNAL PIN CONFIGURATIONS

handbook, halfpage

MLC856

V

DDO

D9 to D0

IR

V

SSO

handbook, halfpage

V

V

DDA

SSA

TDA8766

V

I

MLC857

Fig.10 CMOS data and In Range (IR) outputs.

handbook, halfpage

V

DDO

OE

(STDBY)

V

SSO

MLC858

handbook, halfpage

V

V

DDA

V
V
V

SSA

Fig.11 Analog inputs.

RT

RM

RB

R

LAD

MLC859

Fig.12 OE (STDBY) input.

1996 Mar 20 14

Fig.13 VRB, VRM and VRT.

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

V

DDD

handbook, halfpage

CLK

V

SSD

1

/2V

MLC860

TDA8766

DDD

Fig.14 CLK input.

1996 Mar 20 15

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

APPLICATION INFORMATION

Additional application information will be supplied upon request (please quote number

handbook, full pagewidth

D9

V

SSD1

V

DDD1

CLK

STDBY

V

DDA

n.c.

(2)

32

31 30 29 28 27 26 25

1

IR

2

3

4

TDA8766

5

6

7

(2)

8

12

11

(1)

V

RM

(3)

100

nF

9

10

V

V

SSA

SSA

(1) (1)

V

RB

100

nF

V

SSA

n.c.

13 14

(2)

n.c.

D5 D4 D3n.c.

15

(2)

(4)

V

I

100

nF

V

SSA

D2D8 D7 D6

24

23

22

21

20

19

18

17

16

OE

V

RT

“AN96012”

(2)

n.c.

D1

D0

V

SSO

V

DDO

V

SSD2

V

DDD2

(2)

n.c.

MLC861

TDA8766

).

The analog and digital supplies should be separated and decoupled.
The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value.

Eventually, the reference ladder voltages can be derived from a well regulated V
(1) VRB, VRM and VRT are decoupled to V
(2) Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence.
(3) When VRM is not used, pin 11 can be left open, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded.
(4) When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14).

SSA

.

supply through a resistor bridge and a decoupled capacitor.

DDA

Fig.15 Application diagram.

1996 Mar 20 16

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

PACKAGE OUTLINE

LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm

c

y

X

24

25

17

Z

16

E

A

TDA8766

SOT401-1

pin 1 index

32

1

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

1.60

A

1A2A3bp

0.15

1.5

1.3

0.25

0.05

UNIT

w M

b

p

D

H

D

cE

0.27

0.18

0.17

0.12

e

w M

b

9

8

Z

D

B

0 2.5 5 mm

(1) (1)(1)

D

5.1

4.9

p

v M

v M

scale

(1)

eH

5.1

0.5

4.9

H

7.15

6.85

D

E

A

B

H

E

E

7.15

6.85

A

2

A

A

1

detail X

LLpQZywv θ

0.70

0.75

1.0

0.45

0.57

0.2

0.12 0.1

L

L

Z

0.95

0.55

Q

(A )

3

θ

p

E

D

0.95

0.55

o

7

o

0

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

SOT401-1

IEC JEDEC EIAJ

REFERENCES

1996 Mar 20 17

EUROPEAN

PROJECTION

ISSUE DATE

94-04-25
95-12-19

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

(order code 9398 652 90011).

TDA8766

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Mar 20 18

Philips Semiconductors Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Mar 20 19

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211,

Volodarski Str. 6, 220050 MINSK,
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Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS:

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Chile: see South America
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300

COPENHAGEN S, Tel. [phone], Fax. [phone]

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

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Hungary: see Austria
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Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

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Piazza IV Novembre 3, 20124 MILANO,
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Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong,

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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO,

TEXAS 79905, Tel. [phone], Fax. [phone]

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,

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MAKATI, Metro MANILA,
Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

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Portugal: see Spain
Romania: see Italy
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
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P.O. Box 7383 (01064-970),
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,

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Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

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Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE,

2A Akademika Koroleva str., Office 165, 252148 KIEV,
Tel.[phone], Fax. [phone]

United Kingdom: Philips Semiconductors LTD.,

276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax. [phone]

Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Fax. [phone]

SCDS48 © Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

537021/1100/02/pp20 Date of release: 1996 Mar 20
Document order number: 9397 750 00746