Datasheet TDA8765H-5-C1, TDA8765H-4-C1 Datasheet (Philips)

DATA SH EET

Preliminary specification
Supersedes data of 1998 May 08
File under Integrated Circuits, IC02

1999 Jan 06

INTEGRATED CIRCUITS

TDA8765

10-bit high-speed Analog-to-Digital
Converter (ADC)

1999 Jan 06 2

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

FEATURES

• 10-bit resolution

• Sampling rate up to 55 MHz

•−3 dB bandwidth of 200 MHz

• 5 V power supplies

• Binary or twos-complement CMOS outputs

• In-range CMOS-compatible output

• TLL- CMOS-compatible static digital inputs

• 3 to 5 V CMOS-compatible digital outputs

• Differential clock input; Positive Emitter Coupled Logic

(PECL) compatible

• Power dissipation 325 mW (typical)

• Low analog input capacitance (typical 2 pF), no buffer

amplifier required

• Integrated sample-and-hold amplifier

• Differential analog input

• External amplitude range control

• Voltage controlled regulator included.

APPLICATIONS

• High-speed analog-to-digital conversion for
– Video signal digitizing
– High Definition TV (HDTV)
– Imaging (camera scanner)
– Medical imaging
– Telecommunication
– Base-station receiver.

GENERAL DESCRIPTION

The TDA8765 is a bipolar 10-bit Analog-to-Digital
Converter (ADC) optimized for telecommunications and
professional imaging. It converts the analog input signal
into 10-bit binary coded digital words at a maximum
sampling rate of 55 MHz. All static digital inputs (SH,

CE
and OTC) are TTL and CMOS compatible and all outputs
are CMOS compatible. A sine wave clock input signal can
also be used.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output supply voltage 3.0 3.3 5.25 V

I

CCA

analog supply current − 33 tbf mA

I

CCD

digital supply current − 30 tbf mA

I

CCO

output supply current f

CLK

= 4 MHz; fi= 400 kHz − 3.2 tbf mA

INL integral non-linearity f

CLK

= 4 MHz; fi= 400 kHz −±0.5 ±1.75 LSB

DNL differential non-linearity f

CLK

= 4 MHz; fi= 400 kHz −±0.3 ±0.5 LSB

f

CLK(max)

maximum clock frequency

TDA8765H/4 40 −−MHz
TDA8765H/5 55 −−MHz

P

tot

total power dissipation − 325 tbf mW

TYPE

NUMBER

PACKAGE

SAMPLING

FREQUENCY (MHz)

NAME DESCRIPTION VERSION

TDA8765H/4

QFP44

plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10 × 10 × 1.75 mm

SOT307-2

40

TDA8765H/5 55

1999 Jan 06 3

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGK801

MSB

data outputs

19

D9
D8
D7
D6
D5
D4
D3

43
42

39

11

V

ref

SH

1, 5 to 8,
12 to 14, 16, 31 and 32

n.c.

D2

21
22
23
24
25
26
27
28

29
30

D1
D0

LSB

V

CCO

33

IR

34

20

18

CMOS

OUTPUTS

LATCHES

ANALOG-TO-DIGITAL

CONVERTER

CLOCK DRIVER

15

V

CCD2

37

V

CCD1

41

V

CCA4

3

V

CCA3

9

V

CCA2

2

V

CCA1

36

CLK

35

CLK

CMOS

OUTPUT

OGND

OVERFLOW/

UNDERFLOW

LATCH

CEOTC

sample-

and-hold

TDA8765

17

DGND2

38

DGND1

40

AGND4

4

AGND3

10

AGND2

44

AGND1

V

I

V

I

AMP

1999 Jan 06 4

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
V

CCA1

2 analog supply voltage 1 (+5 V)

V

CCA3

3 analog supply voltage 3 (+5 V)
AGND3 4 analog ground 3
n.c. 5 not connected
n.c. 6 not connected
n.c. 7 not connected
n.c. 8 not connected
V

CCA2

9 analog supply voltage 2 (+5 V)
AGND2 10 analog ground 2
V

ref

11 reference voltage input
n.c. 12 not connected
n.c. 13 not connected
n.c. 14 not connected
V

CCD2

15 digital supply voltage 2 (+5 V)
n.c. 16 not connected
DGND2 17 digital ground 2
OTC

18

control input twos complement
output; active HIGH

CE

19

chip enable input

(CMOS level; active LOW)
IR 20 in-range output
D9 21 data output; bit 9 (MSB)
D8 22 data output; bit 8

D7 23 data output; bit 7
D6 24 data output; bit 6
D5 25 data output; bit 5
D4 26 data output; bit 4
D3 27 data output; bit 3
D2 28 data output; bit 2
D1 29 data output; bit 1
D0 30 data output; bit 0 (LSB)
n.c. 31 not connected
n.c. 32 not connected
V

CCO

33 output supply voltage (3 to 5.25 V)
OGND 34 output ground
CLK

35

complementary clock input; active

LOW
CLK 36 clock input
V

CCD1

37 digital supply voltage 1 (+5 V)
DGND1 38 digital ground 1
SH 39 sample-and-hold enable input

(CMOS level; active HIGH)
AGND4 40 analog ground 4
V

CCA4

41 analog supply voltage 4 (+5 V)

V

I

42 positive analog input voltage

V

I

43 negative analog input voltage

AGND1 44 analog ground 1

SYMBOL PIN DESCRIPTION

1999 Jan 06 5

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

Fig.2 Pin configuration.

handbook, full pagewidth

TDA8765H

MGK800

1
2
3
4
5
6
7
8

9
10
11

33
32
31
30
29
28
27
26
25
24
23

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

n.c.

n.c.
n.c.

n.c.
n.c.

V

CCA1

V

CCA3

V

CCA2

V

ref

AGND3

AGND2

n.c.

n.c.

n.c.

n.c.

IR

D9

D8

DGND2

V

CCD2

CE

OTC

n.c.

n.c.

OGND

DGND1

AGND4

AGND1

V

CCD1

V

CCA4

CLK

V

CCO

CLK

SH

D7

D6

D5

D4

D3

D2

D1

D0

VIV

I

1999 Jan 06 6

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

CCA

, V

CCD

and V

CCO

may have any value between −0.3 and +7.0 V provided that the supply

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage note 1 −0.3 +7.0 V

V

CCD

digital supply voltage note 1 −0.3 +7.0 V

V

CCO

output supply voltage note 1 −0.3 +7.0 V

∆V

CC

supply voltage difference

V

CCA

− V

CCD

−1.0 +1.0 V

V

CCD

− V

CCO

−1.0 +4.0 V

V

CCA

− V

CCO

−1.0 +4.0 V

V

I

input voltage at pins 42 and 43 referenced to AGND 0.3 V

CCA

V

V

i(p-p)

input voltage at pins 35 and 36 for
differential clock drive (peak-to-peak
value)

− V

CCD

V

I

O

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature 0 +85 °C

T

j

junction temperature − 150 °C

SYMBOL PARAMETER CONDITION VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 75 K/W

1999 Jan 06 7

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

CHARACTERISTICS

V

CCA=V2

to V44, V9to V10, V3to V4 and V41to V40= 4.75 to 5.25 V; V

CCD=V37

to V38and V15to V17= 4.75 to 5.25 V;

V

CCO=V33

to V34= 3.0 to 5.25 V; AGND and DGND shorted together; T

amb

= 0 to 85 °C; typical values measured at

V

CCA=VCCD

= 5 V and V

CCO

= 3.3 V, T

amb

=25°C, V

I(p-p)

− V

I(p-p)

= 2.0 V and CL= 10 pF; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output supply voltage 3.0 3.3 5.25 V

I

CCA

analog supply current − 33 45 mA

I

CCD

digital supply current − 30 37 mA

I

CCO

output supply current f

CLK

= 4 MHz; fi= 400 kHz − 3.2 tbf mA

f

CLK

= 40 MHz;

fi= 4.43 MHz

− 11 tbf mA

Inputs

CLK

AND CLK (REFERENCED TO DGND)

V

IL

LOW-level input voltage V

CCD

= 5 V; note 1 3.19 − 3.52 V

V

IH

HIGH-level input voltage V

CCD

= 5 V; note 1 3.83 − 4.12 V

I

IL

LOW-level input current V

CLK

or V

CLK

= 3.19 V −10 −−µA

I

IH

HIGH-level input current V

CLK

or V

CLK

= 3.83 V −−10 µA

Z

i

input impedance f

CLK

= 40 MHz 2 −−kΩ

C

i

input capacitance f

CLK

= 40 MHz −−2pF

∆V

CLK(p-p)

differential AC input voltage
for switching (V

CLK

− V

CLK

;

peak-to-peak value)

DC voltage level = 2.5 V 0.5 − 2.0 V

OTC, SH AND CE (REFERENCED TO DGND); see Tables 2 and 3
V

IL

LOW-level input voltage 0 − 0.8 V

V

IH

HIGH-level input voltage 2.0 − V

CCD

V

I

IL

LOW-level input current VIL= 0.8 V −20 −−µA

I

IH

HIGH-level input current VIH= 2.0 V −−20 µA

V

I

AND V

I

(REFERENCED TO AGND; see Table 1); V

REF

=V

CCA

− 1.825 V

I

IL

LOW-level input current − 10 −µA

I

IH

HIGH-level input current − 10 −µA

R

i

input resistance fi= 4.43 MHz 100 −−kΩ

C

i

input capacitance fi= 4.43 MHz −−2pF

V

I(CM)

common mode input voltage VI= VI; output code 511

V

CCA

= 5 V tbf 3.6 tbf V

V

CCA

= 4.75 V tbf 3.35 tbf V

V

CCA

= 5.25 V tbf 3.85 tbf V

1999 Jan 06 8

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

Voltage controlled regulator input V

ref

(referenced to AGND); note 2

V

ref

full-scale fixed voltage V

CCA

=5V − 3.175 − V

V

I(p-p)

− V

I(p-p)

input voltage amplitude
(peak-to-peak value)

V

ref=VCCA

− 1.825 V − 2.0 − V

I

ref

input current at V

ref

− 0.5 10 µA

Outputs (referenced to OGND)

D

IGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND)

V

OL

LOW-level output voltage IOL=2mA 0 − 0.5 V

V

OH

HIGH-level output voltage IOH= −0.4 mA V

CCO

− 0.5 − V

CCO

V

I

o

output current in 3-state output level between 0.5 V

and V

CCO

−20 − +20 µA

Switching characteristics

C

LOCK FREQUENCY f

CLK

; see Fig.5

f

CLK(min)

minimum clock frequency SH = HIGH −−1 MHz

SH = LOW −−1 kHz

f

CLK(max)

maximum clock frequency

TDA8765H/4 40 −−MHz
TDA8765H/5 55 −−MHz

t

CLKH

clock pulse width HIGH 8.5 −−ns

t

CLKL

clock pulse width LOW 8.5 −−ns

Analog signal processing; 50% clock duty factor; V

I

− VI= 2.0 V; V

ref=VCCA

− 1.825 V; see Table 1

L

INEARITY

INL integral non-linearity f

CLK

= 4 MHz; fi= 400 kHz −±0.5 ±1.75 LSB

DNL differential non-linearity f

CLK

= 4 MHz; fi= 400 kHz;

no missing code

−±0.3 ±0.5 LSB

E

offset

offset error V

CCA=VCCD=VCCO

=5V;

T

amb

=25°C; VI= VI;

output code = 511

tbf −11 tbf mV

E

G

gain error amplitude; spread
from device to device

V

CCA=VCCD=VCCO

=5V;

T

amb

=25°C;

V

I(p-p)

− V

I(p-p)

= 2.0 V

−5 − +5 %FS

BANDWIDTH (f

CLK

= 55 MHz); note 3

B analog bandwidth −3 dB; full-scale input tbf 200 − MHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Jan 06 9

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

HARMONICS (f

CLK

= 40 MHz)

H

fund(FS)

fundamental harmonics
(full scale)

fi= 4.43 MHz −−0dB

H

tot(FS)

harmonics (full scale);
all components

fi= 4.43 MHz

second harmonic −−75 − dB
third harmonic −−70 − dB

THD total harmonic distortion f

i

= 4.43 MHz; note 4 −−66 − dB
THERMAL NOISE
N

th(rms)

thermal noise (RMS value) grounded input;

f

CLK

= 40 MHz

− 0.2 tbf LSB

SPURIOUS FREE DYNAMIC RANGE
DR

sf

spurious free dynamic range fi= 4.43 MHz tbf 71 − dB

f

i

= 10 MHz tbf 68 − dB

f

i

= 20 MHz tbf 67 − dB
SIGNAL-TO-NOISE RATIO; note 5
S/N signal-to-noise ratio without harmonics;

f

CLK

= 40 MHz;

fi= 4.43 MHz

− 59 − dB

EFFECTIVE NUMBER OF BITS; see Figs 3 and 4 and note 5
N

bit

effective number of bits
TDA8765H/4
(f

CLK

= 40 MHz)

fi= 4.43 MHz 9.0 9.6 − bits
f

i

=10MHz − 9.6 − bits

f

i

=15MHz − 9.5 − bits

effective number of bits
TDA8765H/5
(f

CLK

= 55 MHz)

fi= 4.43 MHz − 9.6 − bits
f

i

=10MHz − 9.4 − bits

f

i

=15MHz − 9.3 − bits

f

i

=20MHz − 9.1 − bits
INTERMODULATION; note 6
TTIR two-tone intermodulation

rejection

f

CLK

= 40 MHz tbf 66 − dB

d

3

third-order intermodulation
distortion

f

CLK

= 40 MHz tbf 67 − dB

BIT ERROR RATE
BER bit error rate f

CLK

= 40 MHz;
fi= 4.43 MHz;
VI= ±16 LSB at code 511

− 10

−15

tbf times/

sample

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Jan 06 10

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

Notes

1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:
a) PECL mode 1 (DC level varies equal to DC level of V

CCD

): CLK and CLK inputs are at differential PECL levels.

b) PECL mode 2 (DC level varies equal to DC level of V

CCD

): CLK input is at PECL level and sampling is taken on
the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.

c) PECL mode 3 (DC level varies equal to DC level of V

CCD

): CLK input is at PECL level and sampling is taken on
the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.

d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with

a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.

2. It is possible with an external reference connected to pin V

ref

to adjust the ADC input range. This voltage has to be

referenced to V

CCA

. For V

CCA

− 1.825 V, the differential input voltage amplitude is 2 V (p-p).

3. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
full-scale sine wave.

4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:

where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.

5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all
harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:
SNR = N

bit

× 6.02 + 1.76 dB.

6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6dB
below full scale for each input signal).
d3 is the ratio of the RMS-value of either input tone to the RMS-value of the worst case third order intermodulation
product.

7. Output data acquisition: the output data is available after the maximum delay of td.

Timing (C

L

= 10 pF); see Fig.5 and note 7

t

d(s)

sampling delay time −−2ns

t

h

output hold time 4 −−ns

t

d

output delay time V

CCO

= 5.25 V − 10 15 ns

V

CCO

= 3.0 V − 13 18 ns
3-state output delay times; see Fig.6
t

dZH

enable HIGH − 14 18 ns

t

dZL

enable LOW − 16 20 ns

t

dHZ

disable HIGH − 16 20 ns

t

dLZ

disable LOW − 14 18 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

THD 20log

F

(2nd)2(3rd)2(4th)2(5th)2(6th)

2

++++

---------------------------------------------------------------------------------------------------------------=

1999 Jan 06 11

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

Table 1 Output coding with differential inputs (typical values to AGND); V

i(p-p)

− V

i(p-p)

= 2.0 V; V

ref=VCCA

− 1.825 V

Table 2 Mode selection

Note

1. X = don’t care.

Table 3 Sample-and-hold selection

CODE V

i(p-p)

V

i(p-p)

IR

BINARY OUTPUTS

TWOS COMPLEMENT

OUTPUTS

D9 TO D0 D9 TO D0

Underflow <3.1 >4.1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

0 3.1 4.1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 00
1 −−1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1

↓−−↓ ↓ ↓

511 3.6 3.6 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

↓−−↓ ↓ ↓

1022 −−1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0
1023 4.1 3.1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

Overflow >4.1 <3.1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

OTC

CE D0 TO D9 AND IR

0 0 binary; active
1 0 twos complement; active

X

(1)

1 high impedance

SH SAMPLE-AND-HOLD

1 active
0 inactive; tracking mode

1999 Jan 06 12

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

Fig.4 Typical fast Fourier transform (f

CLK

= 50 MHz; fi= 21.4 MHz).

Effective bits: 9.12; THD = −62.5 dB.
Harmonic levels (dB): 2nd = −73.0; 3rd = −63.4; 4th = −80.9; 5th = −78.1; 6th = −74.4.

handbook, full pagewidth

0

−160

−140

0 5 10 15

f (MHz)

amplitude

(dB)

2520

−80

−60

−40

−20

−120

−100

MGL431

Fig.3 Typical fast Fourier transform (f

CLK

= 40 MHz; fi= 4.43 MHz).

Effective bits: 9.68; THD = −70.8 dB.
Harmonic levels (dB): 2nd = −80.3; 3rd = −74.5; 4th = −87.7; 5th = −76.4; 6th = −78.6.

handbook, full pagewidth

0

−160

−140

0 5 10 15

f (MHz)

amplitude

(dB)

20

−80

−60

−40

−20

−120

−100

MGL430

1999 Jan 06 13

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

Fig.5 Timing diagram.

handbook, full pagewidth

t

d(s)

sample N + 1

sample N

CLK

MBH427

sample N + 2

DATA

D0 to D9

t

d

t

h

HIGH

LOW

HIGH

LOW

50%

DATA

N + 1

DATA

N

DATA

N − 1

DATA

N − 2

50%

t

CLKH

t

CLKL

V

I

Fig.6 Timing diagram and test conditions of 3-state output delay time.

fCE= 100 kHz.

handbook, full pagewidth

MBH423

50 %

50 %

HIGH

LOW

t

dZH

t

dHZ

50 %

HIGH

LOW

t

dZL

t

dLZ

10 %

90 %

output
data

V

CCD

output
data

3.3 kΩ

15 pF

S1

V

CCD

TDA8765

CE

CE

TEST

t

dLZ

t

dZL

t

dHZ

S1

V

CCD

V

CCD
DGND
DGND

t

dZH

0 V

1999 Jan 06 14

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

APPLICATION INFORMATION

Fig.7 Application diagram.

The analog, digital and output supplies should be separated and decoupled.
(1) Single-ended clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain a middle voltage of 3.6 V; see common mode input voltage.

In addition, the minimum current into these resistors should be about 1 mA in order to ensure a sufficient analog input stability.

(3) V

ref

must be decoupled to V

CCA

.

handbook, full pagewidth

MGK802

1

R1

1 : 1

R2

V

CCA

2

3
4
5
6
7
8
9
10
11

12

n.c.

n.c.

n.c. n.c.

13 14 15 16 17 18 19 20 21 22

IR

D9

(MSB)

D8

TDA8765

44 43 42 41 40 39 38 37 36 35 34

33
32
31
30
29
28

26
25
24
23

27

n.c.

n.c

5 V

100 nF

5 V

100 nF

100 nF

10 nF4.7 µF

220 nF

100 nF

100 Ω

output format select

chip select input

5 V

100 nF

V

ref

(3)

5 V

n.c.

n.c.

n.c.

n.c.

IN

n.c.

CLK

CLK

(1)

100 nF

100 nF

5 V5 V SH

mode

100 Ω

D2

D1

D0 (LSB)

D3
D4
D5
D6
D7

V

I

V

I

1999 Jan 06 15

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

PACKAGE OUTLINE

UNIT A1A2A3bpcE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.25

0.05

1.85

1.65

0.25

0.40

0.20

0.25

0.14

10.1

9.9

0.8 1.3

12.9

12.3

1.2

0.8

10

0

o

o

0.15 0.10.15

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.95

0.55

SOT307-2

95-02-04
97-08-01

D

(1) (1)(1)

10.1

9.9

H

D

12.9

12.3

E

Z

1.2

0.8

D

e

E

B

11

c

E

H

D

Z

D

A

Z

E

e

v M

A

X

1

44

34

33 23

22

12

y

θ

A

1

A

L

p

detail X

L

(A )

3

A

2

pin 1 index

D

H

v M

B

b

p

b

p

w M

w M

0 2.5 5 mm

scale

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

A

max.

2.10

1999 Jan 06 16

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Jan 06 17

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1999 Jan 06 18

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

NOTES

1999 Jan 06 19

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1999 SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands 545104/750/02/pp20 Date of release: 1999Jan 06 Document order number: 9397 750 04716