Datasheet tda8765 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8765

10-bit high-speed Analog-to-Digital
Converter (ADC)

Preliminary specification
Supersedes data of 1998 May 08
File under Integrated Circuits, IC02

1999 Jan 06

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

FEATURES

• 10-bit resolution

• Sampling rate up to 55 MHz

•−3 dB bandwidth of 200 MHz

• 5 V power supplies

• Binary or twos-complement CMOS outputs

• In-range CMOS-compatible output

• TLL- CMOS-compatible static digital inputs

• 3 to 5 V CMOS-compatible digital outputs

• Differential clock input; Positive Emitter Coupled Logic

(PECL) compatible

• Power dissipation 325 mW (typical)

• Low analog input capacitance (typical 2 pF), no buffer

amplifier required

• Integrated sample-and-hold amplifier

• Differential analog input

• External amplitude range control

• Voltage controlled regulator included.

TDA8765

APPLICATIONS

• High-speed analog-to-digital conversion for
– Video signal digitizing
– High Definition TV (HDTV)
– Imaging (camera scanner)
– Medical imaging
– Telecommunication
– Base-station receiver.

GENERAL DESCRIPTION

The TDA8765 is a bipolar 10-bit Analog-to-Digital
Converter (ADC) optimized for telecommunications and
professional imaging. It converts the analog input signal
into 10-bit binary coded digital words at a maximum
sampling rate of 55 MHz. All static digital inputs (SH,
and OTC) are TTL and CMOS compatible and all outputs
are CMOS compatible. A sine wave clock input signal can
also be used.

CE

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

INL integral non-linearity f
DNL differential non-linearity f
f

CLK(max)

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output supply voltage 3.0 3.3 5.25 V
analog supply current − 33 tbf mA
digital supply current − 30 tbf mA
output supply current f

= 4 MHz; fi= 400 kHz − 3.2 tbf mA

CLK

= 4 MHz; fi= 400 kHz −±0.5 ±1.75 LSB

CLK

= 4 MHz; fi= 400 kHz −±0.3 ±0.5 LSB

CLK

maximum clock frequency

TDA8765H/4 40 −−MHz
TDA8765H/5 55 −−MHz

P

tot

total power dissipation − 325 tbf mW

ORDERING INFORMATION

TYPE

NUMBER

TDA8765H/4
TDA8765H/5 55

NAME DESCRIPTION VERSION

QFP44

plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10 × 10 × 1.75 mm

PACKAGE

SOT307-2

SAMPLING

FREQUENCY (MHz)

40

1999 Jan 06 2

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

BLOCK DIAGRAM

V

V

V

handbook, full pagewidth

V

ref

V
V

SH

n.c.

V

CCA1

2

11

43

I

42

I

sample-

and-hold

39

1, 5 to 8,
12 to 14, 16, 31 and 32

CCA2

AMP

CCA3

3

9

TDA8765

ANALOG-TO-DIGITAL

CCA4

41

CONVERTER

CLK

35

CLK

CLOCK DRIVER

V

CCD1

36

LATCHES

OVERFLOW/

UNDERFLOW

LATCH

TDA8765

V

CCD2

37

15

OUTPUTS

OUTPUT

18

CMOS

CMOS

CEOTC

19

D9

21
22
23
24
25
26
27
28

29
30

33

20

D8
D7
D6
D5
D4
D3
D2
D1
D0

MSB

data outputs

LSB

V

CCO

IR

44

AGND1

10

AGND2

4

AGND3

40

AGND4

DGND1

Fig.1 Block diagram.

38

17

DGND2

34

MGK801

OGND

1999 Jan 06 3

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
V

CCA1

V

CCA3

AGND3 4 analog ground 3
n.c. 5 not connected
n.c. 6 not connected
n.c. 7 not connected
n.c. 8 not connected
V

CCA2

AGND2 10 analog ground 2
V

ref

n.c. 12 not connected
n.c. 13 not connected
n.c. 14 not connected
V

CCD2

n.c. 16 not connected
DGND2 17 digital ground 2
OTC

CE

IR 20 in-range output
D9 21 data output; bit 9 (MSB)
D8 22 data output; bit 8

2 analog supply voltage 1 (+5 V)
3 analog supply voltage 3 (+5 V)

9 analog supply voltage 2 (+5 V)

11 reference voltage input

15 digital supply voltage 2 (+5 V)

control input twos complement

18

output; active HIGH
chip enable input

19

(CMOS level; active LOW)

TDA8765

SYMBOL PIN DESCRIPTION

D7 23 data output; bit 7
D6 24 data output; bit 6
D5 25 data output; bit 5
D4 26 data output; bit 4
D3 27 data output; bit 3
D2 28 data output; bit 2
D1 29 data output; bit 1
D0 30 data output; bit 0 (LSB)
n.c. 31 not connected
n.c. 32 not connected
V

CCO

OGND 34 output ground
CLK

CLK 36 clock input
V

CCD1

DGND1 38 digital ground 1
SH 39 sample-and-hold enable input

AGND4 40 analog ground 4
V

CCA4

V

I

V

I

AGND1 44 analog ground 1

33 output supply voltage (3 to 5.25 V)

complementary clock input; active

35

LOW

37 digital supply voltage 1 (+5 V)

(CMOS level; active HIGH)

41 analog supply voltage 4 (+5 V)
42 positive analog input voltage
43 negative analog input voltage

1999 Jan 06 4

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

I

VIV

AGND1
44

43

42

n.c.

1
V
V

AGND3

V

AGND2

CCA1
CCA3

n.c.
n.c.

n.c.
n.c.

CCA2

V

ref

2

3

4

5

6

7

8

9

10
11

CCA4

AGND4

V

41

40

TDA8765H

SH
39

DGND1

V

38

CCD1

37

CLK
36

CLK

35

OGND
34

TDA8765

V

33

CCO

n.c.

32
31

n.c.
D0

30
29

D1

28

D2
D3

27
26

D4
D5

25
24

D6
D7

23

12
n.c.

13

14

15

16

17

n.c.

n.c.

CCD2

V

n.c.

DGND2

Fig.2 Pin configuration.

18

OTC

19
CE

20

21

22

IR

D9

D8

MGK800

1999 Jan 06 5

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital

TDA8765

Converter (ADC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V
∆V

V
V

I

O

T
T
T

CCA
CCD
CCO

CC

I
i(p-p)

stg
amb
j

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output supply voltage note 1 −0.3 +7.0 V
supply voltage difference

− V

V
V
V

CCA
CCD
CCA

− V

− V

CCD
CCO
CCO

input voltage at pins 42 and 43 referenced to AGND 0.3 V
input voltage at pins 35 and 36 for

−1.0 +1.0 V

−1.0 +4.0 V

−1.0 +4.0 V

CCA

− V

CCD

differential clock drive (peak-to-peak
value)

output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 +85 °C
junction temperature − 150 °C

V
V

Note

1. The supply voltages V

CCA

, V

CCD

and V

may have any value between −0.3 and +7.0 V provided that the supply

CCO

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITION VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 75 K/W

1999 Jan 06 6

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital

TDA8765

Converter (ADC)

CHARACTERISTICS

V

CCA=V2

V

CCO=V33

V

CCA=VCCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Inputs

CLK
V

IL

V

IH

I

IL

I

IH

Z

i

C

i

∆V

OTC, SH AND CE (REFERENCED TO DGND); see Tables 2 and 3
V

IL

V

IH

I

IL

I

IH

V

AND V

I

I

IL

I

IH

R

i

C

i

V

I(CM)

to V44, V9to V10, V3to V4 and V41to V40= 4.75 to 5.25 V; V

to V34= 3.0 to 5.25 V; AGND and DGND shorted together; T

= 5 V and V

CCO

= 3.3 V, T

=25°C, V

amb

I(p-p)

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output supply voltage 3.0 3.3 5.25 V
analog supply current − 33 45 mA
digital supply current − 30 37 mA
output supply current f

= 4 MHz; fi= 400 kHz − 3.2 tbf mA

CLK

= 40 MHz;

f

CLK

fi= 4.43 MHz

AND CLK (REFERENCED TO DGND)

CLK(p-p)

LOW-level input voltage V
HIGH-level input voltage V
LOW-level input current V
HIGH-level input current V
input impedance f
input capacitance f
differential AC input voltage

for switching (V

CLK

− V

CLK

;

= 5 V; note 1 3.19 − 3.52 V

CCD

= 5 V; note 1 3.83 − 4.12 V

CCD

or V

CLK

or V

CLK

= 40 MHz 2 −−kΩ

CLK

= 40 MHz −−2pF

CLK

DC voltage level = 2.5 V 0.5 − 2.0 V

peak-to-peak value)

LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2.0 − V
LOW-level input current VIL= 0.8 V −20 −−µA
HIGH-level input current VIH= 2.0 V −−20 µA

(REFERENCED TO AGND; see Table 1); V

I

REF

LOW-level input current − 10 −µA
HIGH-level input current − 10 −µA
input resistance fi= 4.43 MHz 100 −−kΩ
input capacitance fi= 4.43 MHz −−2pF
common mode input voltage VI= VI; output code 511

V

CCA

V

CCA

V

CCA

to V38and V15to V17= 4.75 to 5.25 V;

= 0 to 85 °C; typical values measured at

− V

CCD=V37

amb

= 2.0 V and CL= 10 pF; unless otherwise specified.

I(p-p)

− 11 tbf mA

= 3.19 V −10 −−µA

CLK

= 3.83 V −−10 µA

CLK

CCD

=V

CCA

− 1.825 V

= 5 V tbf 3.6 tbf V
= 4.75 V tbf 3.35 tbf V
= 5.25 V tbf 3.85 tbf V

V

1999 Jan 06 7

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital

TDA8765

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Voltage controlled regulator input V

V
V

ref
I(p-p)

− V

full-scale fixed voltage V
input voltage amplitude

I(p-p)

(peak-to-peak value)

I

ref

input current at V

ref

Outputs (referenced to OGND)

D

IGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND)

V

OL

V

OH

I

o

LOW-level output voltage IOL=2mA 0 − 0.5 V
HIGH-level output voltage IOH= −0.4 mA V
output current in 3-state output level between 0.5 V

Switching characteristics

LOCK FREQUENCY f

C
f

CLK(min)

f

CLK(max)

minimum clock frequency SH = HIGH −−1 MHz

maximum clock frequency

; see Fig.5

CLK

TDA8765H/4 40 −−MHz
TDA8765H/5 55 −−MHz

t

CLKH

t

CLKL

clock pulse width HIGH 8.5 −−ns
clock pulse width LOW 8.5 −−ns

Analog signal processing; 50% clock duty factor; V

(referenced to AGND); note 2

ref

=5V − 3.175 − V

CCA

V

ref=VCCA

and V

− 1.825 V − 2.0 − V

CCO

SH = LOW −−1 kHz

− VI= 2.0 V; V

I

− 0.5 10 µA

− 0.5 − V

CCO

−20 − +20 µA

ref=VCCA

− 1.825 V; see Table 1

CCO

V

INEARITY

L
INL integral non-linearity f

DNL differential non-linearity f

= 4 MHz; fi= 400 kHz −±0.5 ±1.75 LSB

CLK

= 4 MHz; fi= 400 kHz;

CLK

−±0.3 ±0.5 LSB

no missing code

E

offset

offset error V

CCA=VCCD=VCCO

T

=25°C; VI= VI;

amb

=5V;

tbf −11 tbf mV

output code = 511

E

G

BANDWIDTH (f

gain error amplitude; spread
from device to device

= 55 MHz); note 3

CLK

V

CCA=VCCD=VCCO

T

=25°C;

amb

V

I(p-p)

− V

I(p-p)

= 2.0 V

=5V;

−5 − +5 %FS

B analog bandwidth −3 dB; full-scale input tbf 200 − MHz

1999 Jan 06 8

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital

TDA8765

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

HARMONICS (f
H

fund(FS)

H

tot(FS)

THD total harmonic distortion f
THERMAL NOISE
N

th(rms)

SPURIOUS FREE DYNAMIC RANGE
DR

sf

SIGNAL-TO-NOISE RATIO; note 5
S/N signal-to-noise ratio without harmonics;

EFFECTIVE NUMBER OF BITS; see Figs 3 and 4 and note 5
N

bit

INTERMODULATION; note 6
TTIR two-tone intermodulation

d

3

BIT ERROR RATE
BER bit error rate f

= 40 MHz)

CLK

fundamental harmonics

fi= 4.43 MHz −−0dB

(full scale)
harmonics (full scale);

fi= 4.43 MHz

all components

second harmonic −−75 − dB
third harmonic −−70 − dB

= 4.43 MHz; note 4 −−66 − dB

i

thermal noise (RMS value) grounded input;

f

= 40 MHz

CLK

− 0.2 tbf LSB

spurious free dynamic range fi= 4.43 MHz tbf 71 − dB

f

= 10 MHz tbf 68 − dB

i

f

= 20 MHz tbf 67 − dB

i

− 59 − dB

= 40 MHz;

f

CLK

fi= 4.43 MHz

effective number of bits
TDA8765H/4
(f

= 40 MHz)

CLK

effective number of bits
TDA8765H/5
(f

= 55 MHz)

CLK

fi= 4.43 MHz 9.0 9.6 − bits
f

=10MHz − 9.6 − bits

i

f

=15MHz − 9.5 − bits

i

fi= 4.43 MHz − 9.6 − bits
f

=10MHz − 9.4 − bits

i

=15MHz − 9.3 − bits

f

i

=20MHz − 9.1 − bits

f

i

f

= 40 MHz tbf 66 − dB

CLK

rejection
third-order intermodulation

f

= 40 MHz tbf 67 − dB

CLK

distortion

= 40 MHz;

CLK

− 10

−15

tbf times/
fi= 4.43 MHz;
VI= ±16 LSB at code 511

sample

1999 Jan 06 9

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital

TDA8765

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing (C

t

d(s)

t

h

t

d

3-state output delay times; see Fig.6
t

dZH

t

dZL

t

dHZ

t

dLZ

Notes

1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:
a) PECL mode 1 (DC level varies equal to DC level of V
b) PECL mode 2 (DC level varies equal to DC level of V

c) PECL mode 3 (DC level varies equal to DC level of V

d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with

2. It is possible with an external reference connected to pin V
referenced to V

3. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
full-scale sine wave.

4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
THD 20log

where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.

5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all
harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:
SNR = N

6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6dB
below full scale for each input signal).
d3 is the ratio of the RMS-value of either input tone to the RMS-value of the worst case third order intermodulation
product.

7. Output data acquisition: the output data is available after the maximum delay of td.

= 10 pF); see Fig.5 and note 7

L

sampling delay time −−2ns
output hold time 4 −−ns
output delay time V

= 5.25 V − 10 15 ns

CCO

V

= 3.0 V − 13 18 ns

CCO

enable HIGH − 14 18 ns
enable LOW − 16 20 ns
disable HIGH − 16 20 ns
disable LOW − 14 18 ns

): CLK and CLK inputs are at differential PECL levels.

CCD

): CLK input is at PECL level and sampling is taken on

CCD

the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.

): CLK input is at PECL level and sampling is taken on

CCD

the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.

a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.

to adjust the ADC input range. This voltage has to be

ref

. For V

CCA

---------------------------------------------------------------------------------------------------------------=
(2nd)2(3rd)2(4th)2(5th)2(6th)

× 6.02 + 1.76 dB.

bit

− 1.825 V, the differential input voltage amplitude is 2 V (p-p).

CCA

F

++++

2

1999 Jan 06 10

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital

TDA8765

Converter (ADC)

Table 1 Output coding with differential inputs (typical values to AGND); V

CODE V

Underflow <3.1 >4.1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

0 3.1 4.1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 00
1 −−1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1

↓−−↓ ↓ ↓

511 3.6 3.6 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

↓−−↓ ↓ ↓

1022 −−1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0
1023 4.1 3.1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

Overflow >4.1 <3.1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

Table 2 Mode selection

OTC

i(p-p)

0 0 binary; active
1 0 twos complement; active

(1)

X

V

i(p-p)

IR

CE D0 TO D9 AND IR

1 high impedance

BINARY OUTPUTS

D9 TO D0 D9 TO D0

i(p-p)

− V

i(p-p)

= 2.0 V; V

ref=VCCA

TWOS COMPLEMENT

OUTPUTS

− 1.825 V

Note

1. X = don’t care.

Table 3 Sample-and-hold selection

SH SAMPLE-AND-HOLD

1 active
0 inactive; tracking mode

1999 Jan 06 11

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

0

amplitude

(dB)

−20

−40

−60

−80

−100

−120

−140

−160

0 5 10 15

Effective bits: 9.68; THD = −70.8 dB.
Harmonic levels (dB): 2nd = −80.3; 3rd = −74.5; 4th = −87.7; 5th = −76.4; 6th = −78.6.

f (MHz)

TDA8765

MGL430

20

Fig.3 Typical fast Fourier transform (f

handbook, full pagewidth

0

amplitude

(dB)

−20

−40

−60

−80

−100

−120

−140

−160

0 5 10 15

Effective bits: 9.12; THD = −62.5 dB.
Harmonic levels (dB): 2nd = −73.0; 3rd = −63.4; 4th = −80.9; 5th = −78.1; 6th = −74.4.

= 40 MHz; fi= 4.43 MHz).

CLK

f (MHz)

MGL431

2520

Fig.4 Typical fast Fourier transform (f

1999 Jan 06 12

= 50 MHz; fi= 21.4 MHz).

CLK

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

t

CLKH

t

d(s)

t

CLKL

handbook, full pagewidth

CLK

V

I

DATA

D0 to D9

sample N

DATA

N − 2

sample N + 1

DATA

N − 1

TDA8765

HIGH
50%
LOW

sample N + 2

t

h

DATA

N

t

d

DATA

N + 1

HIGH
50%
LOW

MBH427

handbook, full pagewidth

fCE= 100 kHz.

V

CCD

CE

output
data

output
data

0 V

LOW

t

dLZ

10 %

TDA8765

CE

Fig.5 Timing diagram.

HIGH

t

dZL

HIGH

50 %

3.3 kΩ

15 pF

t

dHZ

90 %

S1

LOW

V

CCD

50 %

t

dZH

50 %

TEST

t

dLZ

t

dZL

t

dHZ

t

dZH

S1

V

CCD

V

CCD
DGND
DGND

MBH423

Fig.6 Timing diagram and test conditions of 3-state output delay time.

1999 Jan 06 13

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

APPLICATION INFORMATION

handbook, full pagewidth

IN

220 nF

100 Ω

1 : 1

V

I

100 Ω

V

I

V

CCA

R1

5 V

10 nF4.7 µF

R2

5 V

100 nF

V

ref

100 nF

100 nF

(3)

n.c.

n.c.
n.c.
n.c.
n.c.

5 V5 V SH

100 nF

44 43 42 41 40 39 38 37 36 35 34

1
2

3
4
5
6
7
8
9
10
11

12

13 14 15 16 17 18 19 20 21 22

mode

TDA8765

100 nF

TDA8765

CLK

(1)

CLK

5 V

33
32
31
30
29
28
27
26
25
24
23

100 nF

n.c
n.c.
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7

n.c.

n.c. n.c.

n.c.

5 V

The analog, digital and output supplies should be separated and decoupled.
(1) Single-ended clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain a middle voltage of 3.6 V; see common mode input voltage.

In addition, the minimum current into these resistors should be about 1 mA in order to ensure a sufficient analog input stability.

must be decoupled to V

(3) V

ref

CCA

.

100 nF

IR

D8

D9

(MSB)

chip select input
output format select

Fig.7 Application diagram.

MGK802

1999 Jan 06 14

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

22

Z

E

TDA8765

SOT307-2

e

w M

b

p

pin 1 index

44

1

w M

b

0.25

p

D

H

0.40

0.20

D

D

0.25

10.1

0.14

9.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

12

11

Z

D

B

v M

0 2.5 5 mm

scale

(1)

(1) (1)(1)

eH

H

D

10.1

9.9

12.9

0.8 1.3

12.3

v M

H

E

A

B

E

12.9

12.3

E

LL

0.95

0.55

A

p

A

2

A

1

detail X

Z

D

0.15 0.10.15

1.2

0.8

(A )

3

L

p

L

Zywv θ

E

1.2

0.8

θ

o

10

o

0

OUTLINE

VERSION

SOT307-2

IEC JEDEC EIAJ

REFERENCES

1999 Jan 06 15

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

TDA8765

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Jan 06 16

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital

TDA8765

Converter (ADC)

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)
(5)

SOLDERING METHOD

(1)

suitable

suitable
suitable

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Jan 06 17

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

NOTES

1999 Jan 06 18

Philips Semiconductors Preliminary specification

10-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8765

NOTES

1999 Jan 06 19

Philips Semiconductors – a worldwide company

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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Uruguay: see South America
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1999 SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545104/750/02/pp20 Date of release: 1999Jan 06 Document order number: 9397 750 04716