Datasheet TDA8763AM-5-C4, TDA8763AM-5-C3, TDA8763AM-4-C4, TDA8763AM-4-C3, TDA8763AM-4-C1 Datasheet (Philips)

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Page 1
DATA SH EET
Product specification Supersedes data of 1997 Feb 07 File under Integrated Circuits, IC02
1999 Jan 06
INTEGRATED CIRCUITS
TDA8763A
Page 2
1999 Jan 06 2
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
FEATURES
10-bit resolution
Sampling rate up to 50 MHz
DC sampling allowed
One clock cycle conversion only
High signal-to-noise ratio over a large analog input
frequency range (9.4 effective bits at 4.43 MHz full-scale input at f
clk
= 40 MHz)
No missing codes guaranteed
In-Range (IR) CMOS output
Levels TTL and CMOS compatible digital inputs
3 to 5 V CMOS digital outputs
Low-level AC clock input signal allowed
External reference voltage regulator
Power dissipation only 175 mW (typical)
Low analog input capacitance, no buffer amplifier
required
No sample-and-hold circuit required.
APPLICATIONS
High-speed analog-to-digital conversion for:
Video data digitizing
Radar pulse analysis
Transient signal analysis
High energy physics research
•Σ∆ modulators
Medical imaging.
GENERAL DESCRIPTION
The TDA8763A is a 10-bit high-speed low-power analog-to-digital converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz. All digital inputs and outputs are TTL and CMOS compatible, although a low-level sine wave clock input signal is allowed.
The device requires an external source to drive its reference ladder. If the application requires that the reference is driven via internal sources the recommendation is to use the TDA8763.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
SAMPLING
FREQUENCY (MHz)
NAME DESCRIPTION VERSION
TDA8763AM/3 SSOP28
plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1 30 TDA8763AM/4 SSOP28 SOT341-1 40 TDA8763AM/5 SSOP28 SOT341-1 50
Page 3
1999 Jan 06 3
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CCA
analog supply voltage 4.75 5.0 5.25 V
V
CCD
digital supply voltage 4.75 5.0 5.25 V
V
CCO
output stages supply voltage 3.0 3.3 5.25 V
I
CCA
analog supply current 18 24 mA
I
CCD
digital supply current 16 21 mA
I
CCO
output stages supply current f
clk
= 40 MHz; ramp input 12mA
INL integral non-linearity f
clk
= 40 MHz; ramp input −±0.8 ±2.0 LSB
DNL differential non-linearity f
clk
= 40 MHz; ramp input −±0.5 ±0.9 LSB
f
clk(max)
maximum clock frequency
TDA8763AM/3 30 −−MHz TDA8763AM/4 40 −−MHz TDA8763AM/5 50 −−MHz
P
tot
total power dissipation f
clk
= 40 MHz; ramp input 175 247 mW
Page 4
1999 Jan 06 4
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
12 DGND2
6
8
R
LAD
7
9
V
RB
V
RM
V
RT
V
I
11
V
CCD2
3
26
V
CCA
21
22
23
24
20 D4
D5
D6
D7
D8
19 18
25
2
D3
D2 17 D1 16 D0
D9
IN-RANGE LATCH
CMOS
OUTPUTS
LATCHES
ANALOG -TO - DIGITAL
CONVERTER
CLOCK DRIVER
MBG913
CMOS OUTPUT
1
CLK
10
OE
TC
TDA8763A
13
V
CCO
4 AGND
analog ground digital ground digital ground
27 DGND1
14
OGND
output ground
analog
voltage input
data outputs
LSB
MSB
28
V
CCD1
IR output
Page 5
1999 Jan 06 5
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
PINNING
SYMBOL PIN DESCRIPTION
CLK 1 clock input TC 2 twos complement input (active LOW) V
CCA
3 analog supply voltage (+5 V) AGND 4 analog ground n.c. 5 not connected V
RB
6 reference voltage BOTTOM input V
RM
7 reference voltage MIDDLE input V
I
8 analog input voltage V
RT
9 reference voltage TOP input OE 10 output enable input (CMOS level
input, active LOW)
V
CCD2
11 digital supply voltage 2 (+5 V) DGND2 12 digital ground 2 V
CCO
13 supply voltage for output stages
(3 to 5 V) OGND 14 output ground n.c. 15 not connected D0 16 data output; bit 0 (LSB) D1 17 data output; bit 1 D2 18 data output; bit 2 D3 19 data output; bit 3 D4 20 data output; bit 4 D5 21 data output; bit 5 D6 22 data output; bit 6 D7 23 data output; bit 7 D8 24 data output; bit 8 D9 25 data output; bit 9 (MSB) IR 26 in range data output DGND1 27 digital ground 1 V
CCD1
28 digital supply voltage 1 (+5 V)
Fig.2 Pin configuration.
andbook, halfpage
handbook, halfpage
1 2 3 4 5 6 7 8
9 10 11 12 13
28 27 26 25 24 23 22 21 20 19 18 17 16 1514
CLK
TC
CCA
AGND
n.c.
RB
RM
I
RT
OE
CCD2
DGND2
CCO
OGND
CCD1 DGND1 IR
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 n.c.
V
V
V
V
V
V
V
V
TDA8763A
MBG914
Page 6
1999 Jan 06 6
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. The supply voltages V
CCA
, V
CCD
and V
CCO
may have any value between 0.3 V and +7.0 V provided that the supply
voltage differences VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CCA
analog supply voltage note 1 0.3 +7.0 V
V
CCD
digital supply voltage note 1 0.3 +7.0 V
V
CCO
output stages supply voltage note 1 0.3 +7.0 V
V
CC
supply voltage difference
V
CCA
V
CCD
1.0 +1.0 V
V
CCA
V
CCO
1.0 +4.0 V
V
CCD
V
CCO
1.0 +4.0 V
V
I
input voltage referenced to AGND 0.3 +7.0 V
V
i(sw)(p-p)
AC input voltage for switching (peak-to-peak value) referenced to DGND V
CCD
V
I
O
output current 10 mA
T
stg
storage temperature 55 +150 °C
T
amb
operating ambient temperature 40 +85 °C
T
j
junction temperature 150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-a)
thermal resistance from junction to ambient in free air 110 K/W
Page 7
1999 Jan 06 7
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
CHARACTERISTICS
V
CCA=V3
to V4= 4.75 to 5.25 V; V
CCD=V11
to V12and V28to V27= 4.75 to 5.25 V; V
CCO=V13
to V14= 3.0 to 5.25 V;
AGND and DGND shorted together; T
amb
=0to+70°C; typical values measured at V
CCA=VCCD
= 5 V and
V
CCO
= 3.3 V; V
i(p-p)
= 2.0 V; CL= 15 pF and T
amb
=25°C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
CCA
analog supply voltage 4.75 5.0 5.25 V
V
CCD1
digital supply voltage 1 4.75 5.0 5.25 V
V
CCD2
digital supply voltage 2 4.75 5.0 5.25 V
V
CCO
output stages supply voltage 3.0 3.3 5.25 V
V
CC
supply voltage difference
V
CCA
V
CCD
0.20 +0.20 V
V
CCA
V
CCO
0.20 +2.25 V
V
CCD
V
CCO
0.20 +2.25 V
I
CCA
analog supply current 18 24 mA
I
CCD
digital supply current 16 21 mA
I
CCO
output stages supply current f
clk
= 40 MHz; ramp input 12 mA
Inputs
C
LOCK INPUT CLK (REFERENCED TO DGND); note 1
V
IL
LOW-level input voltage 0 0.8 V
V
IH
HIGH-level input voltage 2.0 V
CCD
V
I
IL
LOW-level input current V
clk
= 0.8 V 10+1µA
I
IH
HIGH-level input current V
clk
= 2.0 V 210 µA
Z
i
input impedance f
clk
= 40 MHz 2 k
C
i
input capacitance 2 pF INPUTS OE AND TC (REFERENCED TO DGND); see Table 2 V
IL
LOW-level input voltage 0 0.8 V V
IH
HIGH-level input voltage 2.0 V
CCD
V
I
IL
LOW-level input current VIL= 0.8 V 1 −− µA I
IH
HIGH-level input current VIH= 2.0 V −−1µA V
I
(ANALOG INPUT VOLTAGE REFERENCED TO AGND)
I
IL
LOW-level input current VI=VRB= 1.3 V 0 −µA I
IH
HIGH-level input current VI=VRT= 3.67 V 35 −µA Z
i
input impedance fi= 4.43 MHz 8 k C
i
input capacitance 5 pF Reference voltages for the resistor ladder see Table 1 V
RB
reference voltage BOTTOM 1.2 1.3 2.45 V V
RT
reference voltage TOP 3.2 3.67 V
CCA
0.8 V
V
diff
differential reference voltage
VRT− V
RB
2.0 2.37 3.0 V
I
ref
reference current VRT− VRB= 2.37 V 9.7 mA
Page 8
1999 Jan 06 8
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
R
lad
resistor ladder 245 −Ω TC
Rlad
temperature coefficient of the
resistor ladder
1860 ppm
456 m/K
V
offset(B)
offset voltage BOTTOM VRT− VRB= 2.37 V; note 2 175 mV V
offset(T)
offset voltage TOP VRT− VRB= 2.37 V; note 2 175 mV V
i(p-p)
analog input voltage
(peak-to-peak value)
note 3 1.70 2.02 2.55 V
Outputs
D
IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)
V
OL
LOW-level output voltage IOL= 1 mA 0 0.5 V V
OH
HIGH-level output voltage IOH= 1mA V
CCO
0.5 V
CCO
V
I
OZ
output current in 3-state mode 0.5 V < Vo<V
CCO
20 +20 µA
Switching characteristics
C
LOCK INPUT CLK; see Fig.4; note 1
f
clk(max)
maximum clock frequency
TDA8763AM/3 30 −− MHz TDA8763AM/4 40 −− MHz TDA8763AM/5 50 −− MHz
t
CPH
clock pulse width HIGH full effective bandwidth 8.5 −− ns t
CPL
clock pulse width LOW full effective bandwidth 5.5 −− ns
Analog signal processing
L
INEARITY
INL integral non-linearity f
clk
= 40 MHz; ramp input −±0.8 ±2.0 LSB
DNL differential non-linearity f
clk
= 40 MHz; ramp input −±0.5 ±0.9 LSB
E
offset
offset error middle code; VRB= 1.3 V;
VRT= 3.67 V
−±1−LSB
E
G
gain error (from device to
device) using external
reference voltage
VRB= 1.3 V; VRT= 3.67 V; note 4
−±0.1 %
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Page 9
1999 Jan 06 9
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
BANDWIDTH (f
clk
= 40 MHz)
B analog bandwidth full-scale sine wave;
note 5
15 MHz
75% full-scale sine wave; note 5
20 MHz
small signal at mid-scale; V
I
= ±10 LSB at code 512;
note 5
350 MHz
t
stLH
analog input settling time
LOW-to-HIGH
full-scale square wave; see Fig.6; note 6
1.5 3.0 ns
t
stHL
analog input settling time
HIGH-to-LOW
full-scale square wave; see Fig.6; note 6
1.5 3.0 ns
HARMONICS (f
clk
=40MHZ); see Figs 7 and 8
H
fund(FS)
fundamental harmonics
(full-scale)
fi= 4.43 MHz −−0dB
H
all(FS)
harmonics (full-scale); all
components
fi= 4.43 MHz
second harmonics −−75 65 dB third harmonics −−72 65 dB
THD total harmonic distortion f
i
= 4.43 MHz −−64 dB SIGNAL-TO-NOISE RATIO; see Figs 7 and 8; note 7 SNR
FS
signal-to-noise ratio (full-scale) without harmonics;
f
clk
= 40 MHz;
fi= 4.43 MHz
55 58 dB
EFFECTIVE BITS; see Figs 7 and 8; note 7 EB effective bits TDA8763AM/3;
f
clk
= 30 MHz
f
i
= 4.43 MHz 9.4 bits
f
i
= 7.5 MHz 9.1 bits
TDA8763AM/4; f
clk
= 40 MHz
f
i
= 4.43 MHz 9.4 bits
f
i
= 7.5 MHz 9.0 bits
f
i
= 10 MHz 8.9 bits
f
i
= 15 MHz 8.1 bits
TDA8763AM/5; f
clk
= 50 MHz
f
i
= 4.43 MHz 9.3 bits
f
i
= 7.5 MHz 8.9 bits
f
i
= 10 MHz 8.8 bits
f
i
= 15 MHz 8.0 bits
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Page 10
1999 Jan 06 10
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 1023: a) V
offset(B)
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00
and the reference voltage BOTTOM (VRB) at T
amb
=25°C.
b) V
offset(T)
(voltage offset TOP) is the difference between reference voltage TOP (VRT) and the analog input which
produces data outputs equal to code 1023 at T
amb
=25°C.
T
WO-TONE; note 8
TTIR two-tone intermodulation
rejection
f
clk
= 40 MHz −−69 dB
BIT ERROR RATE BER bit error rate f
clk
= 50 MHz; fi= 4.43 MHz; VI= ±16 LSB at code 512
10
13
times/
sample
DIFFERENTIAL GAIN; note 9 G
diff
differential gain f
clk
= 40 MHz; PAL modulated ramp
0.8 %
DIFFERENTIAL PHASE; note 9
ϕ
diff
differential phase f
clk
= 40 MHz; PAL modulated ramp
0.4 deg
Timing (f
clk
= 40 MHz; CL= 15 pF); see Fig.4; note 10
t
ds
sampling delay time 3 ns
t
h
output hold time 4 −− ns
t
d
output delay time V
CCO
= 4.75 V 10 13 ns
V
CCO
= 3.15 V 12 15 ns
C
L
digital output load capacitance −−15 pF 3-state output delay times; see Fig.5 t
dZH
enable HIGH 5.5 8.5 ns t
dZL
enable LOW 12 15 ns t
dHZ
disable HIGH 19 24 ns t
dLZ
disable LOW 12 15 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Page 11
1999 Jan 06 11
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins V
RB
and VRT via offset resistors ROB and ROT as shown in Fig.3.
a) The current flowing into the resistor ladder is and the full-scale input range at the converter,
to cover code 0 to code 1023, is
b) Since R
L
, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
will be kept reasonably constant from device to device. Consequently variation of the output
codes at a given input voltage depends mainly on the difference V
RT
VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized.
4.
5. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data.
7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = ENOB × 6.02 + 1.76 dB.
8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.
9. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a digital-to-analog converter.
10. Output data acquisition: the output data is available after the maximum delay time of t
d(max)
. For 50 MHz version it is
recommended to have the lowest possible output load.
I
L
VRTVRB–
R
OBRLROT
++
------------------------------------------
=
V
IRLIL
×
R
L
R
OBRLROT
++
------------------------------------------
== V(
RT
× VRB– )+ 0.˙852 V(
RTVRB
)×=
RL
ROB RL ROT++
------------------------------------------------
E
G
V
1023V0
()V
ip p()
V
ip p()
----------------------------------------------------------- -
100×=
Fig.3 Explanation of note 3.
handbook, halfpage
R
LAD
R
OT
V
RT
V
RM
V
RB
R
OB
code 1023
code 0
MGD281
I
L
R
L
Page 12
1999 Jan 06 12
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB= 1.3 V, VRT= 3.67 V)
Table 2 Mode selection
STEP V
i(p-p)
IR
BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
U/F <1.475 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0000000
0 1.475 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0000000 1 . 100000000011000000001
. . .....................
. . .....................
1022 . 111111111100111111110 1023 3.495 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1111111
O/F >3.495 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1111111
TC OE D9 to D0 IR
X 1 high impedance high impedance 0 0 active; twos complement active 1 0 active; binary active
Fig.4 Timing diagram.
handbook, full pagewidth
ds
t
sample N + 1
sample N
CLK
MBG916
sample N + 2
0 V
50%
V
CCO
0 V
50%
V
CCO
V
l
DATA D0 to D9
t
d
t
h
CPH
t
CPL
t
DATA
N + 1
DATA
N
DATA
N - 1
DATA
N - 2
Page 13
1999 Jan 06 13
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
Fig.5 Timing diagram and test conditions of 3-state output delay time.
fOE= 100kHz.
handbook, full pagewidth
MGD262
50%
50%
HIGH
LOW
dZH
t
dHZ
t
50%
HIGH
LOW
dZL
t
dLZ
t
10%
90%
output data
V
CCD
output data
3.3 k
15 pF
S1
V
CCD
TDA8763A
OE
OE
TEST
dLZ
t
dZL
t
dHZ
t
dZH
S1
CCD
V
CCD
V
DGND DGND
t
Fig.6 Analog input settling time diagram.
MBE566
50%
STLH
t
2 ns
code 0
code 1023
I
50%
0.5 ns
50%
2 ns
STHL
t
50%
0.5 ns
CLK
V
Page 14
1999 Jan 06 14
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
Fig.7 Typical Fast Fourier Transform (f
clk
= 40 MHz; fi= 4.43 MHz).
Effective bits: 9.42; THD= 71.8 dB.
Harmonic levels (dB): 2nd = 83.19; 3rd = 78.09; 4th = 78.72; 5th = 78.33; 6th = 77.55.
handbook, full pagewidth
0
120
140
0 2.50 5.00
MGD862
40
80
12.57.50 10.0 15.0 17.5 20.0 f (MHz)
100
20
60
amplitude
(dB)
Fig.8 Typical Fast Fourier Transform (f
clk
= 50 MHz; fi= 10 MHz).
Effective bits: 8.91; THD = 62.96 dB. Harmonic levels (dB): 2nd = 71.38; 3rd = 71.54; 4th = 74.14; 5th = 65.15; 6th = 77.16.
handbook, full pagewidth
0
120
140
0 2.50 5.00
MGD863
40
80
12.57.50 10.0 15.0 17.5 25.020.0 22.5 f (MHz)
100
20
60
amplitude
(dB)
Page 15
1999 Jan 06 15
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
INTERNAL PIN CONFIGURATIONS
Fig.9 CMOS data and in range outputs.
handbook, halfpage
MBG915
V
CCO
OGND
D9 to D0
IR
Fig.10 Analog inputs.
handbook, halfpage
MGC040 - 1
AGND
V
CCA
V
I
Fig.11 OE and TC input.
handbook, halfpage
MBE557
V
CCO
OGND
OE TC
Fig.12 VRB, VRM and VRT.
handbook, halfpage
R
MGD232
V
RB
V
RM
V
CCA
AGND
V
RT
LAD
Page 16
1999 Jan 06 16
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
Fig.13 CLK input.
handbook, halfpage
1.5 V
V
CCD
DGND
CLK
MBE559 - 1
Page 17
1999 Jan 06 17
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
APPLICATION INFORMATION
Fig.14 Application diagram.
The analog and digital supplies should be separated and well decoupled. An application note is available and describes the design and the realization of a demonstration board that uses the version TDA8768AM with an
application environment. (1) V
RB
, VRM and VRT are decoupled to AGND. (2) Pin 15 may be connected to DGND in order to prevent noise influence. (3) Decoupling capacitor for supplies; must be placed close to the device.
handbook, full pagewidth
28
27
26
25
24
23
22
21
20
19
18
17
TDA8763A
DGND1
V
CCO
D3
D4
D5
D6
D7
D8
D9
D2
D1
D0
V
CCD2
V
CCA
1
2
3
4
5
6
7
8
9
10
11
12
CLK
AGND
n.c.
n.c.
V
RB
V
RM
V
RT
MBG918
16
15
13
14
100 nF
100 nF
DGND2
OGND
IR
OE
TC
V
CCD1
AGND
AGND
100 nF
AGND
V
I
(1)
(1)
(1)
(2)
100 nF
(3)
100 nF
(3)
100 nF
(3)
100 nF
(3)
Page 18
1999 Jan 06 18
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
PACKAGE OUTLINE
UNIT A
1
A2A
3
b
p
cD
(1)E(1) (1)
eHELLpQZywv θ
REFERENCES
OUTLINE VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
0.65 1.25
7.9
7.6
0.9
0.7
1.1
0.7
8 0
o o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
1.03
0.63
SOT341-1 MO-150AH
93-09-08 95-02-04
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
114
28 15
0.25
y
pin 1 index
0 2.5 5 mm
scale
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
A
max.
2.0
Page 19
1999 Jan 06 19
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
SOLDERING Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011). There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically developed.
If wave soldering is used the following conditions must be observed for optimal results:
Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
Page 20
1999 Jan 06 20
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
PACKAGE
SOLDERING METHOD
WAVE REFLOW
(1)
BGA, SQFP not suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable
(2)
suitable
PLCC
(3)
, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
(3)(4)
suitable
SSOP, TSSOP, VSO not recommended
(5)
suitable
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Page 21
1999 Jan 06 21
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
NOTES
Page 22
1999 Jan 06 22
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
NOTES
Page 23
1999 Jan 06 23
Philips Semiconductors Product specification
10-bit high-speed low-power ADC TDA8763A
NOTES
Page 24
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Philips Semiconductors – a worldwide company
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Printed in The Netherlands 545004/750/03/pp24 Date of release: 1999 Jan 06 Document order number: 9397 750 04693
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