Datasheet TDA8762AM-8-C1, TDA8762AM-6-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1995 April 27
File under Integrated Circuits, IC02

1996 Mar 21

INTEGRATED CIRCUITS

TDA8762A

10-bit high-speed low-power
analog-to-digital converter

1996 Mar 21 2

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

FEATURES

• 10-bit resolution

• Sampling rate up to 80 MHz

• DC sampling allowed

• One clock cycle conversion only

• High signal-to-noise ratio over a large analog input

frequency range (9.3 effective bits at 4.43 MHz
full-scale input at f

clk

= 80 MHz)

• No missing codes guaranteed

• In range (IR) TTL output

• TTL compatible digital inputs and outputs

• Low-level AC clock input signal allowed

• External reference voltage regulator

• Power dissipation only 380 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

APPLICATIONS

High-speed analog-to-digital conversion for:

• Video data digitizing

• Radar pulse analysis

• Transient signal analysis

• High energy physics research

•Σ∆ modulators

• Medical imaging.

GENERAL DESCRIPTION

The TDA8762A is a 10-bit high-speed analog-to-digital
converter (ADC) for professional video and other
applications. It converts the analog input signal into 10-bit
binary-coded digital words at a maximum sampling rate of
80 MHz. All digital inputs and outputs are TTL compatible,
although a low-level sine wave clock input signal is
allowed.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.4 5.0 5.25 V

I

CCA

analog supply current − 29 36 mA

I

CCD

digital supply current − 24 30 mA

I

CCO

output stages supply current CL= 15 pF; ramp input − 23 30 mA

INL integral non-linearity f

clk

= 80 MHz; ramp input −±0.75 ±1.5 LSB

DNL differential non-linearity f

clk

= 80 MHz; ramp input −±0.3 ±0.7 LSB

f

clk(max)

maximum clock frequency

TDA8762AM/6 60 −−MHz
TDA8762AM/8 80 −−MHz

P

tot

total power dissipation − 380 500 mW

TYPE

NUMBER

PACKAGE

SAMPLING

FREQUENCY (MHz)

NAME DESCRIPTION VERSION

TDA8762AM/6 SSOP28

plastic shrink small outline package; 28 leads;
body width 5.3 mm

SOT341-1 60

TDA8762AM/8 SSOP28 SOT341-1 80

1996 Mar 21 3

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

12
DGND

5

6

8

7

9

AGND2

V

RB

V

RM

V

RT

V

I

11

V

CCD

3

26

V

CCA

21

22

23

24

20 D4

D5

D6

D7

D8

19
18

25

2

D3

D2
17 D1
16 D0

D9

IN RANGE LATCH

TTL OUTPUTSLATCHES

CLOCK DRIVER

MBE560

TTL OUTPUT

1

CLK

10

OE

TC

TDA8762A

13

V

CCO1

4
AGND1

analog grounds digital ground

27
OGND2

14
OGND1

output grounds

analog

voltage input

data outputs

LSB

MSB

28

V

CCO2

IR
output

R

LAD

ANALOG -TO - DIGITAL

CONVERTER

1996 Mar 21 4

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

PINNING

SYMBOL PIN DESCRIPTION

CLK 1 clock input
TC 2 two’s complement input (active LOW)
V

CCA

3 analog supply voltage (5 V)
AGND1 4 analog ground 1
AGND2 5 analog ground 2
V

RB

6 reference voltage BOTTOM input
V

RM

7 reference voltage MIDDLE
V

I

8 analog input voltage
V

RT

9 reference voltage TOP input
OE 10 output enable input

(TTL level input, active LOW)

V

CCD

11 digital supply voltage (5 V)
DGND 12 digital ground
V

CCO1

13 supply voltage for output stages 1

(5 V)
OGND1 14 output ground 1
n.c. 15 not connected
D0 16 data output; bit 0 (LSB)
D1 17 data output; bit 1
D2 18 data output; bit 2
D3 19 data output; bit 3
D4 20 data output; bit 4
D5 21 data output; bit 5
D6 22 data output; bit 6
D7 23 data output; bit 7
D8 24 data output; bit 8
D9 25 data output; bit 9 (MSB)
IR 26 in range data output
OGND2 27 output ground 2
V

CCO2

28 supply voltage for output stages 2

(5 V)

Fig.2 Pin configuration.

handbook, halfpage

1
2
3
4
5
6
7
8

9
10
11
12
13

28
27
26
25
24
23
22
21

20
19
18
17
16
1514

CLK

TC

CCA

AGND1
AGND2

RB

RM

I

RT

OE

CCD

DGND

CCO1

OGND1

CCO2
OGND2
IR

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
n.c.

V

V

V

V

V

V

V

V

TDA8762A

MBE561

1996 Mar 21 5

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

CCA

, V

CCD

and V

CCO

may have any value between −0.3 and +7.0 V provided that the supply

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage note 1 −0.3 +7.0 V

V

CCD

digital supply voltage note 1 −0.3 +7.0 V

V

CCO

output stages supply voltage note 1 −0.3 +7.0 V

∆V

CC

supply voltage difference

V

CCA

− V

CCD

−1.0 +1.0 V

V

CCA

− V

CCO

−1.0 +1.0 V

V

CCD

− V

CCO

−1.0 +1.0 V

V

I

input voltage referenced to AGND −0.3 +7.0 V

V

clk(p-p)

AC input voltage for switching
(peak-to-peak value)

referenced to DGND − V

CCD

V

I

O

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature 0 +70 °C

T

j

junction temperature − +150 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 110 K/W

1996 Mar 21 6

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

CHARACTERISTICS

V

CCA=V3

to V4and V5= 4.75 to 5.25 V; V

CCD=V11

to V12= 4.75 to 5.25 V; V

CCO=V13

and V28to V14 and

V27= 4.4 to 5.25 V; AGND and DGND shorted together; T

amb

= 0 to +70 °C; typical values measured at

V

CCA=VCCD=VCCO

=5V; V

I(p-p)

= 2.0 V; CL= 15 pF and T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.4 5.0 5.25 V

∆V

CC

voltage difference

V

CCA

− V

CCD

−0.25 − +0.25 V

V

CCA

− V

CCO

−0.4 − +0.4 V

V

CCD

− V

CCO

−0.4 − +0.4 V

I

CCA

analog supply current − 29 36 mA

I

CCD

digital supply current − 24 30 mA

I

CCO

output stages supply current CL= 15 pF; ramp input − 23 30 mA

Inputs

C

LOCK INPUT CLK (REFERENCED TO DGND); note 1

V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current V

clk

= 0.4 V −10 +1 µA

I

IH

HIGH level input current V

clk

= 2.7 V −−20 µA

Z

I

input impedance f

clk

= 80 MHz − 2 − kΩ

C

I

input capacitance f

clk

= 80 MHz − 2 − pF
INPUTS OE AND TC (REFERENCED TO DGND); see Table 2
V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current VIL= 0.4 V −400 −− µA

I

IH

HIGH level input current VIH= 2.7 V −−20 µA
VI(ANALOG INPUT VOLTAGE REFERENCED TO AGND)
I

IL

LOW level input current VI= 1.3 V − 0 −µA
I

IH

HIGH level input current VI= 3.8 V − 70 −µA
Z

I

input impedance fi= 4.43 MHz − 5 − kΩ
C

I

input capacitance fi= 4.43 MHz − 8 − pF

1996 Mar 21 7

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

Reference voltages for the resistor ladder; see Table 1
V

RB

reference voltage BOTTOM 1.2 1.3 − V
V

RT

reference voltage TOP − 3.8 V

CCA

− 0.8 V V

V

diff

differential reference voltage

VRT− V

RB

1.8 2.5 3.0 V

I

ref

reference current − 28 − mA
R

LAD

resistor ladder − 90 −Ω
TC

RLAD

temperature coefficient of the

resistor ladder

− 1860 − ppm
167 mΩ/K

V

osB

offset voltage BOTTOM note 2 − 220 − mV

V

osT

offset voltage TOP note 2 − 220 − mV

V

I(p-p)

analog input voltage
(peak-to-peak value)

note 3 1.5 2.06 2.5 V

Outputs

D

IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)

V

OL

LOW level output voltage IO= 1 mA 0 − 0.4 V

V

OH

HIGH level output voltage IO= 0 mA 2.7 − V

CCO

− 0.5 V

I

O

= −0.4 mA 2.7 − V

CCO

− 1.3 V

I

O

= −1 mA 2.4 − V

CCO

− 1.4 V

I

OZ

output current in 3-state mode 0.4 V < VO<V

CCO

−20 − +20 µA

Switching characteristics

C

LOCK INPUT CLK; see Fig.4; note 1

f

clk(max)

maximum clock frequency

TDA8762A/6 60 −− MHz
TDA8762A/8 80 −− MHz

t

CPH

clock pulse width HIGH 5 −− ns

t

CPL

clock pulse width LOW 5 −− ns

Analog signal processing

L

INEARITY

INL integral non-linearity f

clk

= 80 MHz; ramp input −±0.75 ±1.5 LSB

DNL differential non-linearity f

clk

= 80 MHz; ramp input −±0.3 ±0.7 LSB

OFER offset error middle code; V

RB

= 1.3 V;

VRT= 3.8 V

−±1− LSB

GER gain error (from device to device) V

RB

= 1.3 V; VRT= 3.8 V;

note 4

−±0.1 − %

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Mar 21 8

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

BANDWIDTH (f

clk

= 80 MHz)

B analog bandwidth full-scale sine wave; note 5 − 40 − MHz

75% full-scale sine wave;
note 5

− 55 − MHz

small signal at mid-scale;
V

I

= ±10 LSB at code 512;

note 5

− 700 − MHz

t

STLH

analog input settling time
LOW-to-HIGH

full-scale square wave;
see Fig.6; note 6

− 2.0 3 ns

t

STHL

analog input settling time
HIGH-to-LOW

full-scale square wave;
see Fig.6; note 6

− 2.5 3.5 ns

HARMONICS (f

clk

=80MHZ)

h

1

fundamental harmonics (full scale) fi= 4.43 MHz −−0dB

h

all

harmonics (full scale);
all components

fi= 4.43 MHz

second harmonics −−70 62 dB
third harmonics −−75 67 dB

THD total harmonic distortion f

i

= 4.43 MHz −−68 − dB
SIGNAL-TO-NOISE RATIO; see Fig.8; note 7
S/N signal-to-noise ratio (full scale) without harmonics;

f

clk

= 80 MHz;

fi= 4.43 MHz

56 58 − dB

EFFECTIVE BITS; see Figs 7, 8 and 9; note 7
EB effective bits

TDA8762AM/6 f

clk

= 60 MHz

f

i

= 4.43 MHz − 9.35 − bits

f

i

= 10 MHz − 9.0 − bits

f

i

= 20 MHz − 8.1 − bits

TDA8762AM/8 f

clk

= 80 MHz

f

i

= 4.43 MHz − 9.3 − bits

f

i

= 10 MHz − 8.9 − bits

f

i

= 20 MHz − 8.0 − bits
TWO-TONE; note 8
TTIR two-tone intermodulation rejection f

clk

= 80 MHz −−68 − dB
BIT ERROR RATE
BER bit error rate f

clk

= 80 MHz;

fi= 4.43 MHz;
VI= ±16 LSB at code 512

− 10

−13

− times/

sample

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Mar 21 9

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.

2. Analog input voltages producing code 0 up to and including code 1023:
a) V

osB

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

the reference voltage BOTTOM (VRB) at T

amb

=25°C.

b) V

osT

(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

produces data outputs equal to code 1023 at T

amb

=25°C.

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.

a) The current flowing into the resistor ladder is IL= and the full-scale input range at the converter,

to cover code 0 to code 1023, is .

b) Since R

L

, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

will be kept reasonably constant from part to part. Consequently variation of the output codes

at a given input voltage depends mainly on the difference V

RT

− VRB and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.

4.

D

IFFERENTIAL GAIN; note 9

G

diff

differential gain f

clk

= 80 MHz;

PAL modulated ramp

− 0.5 − %

DIFFERENTIAL PHASE; note 9

ϕ

diff

differential phase f

clk

= 80 MHz;

PAL modulated ramp

− 0.5 − deg

Timing (f

clk

= 80 MHz; CL= 15 pF); see Fig.4; note 10

t

ds

sampling delay time −−2ns

t

h

output hold time 5 −− ns

t

d

output delay time − 913 ns

C

L

digital output load capacitance − 15 20 pF
3-state output delay times; see Fig.5
t

dZH

enable HIGH − 45 50 ns
t

dZL

enable LOW − 25 35 ns
t

dHZ

disable HIGH − 12 15 ns
t

dLZ

disable LOW − 12 15 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

RTVRB

–

R

OBRLROT

++

------------------------------------------

V

I

RLIL×

R

L

R

OBRLROT

++

------------------------------------------

V

RTVRB

–()0.824 VRTVRB–()×=×==

R

L

R

OBRLROT

++

-----------------------------------------

GER

V

1023V0

–()2V–
2V

------------------------------------------------

100×=

1996 Mar 21 10

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

5. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.

6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.

7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.

9. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.

10. Output data acquisition: the output data is available after the maximum delay time of td. In the event of a 80 MHz
clock operation, the hardware design must take into account the td and th limits with respect to the input
characteristics of the acquisition circuit; an external latch will ease the design if output data lines cannot be short to
minimize capacitance.

Fig.3 Explanation of note 3.

handbook, halfpage

R

LAD

R

OT

V

RT

V

RM

V

RB

R

OB

code 1023

code 0

7

6

9

MGD281

I

L

R

L

1996 Mar 21 11

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB= 1.3 V, VRT= 3.8 V)

Table 2 Mode selection

STEP V

I(p-p)

IR

BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

U/F <1.52 0 00000000001000000000
0 1.52 1 00000000001000000000
1 . 100000000011000000001

. . .....................

. . .....................

1022 . 111111111100111111110
1023 3.58 1 11111111110111111111
O/F >3.58 0 11111111110111111111

TC OE D9 TO D0 IR

X 1 high impedance high impedance
0 0 active; two’s complement active
1 0 active; binary active

Fig.4 Timing diagram.

handbook, full pagewidth

ds

t

sample N + 1

sample N

CLK

MGC037

sample N + 2

1.4 V

V

l

DATA
D0 to D9

t

d

t

h

CPH

t

CPL

t

2.4 V

0.4 V

1.4 V

DATA

N + 1

DATA

N

DATA

N - 1

DATA

N - 2

1996 Mar 21 12

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

Fig.5 Timing diagram and test conditions of 3-state output delay time.

fOE= 100kHz.

handbook, full pagewidth

MBE562

50%

50%

HIGH

LOW

dZH

t

dHZ

t

50%

HIGH

LOW

dZL

t

dLZ

t

10%

90%

output
data

V

CCD

output
data

3.3 kΩ

15 pF

S1

V

CCD

TDA8762A

OE

OE

TEST

dLZ

t

dZL

t

dHZ

t

dZH

S1

CCD

V

CCD

V

GND
GND

t

1996 Mar 21 13

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

Fig.6 Analog input settling-time diagram.

MBE566

50%

STLH

t

2 ns

code 0

code 1023

I

50%

0.5 ns

50%

2 ns

STHL

t

50%

0.5 ns

CLK

V

Fig.7 Fast Fourier Transform (f

clk

= 80 MHz; fi= 4.43 MHz).

Effective bits: 9.35; THD =−71.18 dB;
Harmonic levels (dB): 2nd =−73.61; 3rd = −76.14; 4th = −83.82; 5th = −87.36; 6th = −86.33.

14.9

0

0 4.96 9.93 34.7 39.719.9 24.8 29.8

MBE567

−20

−40

−60

−80

−120

−100

A

(dB)

f (MHz)

1996 Mar 21 14

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

Fig.8 Fast Fourier Transform (f

clk

= 80 MHz; fi= 10 MHz).

Effective bits: 9.12; THD = −65.45 dB;
Harmonic levels (dB): 2nd = −79.52; 3rd = −66.03; 4th = −81.60; 5th = −77.47; 6th = −104.43.

15.0

0

0 5.01 10.0 35.1 40.120.1 25.1 30.1

MBE568

−20

−40

−60

−80

−120

−100

A

(dB)

f (MHz)

Fig.9 Fast Fourier Transform (f

clk

= 80 MHz; fi= 20 MHz).

Effective bits: 8.08; THD = −52.60 dB;
Harmonic levels (dB): 2nd = −58.35; 3rd = −54.22; 4th = −76.61; 5th = −66.90; 6th = −76.80.

15.1

0

0 5.02 10.0 35.2 40.220.1 25.1 30.1

MBE569

−20

−40

−60

−80

−120

−100

A

(dB)

f (MHz)

1996 Mar 21 15

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

INTERNAL PIN CONFIGURATIONS

Fig.10 TTL data and in-range outputs.

MBE563

OGND1

D9 to D0

IR

V

CCO1

V

CCO2

Fig.11 Analog inputs.

handbook, halfpage

MGC040 - 1

AGND

V

CCA

V

I

Fig.12 OE (TC) input.

handbook, halfpage

MGD344

OGND2

V

CCO1

(TC)

OE

Fig.13 VRB, VRM and VRT.

R

MBE565

V

RB

V

RM

V

CCA

AGND

V

RT

LAD

1996 Mar 21 16

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

Fig.14 CLK input.

handbook, halfpage

V

V

CCD

CLK

DGND

MGC042 - 1

ref

(1.3 V)

1996 Mar 21 17

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

APPLICATION INFORMATION

Fig.15 Application diagram.

The analog and digital supplies should be separated and decoupled.
The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value.

Eventually, the reference ladder voltages can be derived from a well regulated V

CCA

supply through a resistor bridge and a decoupled capacitor.
(1) VRB, VRM and VRT are decoupled to AGND.
(2) Pin 15 should be connected to DGND in order to prevent noise influence.
(3) When VRM is not used, pin 7 can be left open, avoiding the decoupling capacitor. In any case, this pin must not be grounded.
(4) When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 8).

handbook, full pagewidth

28

27

26

25

24

23

22

21

20

19

18

17

TDA8762A

OGND2

V

CCO1

D3

D4

D5

D6

D7

D8

D9

D2

D1

D0

V

CCD

V

CCA

1

2

3

4

5

6

7

8

9

10

11

12

CLK

AGND1

AGND2

n.c.

V

RB

V

RM

V

RT

MBE564

16

15

13

14

100 nF

100 nF

DGND

OGND1

IR

OE

TC

V

CCO2

AGND

AGND

100 nF

AGND

V

I

(1)

(3) (1)

(1)

(4)

(2)

1996 Mar 21 18

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

PACKAGE OUTLINE

UNIT A

1

A2A

3

b

p

cD

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

10.4

10.0

5.4

5.2

0.65 1.25

7.9

7.6

0.9

0.7

1.1

0.7

8
0

o
o

0.13 0.10.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

1.03

0.63

SOT341-1 MO-150AH

93-09-08
95-02-04

X

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

(A )

3

A

114

28 15

0.25

y

pin 1 index

0 2.5 5 mm

scale

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

SOT341-1

A

max.

2.0

1996 Mar 21 19

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Mar 21 20

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1996 Mar 21 21

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

NOTES

1996 Mar 21 22

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

NOTES

1996 Mar 21 23

Philips Semiconductors Product specification

10-bit high-speed low-power
analog-to-digital converter

TDA8762A

NOTES

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211,

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Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS:

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COPENHAGEN S, Tel. [phone], Fax. [phone]

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Indonesia: see Singapore
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Piazza IV Novembre 3, 20124 MILANO,
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TOKYO 108, Tel. [phone], Fax. [phone]

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Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO,

TEXAS 79905, Tel. [phone], Fax. [phone]

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC,
MAKATI, Metro MANILA,
Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

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CEP: 04552-903-SÃO PAULO-SP, Brazil,
P.O. Box 7383 (01064-970),
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-16485 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

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Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone]

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209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE,

2A Akademika Koroleva str., Office 165, 252148 KIEV,
Tel.[phone], Fax. [phone]

United Kingdom: Philips Semiconductors LTD.,

276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax. [phone]

Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Fax. [phone]

SCDS48 © Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

537021/1100/02/pp24 Date of release: 1996 Mar 21
Document order number: 9397 750 00751