Datasheet tda8762 DATASHEETS (Philips)

Page 1
INTEGRATED CIRCUITS
DATA SH EET
TDA8762
10-bit high-speed low-power analog-to-digital converter
Product specification Supersedes data of 1995 Feb 15 File under Integrated Circuits, IC02
1996 Mar 28
Page 2
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter

FEATURES

• 10-bit resolution
• Sampling rate up to 40 MHz
• DC sampling allowed
• One clock cycle conversion only
• High signal-to-noise ratio over a large analog input
frequency range (9.4 effective bits at 4.43 MHz full-scale input at f
• No missing codes guaranteed
• In range (IR) TTL output
• TTL compatible digital inputs and outputs
• Low-level AC clock input signal allowed
• External reference voltage regulator
• Power dissipation only 380 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
= 40 MHz)
clk
TDA8762

APPLICATIONS

High-speed analog-to-digital conversion for:
• Video data digitizing
• Radar pulse analysis
• Transient signal analysis
• High energy physics research
•Σ∆ modulators
• Medical imaging.

GENERAL DESCRIPTION

The TDA8762 is a 10-bit high-speed analog-to-digital converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
INL integral non-linearity f
analog supply voltage 4.75 5.0 5.25 V digital supply voltage 4.75 5.0 5.25 V output stages supply voltage 4.4 5.0 5.25 V analog supply current − 29 36 mA digital supply current − 24 30 mA output stages supply current − 23 30 mA
= 40 MHz;
clk
−±0.75 ±1.5 LSB
ramp input
DNL differential non-linearity f
= 40 MHz;
clk
−±0.3 ±0.7 LSB
ramp input
f
clk(max)
P
tot
maximum clock frequency 40 −−MHz total power dissipation − 380 500 mW

ORDERING INFORMATION

TYPE
NUMBER
NAME DESCRIPTION VERSION
TDA8762M/4 SSOP28 plastic shrink small outline package;
PACKAGE
SAMPLING
FREQUENCY (MHz)
SOT341-1 40
28 leads; body width 5.3 mm
1996 Mar 28 2
Page 3
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter

BLOCK DIAGRAM

handbook, full pagewidth
analog
voltage input
V
RT
V
V
RM
V
RB
V
CCA
3
9
R
LAD
I
8
7
6
ANALOG -TO - DIGITAL
CONVERTER
CLK
1
CLOCK DRIVER
IN RANGE LATCH
V
CCD
11
TDA8762
OE 10
TTL OUTPUTSLATCHES
TTL OUTPUT
2
25
D9
D8
24
D7
23
D6
22
D5
21 20 D4
19
D3
18
D2 17 D1 16 D0
V
13
28
V
26
TDA8762
TC
MSB
data outputs
LSB
CCO1
CCO2
IR output
4 AGND1
analog grounds digital ground
5 AGND2
12 DGND
Fig.1 Block diagram.
1996 Mar 28 3
14 OGND1
output grounds
27 OGND2
MGC035
Page 4
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter

PINNING

SYMBOL PIN DESCRIPTION
CLK 1 clock input TC 2 two’s complement input (active LOW) V
CCA
AGND1 4 analog ground 1 AGND2 5 analog ground 2 V
RB
V
RM
V
I
V
RT
OE 10 output enable input
V
CCD
DGND 12 digital ground V
CCO1
OGND1 14 output ground 1 n.c. 15 not connected D0 16 data output; bit 0 (LSB) D1 17 data output; bit 1 D2 18 data output; bit 2 D3 19 data output; bit 3 D4 20 data output; bit 4 D5 21 data output; bit 5 D6 22 data output; bit 6 D7 23 data output; bit 7 D8 24 data output; bit 8 D9 25 data output; bit 9 (MSB) IR 26 in range data output OGND2 27 output ground 2 V
CCO2
3 analog supply voltage (+5 V)
6 reference voltage BOTTOM input 7 reference voltage MIDDLE 8 analog input voltage 9 reference voltage TOP input
(TTL level input, active LOW)
11 digital supply voltage (+5 V)
13 supply voltage for output stages 1
(+5 V)
28 supply voltage for output stages 2
(+5 V)
handbook, halfpage
1
CLK
2
TC
V
3
CCA
V
RB
V
RM
V
RT OE
V
CCD
DGND
CCO1
4 5 6 7
I
8
9 10 11 12 13
TDA8762
MGC036
V
AGND1 AGND2
V
OGND1
Fig.2 Pin configuration.
TDA8762
V
28
CCO2
27
OGND2 IR
26 25
D9
24
D8
23
D7
22
D6 D5
21 20
D4 D3
19 18
D2
17
D1
16
D0
1514
n.c.
1996 Mar 28 4
Page 5
Philips Semiconductors Product specification
10-bit high-speed low-power
TDA8762
analog-to-digital converter

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CCA
V
CCD
V
CCO
∆V
V
I
V
clk(p-p)
I
O
T
stg
T
amb
T
j
CC
analog supply voltage note 1 −0.3 +7.0 V digital supply voltage note 1 −0.3 +7.0 V output stages supply voltage note 1 −0.3 +7.0 V supply voltage difference
V V V
CCA CCA CCD
− V
− V
− V
CCD CCO CCO
−1.0 +1.0 V
−1.0 +1.0 V
−1.0 +1.0 V
input voltage referenced to AGND −0.3 +7.0 V AC input voltage for switching
referenced to DGND − V
CCD
(peak-to-peak value) output current − 10 mA storage temperature −55 +150 °C operating ambient temperature 0 +70 °C junction temperature − +150 °C
V
Note
1. The supply voltages V
CCA
CCD
and V
may have any value between −0.3 V and +7.0 V provided that the supply
CCO
, V
voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air 110 K/W
1996 Mar 28 5
Page 6
Philips Semiconductors Product specification
10-bit high-speed low-power
TDA8762
analog-to-digital converter

CHARACTERISTICS

V
CCA=V3
V27= 4.4 to 5.25 V; AGND and DGND shorted together; T V
CCA=VCCD=VCCO
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply
V
CCA
V
CCD
V
CCO
∆V
I
CCA
I
CCD
I
CCO
Inputs
to V4and V5= 4.75 to 5.25 V; V
=5V; V
analog supply voltage 4.75 5.0 5.25 V digital supply voltage 4.75 5.0 5.25 V output stages supply voltage 4.4 5.0 5.25 V
CC
voltage difference
V
− V V V
CCA CCA CCD
− V
− V
CCD CCO CCO
analog supply current − 29 36 mA digital supply current − 24 30 mA output stages supply current CL= 15 pF; ramp input − 23 30 mA
CCD=V11
= 2.0 V; CL= 15 pF and T
I(p-p)
to V12= 4.75 to 5.25 V; V
= 0 to +70 °C; typical values measured at
amb
=25°C; unless otherwise specified.
amb
CCO=V13
and V28to V14 and
−0.25 − +0.25 V
−0.4 − +0.4 V
−0.4 − +0.4 V
LOCK INPUT CLK (REFERENCED TO DGND); note 1
C V
IL
V
IH
I
IL
I
IH
Z
I
C
I
LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current V HIGH level input current V input impedance f input capacitance f
clk clk
= 40 MHz − 2 − kΩ
clk
= 40 MHz − 2 − pF
clk
INPUTS OE AND TC (REFERENCED TO DGND); see Table 2 V
IL
V
IH
I
IL
I
IH
LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current VIL= 0.4 V −400 −− µA
HIGH level input current VIH= 2.7 V −−20 µA VI(ANALOG INPUT VOLTAGE REFERENCED TO AGND) I
IL
I
IH
Z
I
C
I
LOW level input current VI= 1.3 V − 0 −µA
HIGH level input current VI= 3.8 V − 70 −µA
input impedance fi= 4.43 MHz − 5 − kΩ
input capacitance fi= 4.43 MHz − 8 − pF
CCD
V = 0.4 V −10 +1 µA = 2.7 V −−20 µA
CCD
V
1996 Mar 28 6
Page 7
Philips Semiconductors Product specification
10-bit high-speed low-power
TDA8762
analog-to-digital converter
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for the resistor ladder; see Table 1
V
RB
V
RT
V
diff
I
ref
R
LAD
TC
RLAD
V
osB
V
osT
V
I(p-p)
Outputs
D
IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)
V
OL
V
OH
I
OZ
Switching characteristics
reference voltage BOTTOM 1.2 1.3 − V reference voltage TOP − 3.8 V differential reference voltage
VRT− V
RB
1.8 2.5 3.0 V
CCA
− 0.8 V V
reference current − 28 − mA resistor ladder − 90 −Ω temperature coefficient of the resistor
ladder
− 1860 − ppm
− 167 − mΩ/K
offset voltage BOTTOM note 2 − 220 − mV offset voltage TOP note 2 − 220 − mV analog input voltage
note 3 1.5 2.06 2.5 V
(peak-to-peak value)
LOW level output voltage IO= 1 mA 0 − 0.4 V HIGH level output voltage IO= 0 mA 2.7 − V
I
= −0.4 mA 2.7 − V
O
I
= −1 mA 2.4 − V
O
output current in 3-state mode 0.4 V < VO<V
CCO
−20 − +20 µA
CCO CCO CCO
− 0.5 V
− 1.3 V
− 1.4 V
LOCK INPUT CLK; see Fig.4; note 1
C f
clk(max)
t
CPH
t
CPL
maximum clock frequency 40 −− MHz clock pulse width HIGH 8 −− ns clock pulse width LOW 8 −− ns
Analog signal processing
INEARITY
L INL integral non-linearity f
= 40 MHz;
clk
ramp input
DNL differential non-linearity f
= 40 MHz;
clk
ramp input
OFER offset error middle code;
= 1.3 V; VRT= 3.8 V
V
RB
GER gain error (from device to device) V
= 1.3 V;
RB
VRT= 3.8 V; note 4
−±0.75 ±1.5 LSB
−±0.3 ±0.7 LSB
−±1− LSB
−±0.1 − %
1996 Mar 28 7
Page 8
Philips Semiconductors Product specification
10-bit high-speed low-power
TDA8762
analog-to-digital converter
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
BANDWIDTH (f B analog bandwidth full-scale sine wave;
t
STLH
t
STHL
HARMONICS (f h
1
h
all
THD total harmonic distortion f SIGNAL-TO-NOISE RATIO; see Fig.8; note 7 S/N signal-to-noise ratio (full scale) without harmonics;
EFFECTIVE BITS; see Figs 7, 8 and 9; note 7 EB effective bits f
TWO-TONE; note 8 TTIR two-tone intermodulation rejection f BIT ERROR RATE BER bit error rate f
= 40 MHz)
clk
− 40 − MHz
note 5 75% full-scale sine
− 55 − MHz
wave; note 5 small signal at
− 700 − MHz mid-scale; V
= ±10 LSB at
I
code 512; note 5
analog input settling time LOW-to-HIGH
analog input settling time HIGH-to-LOW
=40MHZ)
clk
full-scale square wave; Fig.6; note 6
full-scale square wave; Fig.6; note 6
− 2.0 3 ns
− 2.5 3.5 ns
fundamental harmonics (full scale) fi= 4.43 MHz −−0dB harmonics (full scale); all components fi= 4.43 MHz
second harmonics −−70 −62 dB third harmonics −−75 −67 dB
= 4.43 MHz −−70 − dB
i
57 59 − dB
= 40 MHz;
f
clk
fi= 4.43 MHz
= 40 MHz
clk
= 4.43 MHz − 9.4 − bits
f
i
f
= 7.5 MHz − 9.3 − bits
i
f
= 10 MHz − 9.0 − bits
i
f
= 15 MHz − 8.7 − bits
i
= 40 MHz −−70 − dB
clk
= 40 MHz;
clk
fi= 4.43 MHz;
− 10
−13
− times/
sample VI= ±16 LSB at code 512
1996 Mar 28 8
Page 9
Philips Semiconductors Product specification
10-bit high-speed low-power
TDA8762
analog-to-digital converter
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
D
IFFERENTIAL GAIN; note 9
G
diff
differential gain f
DIFFERENTIAL PHASE; note 9
ϕ
diff
Timing (f
t
ds
t
h
t
d
C
L
differential phase f
= 40 MHz; CL= 15 pF); see Fig.4; note 10
clk
sampling delay time −−2ns output hold time 5 −− ns output delay time − 10 14 ns
digital output load − 15 40 pF 3-state output delay times; see Fig.5 t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH − 45 50 ns
enable LOW − 25 35 ns
disable HIGH − 12 15 ns
disable LOW − 12 15 ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 1023: a) V
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
osB
the reference voltage BOTTOM (VRB) at T
b) V
(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
osT
produces data outputs equal to code 1023 at T
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.
= 40 MHz;
clk
PAL modulated ramp
= 40 MHz;
clk
PAL modulated ramp
=25°C.
amb
=25°C.
amb
− 0.5 − %
− 0.5 − deg
V
–
a) The current flowing into the resistor ladder is IL= and the full-scale input range at the converter,
to cover code 0 to code 1023, is . .
b) Since R
----------------------------------------­R
, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
L
R
L
++
OBRLROT
will be kept reasonably constant from part to part. Consequently variation of the output codes
RLIL×
V
I
at a given input voltage depends mainly on the difference V
RTVRB
-----------------------------------------­R
++
OBRLROT
R
-----------------------------------------­R
L
++
OBRLROT
− VRB and its variation with temperature and supply
RT
V
–()0.824 VRTVRB–()×=×==
RTVRB
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized.
V
–()2V–
4. .
GER
1023V0
-----------------------------------------------­2V
100×=
1996 Mar 28 9
Page 10
Philips Semiconductors Product specification
10-bit high-speed low-power
TDA8762
analog-to-digital converter
5. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data.
7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
9. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a digital-to-analog converter.
10. Output data acquisition: the output data is available after the maximum delay time of td.
handbook, halfpage
V
RT
R
OT
code 1023
R
L
V
RM
R
LAD
V
RB
I
L
R
OB
MGD281
code 0
Fig.3 Explanation of note 3.
1996 Mar 28 10
Page 11
Philips Semiconductors Product specification
10-bit high-speed low-power
TDA8762
analog-to-digital converter
Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB= 1.3 V, VRT= 3.8 V)
STEP V
I(p-p)
IR
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
U/F <1.52 0 00000000001000000000 0 1.52 1 00000000001000000000 1 . 100000000011000000001
. . .....................
. . .....................
1022 . 111111111100111111110 1023 3.58 1 11111111110111111111 O/F >3.58 0 11111111110111111111
Table 2 Mode selection
TC OE D9 TO D0 IR
X 1 high impedance high impedance 0 0 active; two’s complement active 1 0 active; binary active
BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS
handbook, full pagewidth
CLK
V
l
DATA D0 to D9
t
sample N
DATA
N - 2
t
CPL
CPH
sample N + 1
t
ds
DATA
N - 1
Fig.4 Timing diagram.
1.4 V
sample N + 2
t
h
DATA
N
t
d
DATA
N + 1
MGC037
2.4 V
1.4 V
0.4 V
1996 Mar 28 11
Page 12
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter
V
handbook, full pagewidth
CCD
OE
output data
output data
LOW
t
dLZ
10 %
TDA8762
OE
HIGH
TDA8762
50 %
LOW
V
S1
CCD
t
dZH
50 %
TEST
t
dLZ
t
dZL
t
dHZ
t
dZH
S1
V
CCD
V
CCD
GND GND
MGC038
t
dHZ
HIGH
t
dZL
50 %
3.3 kΩ
15 pF
90 %
fOE= 100 kHz.
Fig.5 Timing diagram and test conditions of 3-state output delay time.
1996 Mar 28 12
Page 13
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter
handbook, full pagewidth
code 1023
V
code 0
CLK
MGD345
I
50 %
2 ns
t
STLH
50 %
0.5 ns
2 ns
t
STHL
50 %
50 %
TDA8762
0.5 ns
Fig.6 Analog input settling-time diagram.
handbook, full pagewidth
0
A
(dB)
20
40
60
80
100
120
0 5 7.5 10 15 17.52.5 12.5
Effective bits: 9.46; THD = −71.19 dB; Harmonic levels (dB): 2nd = −79.70; 3rd = −72.84; 4th = −81.54; 5th = −83.93; 6th = −86.47.
MLC947
20
f (MHz)
Fig.7 Fast Fourier Transform (f
1996 Mar 28 13
= 40 MHz; fi= 4.43 MHz).
clk
Page 14
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter
handbook, full pagewidth
0
A
(dB)
20
40
60
80
100
120
0 5 7.5 10 15 17.52.5 12.5
Effective bits: 9.11; THD = −63.18 dB; Harmonic levels (dB): 2nd = −66.49; 3rd = −66.52; 4th = −85.15; 5th = −75.95; 6th = −83.47.
TDA8762
MLC948
f (MHz)
20
Fig.8 Fast Fourier Transform (f
handbook, full pagewidth
0
A
(dB)
20
40
60
80
100
120
0 5 7.5 10 15 17.52.5 12.5
Effective bits: 8.70; THD = −60.18 dB; Harmonic levels (dB): 2nd = −62.24; 3rd = −70.44; 4th = −77.29; 5th = −65.99; 6th = −89.67.
= 40 MHz; fi= 10 MHz).
clk
f (MHz)
MLC949
20
Fig.9 Fast Fourier Transform (f
1996 Mar 28 14
= 40 MHz; fi= 15 MHz).
clk
Page 15
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter

INTERNAL PIN CONFIGURATIONS

V
handbook, halfpage
CCO2
MGC039
V
CCO1
D9 to D0
IR
OGND1
handbook, halfpage
V
CCA
V
I
AGND
TDA8762
MGC040 - 1
Fig.10 TTL data and in-range outputs.
handbook, halfpage
V
CCO1
OE
(TC)
OGND2
MGD344
Fig.11 Analog inputs.
V
CCA
V
RT
V
RM
V
RB
AGND
R
LAD
MBE565
Fig.12 OE (TC) input.
1996 Mar 28 15
Fig.13 VRB, VRM and VRT.
Page 16
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter
handbook, halfpage
V
CCD
CLK
DGND
V
(1.3 V)
ref
MGC042 - 1
TDA8762
Fig.14 CLK input.
1996 Mar 28 16
Page 17
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter

APPLICATION INFORMATION

Additional application information will be supplied upon request (please quote number
handbook, halfpage
100 nF
100 nF
AGND
100 nF
AGND
AGND
AGND1
AGND2
(1)
(3)(1)
(1)
V
V
CLK
CCA
V
V
RM
(4)
V
CCD
TC
RB
RT
OE
1
2
3
4
5
6
7
V
I
TDA8762
8
9
10
11
28
27
26
25
24
23
22
21
20
19
18
V
CCO2
OGND2
IR
D9
D8
D7
D6
D5
D4
D3
D2
“AN96025”
TDA8762
).
DGND
12
V
CCO1
13
OGND1
14
The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value.
Eventually, the reference ladder voltages can be derived from a well regulated V (1) VRB, VRM and VRT are decoupled to AGND. (2) Pin 15 should be connected to DGND in order to prevent noise influence. (3) When VRM is not used, pin 7 can be left open, avoiding the decoupling capacitor. In any case, this pin must not be grounded. (4) When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 8).
supply through a resistor bridge and a decoupled capacitor.
CCA
MGC043
D1
17
D0
16
(2)
n.c.
15
Fig.15 Application diagram.
1996 Mar 28 17
Page 18
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter

PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
D
c
y
Z
28 15
TDA8762

SOT341-1

E
H
E
A
X
v M
A
pin 1 index
114
w M
b
e
DIMENSIONS (mm are the original dimensions)
UNIT A
mm
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
A
max.
2.0
1
0.21
0.05
A2A3b
1.80
0.25
1.65
0.38
0.25
p
cD
0.20
0.09
p
0 2.5 5 mm
scale
(1)E(1) (1)
10.4
10.0
eHELLpQZywv θ
5.4
0.65 1.25
5.2
7.9
7.6
Q
A
2
A
1
detail X
1.03
0.9
0.63
0.7
(A )
L
p
L
0.13 0.10.2
A
3
θ
1.1
0.7
o
8
o
0
OUTLINE VERSION
SOT341-1 MO-150AH
IEC JEDEC EIAJ
REFERENCES
1996 Mar 28 18
EUROPEAN
PROJECTION
ISSUE DATE
93-09-08 95-02-04
Page 19
Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in
“IC Package Databook”
our
Reflow soldering
Reflow soldering techniques are suitable for all SSOP packages.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
Wave soldering
Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
(order code 9398 652 90011).
TDA8762
If wave soldering cannot be avoided, the following conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering technique should be used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate solder thieves at the downstream end.
Even with these conditions, only consider wave soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
1996 Mar 28 19
Page 20
Philips Semiconductors Product specification
10-bit high-speed low-power
TDA8762
analog-to-digital converter

DEFINITIONS

Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Mar 28 20
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Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter
TDA8762
NOTES
1996 Mar 28 21
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Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter
TDA8762
NOTES
1996 Mar 28 22
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Philips Semiconductors Product specification
10-bit high-speed low-power analog-to-digital converter
TDA8762
NOTES
1996 Mar 28 23
Page 24
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SCDS48 © Philips Electronics N.V. 1996
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Printed in The Netherlands
537021/1100/02/pp24 Date of release: 1996 Mar 28 Document order number: 9397 750 00767
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