Datasheet TDA8761A Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8761A

9-bit analog-to-digital converter
for digital video

Preliminary specification
File under Integrated Circuits, IC02

1996 Feb 13

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter
for digital video

FEATURES

• 9-bit resolution

• Sampling rate up to 40 MHz

• DC sampling allowed

• One clock cycle conversion only

• High signal-to-noise ratio over a large analog input

frequency range (8.2 effective bits at 10 MHz full-scale
input at f

• No missing codes guaranteed

• In range (IR) CMOS output

• CMOS compatible digital inputs

• 3 to 5 V CMOS digital outputs

• Low-level AC clock input signal allowed

• External reference voltage regulator

• Power dissipation only 165 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

= 30 MHz)

clk

TDA8761A

APPLICATIONS

Analog-to-digital conversion for:

• Video data digitizing

• Digital Video Broadcasting (DVB)

• Cable TV.

GENERAL DESCRIPTION

The TDA8761A is a 9-bit analog-to-digital converter (ADC)
for professional video and digital video set box
applications. It converts the analog input signal into 9-bit
binary-coded digital words at a maximum sampling rate of
40 MHz. Its linearity performance ensures the required
conversion accuracy in the event of 256QAM demodulator
concept and for all symbol frequencies. All digital inputs
and outputs are CMOS compatible, although a low-level
sine wave clock input signal is allowed.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

INL integral non-linearity f

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 3.0 3.3 5.25 V
analog supply current − 18 tbf mA
digital supply current − 13 tbf mA
output stages supply current f

= 30 MHz; ramp input − 3 tbf mA

clk

= 30 MHz; ramp input −±0.8 tbf LSB

clk

AINL AC integral non-linearity full-scale input sine wave; note 1 −±0.75 tbf LSB

50% full-scale input sine wave; note 1 −±0.5 tbf LSB

DNL differential non-linearity f

= 30 MHz; ramp input −±0.3 ±0.7 LSB

clk

ADNL AC differential non-linearity full-scale input sine wave; note 1 −±0.5 tbf LSB

50% full-scale input sine wave; note 1 −±0.3 tbf LSB

f

clk(max)

P

tot

maximum clock frequency 40 −−MHz
total power dissipation − 165 tbf mW

Note

= 10 MHz and f

1. f

i

= 30 MHz; fi= 8 MHz and f

clk

= 20 MHz.

clk

1996 Feb 13 2

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter

TDA8761A

for digital video

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8761AM SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

BLOCK DIAGRAM

handbook, full pagewidth

analog

voltage input

V

RT

V

V

RM

V

CCA

3

9

R

LAD

I

8

7

ANALOG -TO - DIGITAL

CONVERTER

CLK

1

CLOCK DRIVER

PACKAGE

LATCHES

V

CCD2

11

TDA8761A

OE
10

CMOS

OUTPUTS

2

25

D8

D7

24

D6

23

D5

22

D4

21
20 D3

19

D2

18

D1

17 D0

TC

MSB

data outputs

LSB

V

6

RB

IN RANGE LATCH

4
AGND

analog ground digital grounds

12
DGND2

27
DGND1

Fig.1 Block diagram.

1996 Feb 13 3

14

OGND

output ground

CMOS OUTPUT

13

28
26

MBG910

V

CCO

V

CCD1



IR
output



Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter
for digital video

PINNING

SYMBOL PIN DESCRIPTION

CLK 1 clock input
TC 2 two’s complement input (active LOW)
V

CCA

AGND 4 analog ground
n.c. 5 not connected
V

RB

V

RM

V

I

V

RT

OE 10 output enable input (CMOS level

V

CCD2

DGND2 12 digital ground 2
V

CCO

OGND 14 output ground
n.c. 15 not connected
n.c. 16 not connected
D0 17 data output; bit 0 (LSB)
D1 18 data output; bit 1
D2 19 data output; bit 2
D3 20 data output; bit 3
D4 21 data output; bit 4
D5 22 data output; bit 5
D6 23 data output; bit 6
D7 24 data output; bit 7
D8 25 data output; bit 8 (MSB)
IR 26 in range data output
DGND1 27 digital ground 1
V

CCD1

3 analog supply voltage (+5 V)

6 reference voltage BOTTOM input
7 reference voltage MIDDLE
8 analog input voltage
9 reference voltage TOP input

input, active LOW)

11 digital supply voltage 2 (+5 V)

13 supply voltage for output stages

(+3 to 5 V)

28 digital supply voltage 1 (+5 V)

handbook, halfpage

1

CLK

2

TC

V

3

CCA

4

AGND

5

n.c.

V

6

RB

V

7

RM

V

RT

OE

V

CCD2

DGND2

V

CCO

OGND

V

I

TDA8761A

8

9
10
11
12
13

MBG909

Fig.2 Pin configuration.

TDA8761A

V

28

CCD1

27

DGND1
IR

26
25

D8

24

D7

23

D6

22

D5
D4

21
20

D3
D2

19
18

D1

17

D0

16

n.c.

1514

n.c.

1996 Feb 13 4

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter

TDA8761A

for digital video

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V
∆V

V
V

I

O

T
T
T

CCA
CCD
CCO

CC

I
i(p-p)

stg
amb
j

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output stages supply voltage note 1 −0.3 +7.0 V
supply voltage differences between

V
V
V

CCA
CCD
CCA

and V
and V
and V

CCD
CCO
CCO

−1.0 +1.0 V

−1.0 +4.0 V

−1.0 +4.0 V

input voltage referenced to AGND −0.3 +7.0 V
AC input voltage for switching

referenced to DGND − V

CCD

(peak-to-peak value)
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 +70 °C
junction temperature − +150 °C

V

Note

1. The supply voltages V

CCA

, V

CCD

and V

may have any value between −0.3 and +7.0 V provided that the supply

CCO

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 110 K/W

1996 Feb 13 5

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter

TDA8761A

for digital video

CHARACTERISTICS

V

CCA=V3

AGND and DGND shorted together; T
V

CCO

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply

V

CCA

V

CCD

V

CCO

∆V

I

CCA

I

CCD

I

CCO

Inputs

to V4= 4.75 to 5.25 V; V

= 3.3 V; V

i(p-p)

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 3.0 3.3 5.25 V

CC

supply voltage differences
between

V

CCA

V

CCA

V

CCD

analog supply current − 18 tbf mA
digital supply current − 13 tbf mA
output stages supply current f

CCD=V11

= 0 to +70 °C; typical values measured at V

amb

= 1.8 V; CL= 15 pF and T

and V

CCD

and V

CCO

and V

CCO

to V12and V28to V27= 4.75 to 5.25 V; V

=25°C; unless otherwise specified.

amb

CCO=V13
CCA=VCCD

to V14= 3.0 to 5.25 V;

= 5 V and

−0.2 − +0.2 V

−0.2 − +2.25 V

−0.2 − +2.25 V

= 30 MHz; ramp input − 3 tbf mA

clk

LOCK INPUT CLK (REFERENCED TO DGND); note 1

C
V

IL

V

IH

I

IL

I

IH

Z

i

C

i

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
LOW level input current V
HIGH level input current V
input impedance f
input capacitance f

= 0.3V

clk

= 0.7V

clk

=30MHz − 2 − kΩ

clk

=30MHz − 2 − pF

clk

INPUTS OE AND TC (REFERENCED TO DGND); see Table 2
V

IL

V

IH

I

IL

I

IH

V

(ANALOG INPUT VOLTAGE REFERENCED TO AGND)

I

I

IL

I

IH

Z

i

C

i

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
LOW level input current VIL= 0.3V
HIGH level input current VIH= 0.7V

LOW level input current VI=VRB= 1.3 V − 0 −µA
HIGH level input current VI=VRT= 3.43 V − 35 −µA
input impedance fi= 10 MHz − 8 − kΩ
input capacitance fi= 10 MHz − 5 − pF

CCD
CCD

CCD

CCD

V
V

CCD

− V

CCD

CCD

−10+1 µA

− 210 µA

V
V

CCD

− V

CCD

CCD

−1 −− µA

−−1 µA

1996 Feb 13 6

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter

TDA8761A

for digital video

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Reference voltages for the resistor ladder; see Table 1

V

RB

V

RT

V

diff

I

ref

R

LAD

TC

RLAD

V

osB

V

osT

V

i(p-p)

Outputs

IGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND)

D
V

OL

V

OH

I

OZ

Switching characteristics

reference voltage BOTTOM 1.2 1.3 2.45 V
reference voltage TOP 3.0 3.43 V
differential reference voltage

VRT− V

RB

1.8 2.13 3.0 V

− 0.8 V V

CCA

reference current VRT− VRB= 2.13 V − 8.7 − mA
resistor ladder − 245 −Ω
temperature coefficient of the

resistor ladder

− 1860 − ppm

− 456 − mΩ/K

offset voltage BOTTOM note 2 − 160 − mV
offset voltage TOP note 2 − 160 − mV
analog input voltage

note 3 1.5 1.81 2.5 V

(peak-to-peak value)

LOW level output voltage IOL= 1 mA 0 − 0.5 V
HIGH level output voltage IOH= −1mA V
output current in 3-state mode 0.5 V < VO<V

CCO

−0.5 − V

CCO

CCO

V

−20 − +20 µA

LOCK INPUT CLK; see Fig.4; note 1

C
f

clk(max)

t

CPH

t

CPL

maximum clock frequency 40 −− MHz
clock pulse width HIGH 10 −− ns
clock pulse width LOW 10 −− ns

Analog signal processing

INEARITY

L
INL integral non-linearity f

= 30 MHz; ramp input −±0.8 tbf LSB

clk

AINL AC integral non-linearity full-scale input sine

wave; note 5
50% full-scale input sine

wave; note 5

DNL differential non-linearity f

= 30 MHz; ramp input −±0.3 ±0.7 LSB

clk

ADNL AC differential non-linearity full-scale input sine

wave; note 5
50% full-scale input sine

wave; note 5

OFER offset error middle code;

= 1.3 V;

V

RB

VRT= 3.43 V

GER gain error (from device to device) V

RB

= 1.3 V;

VRT= 3.43 V; note 4

−±0.75 tbf LSB

−±0.5 tbf LSB

−±0.5 tbf LSB

−±0.3 tbf LSB

−±1− LSB

−±0.1 − %

1996 Feb 13 7

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter

TDA8761A

for digital video

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

BANDWIDTH (f
B analog bandwidth full-scale sine wave;

t

STLH

t

STHL

HARMONICS (f
THD total harmonic distortion f
SIGNAL-TO-NOISE RATIO; see Figs 7 and 8; note 8
S/N signal-to-noise ratio (full scale) without harmonics;

EFFECTIVE BITS; see Figs 7 and 8; note 8
EB effective bits f

TWO-TONE; note 9
TTIR two-tone intermodulation

BIT ERROR RATE
BER bit error rate f

DIFFERENTIAL GAIN; note 10
G

diff

DIFFERENTIAL PHASE; note 10

ϕ

diff

= 30 MHz)

clk

analog input settling time
LOW-to-HIGH

analog input settling time
HIGH-to-LOW

=30MHZ); see Figs 7 and 8

clk

rejection

differential gain f

differential phase f

− 10 − MHz

note 6
75% full-scale sine

− 14 − MHz

wave; note 6
small signal at mid-scale;

= ±10 LSB at

V

I

− 350 − MHz

code 256; note 6
full-scale square wave;

− 2.0 tbf ns

Fig.6; note 7
full-scale square wave;

− 2.5 tbf ns

Fig.6; note 7

= 10 MHz −−56 − dB

i

51 53 − dB

f

= 30 MHz;

clk

fi= 10 MHz

=30MHz

clk

= 4.43 MHz − 8.7 − bits

f

i

= 10 MHz − 8.2 − bits

f

i

f

=30MHz −−56 − dB

clk

= 30 MHz;

clk

− 10

−13

− times/

fi= 10 MHz;
VI= ±16 LSB at
code 256

= 30 MHz;

clk

− 0.5 − %

PAL modulated ramp

= 30 MHz;

clk

− 0.3 − deg

PAL modulated ramp

sample

1996 Feb 13 8

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter

TDA8761A

for digital video

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Timing (f

t

ds

t

h

t

d

C

L

3-state output delay times; see Fig.5
t

dZH

t

dZL

t

dHZ

t

dLZ

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.

2. Analog input voltages producing code 0 up to and including code 511:
a) V

b) V

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to
pins V

a) The current flowing into the resistor ladder is and the full-scale input range at the converter,

b) Since R

= 30 MHz; CL= 15 pF); see Fig.4; note 11

clk

sampling delay time −−2ns
output hold time 5 −− ns
output delay time V

= 4.75 V − 13 16 ns

CCO

= 3.15 V − 16 19 ns

V

CCO

digital output load − 15 40 pF

enable HIGH − 14 18 ns
enable LOW − 16 20 ns
disable HIGH − 16 20 ns
disable LOW − 14 18 ns

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

osB

the reference voltage BOTTOM (VRB) at T

(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

osT

produces data outputs equal to code 511 at T

and VRT via offset resistors ROB and ROT as shown in Fig.3.

RB

to cover code 0 to code 511, is

, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

L

R

----------------------------------------- ­R

L

++

OBRLROT

will be kept reasonably constant from device to device. Consequently variation of the output

RLIL×

V

== V

I

codes at a given input voltage depends mainly on the difference V

=25°C.

amb

=25°C.

amb

I

=

----------------------------------------- -

L

R

OBRLROT

----------------------------------------- ­R

++

OBRLROT

VRTVRB–

++

R

L

(× VRB)– 0.˙852 V(

RT

− VRB and its variation with temperature and

RT

RTVRB

)–×=

supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.

V

–()1.8 V–

GER

4.

= 10 MHz and f

5. f

i

511V0

---------------------------------------------------

1.8 V
= 30 MHz; fi= 8 MHz and f

clk

100×=

= 20 MHz.

clk

6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.

7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.

1996 Feb 13 9

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter

TDA8761A

for digital video

8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.10 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.

10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.

11. Output data acquisition: the output data is available after the maximum delay time of td.

handbook, halfpage

V

V

V

RT

RM

RB

9

R

OT

code 511

R

7

R

LAD

6

L

I

L

R

OB

MGD233

code 0

Fig.3 Explanation of note 3.

1996 Feb 13 10

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter

TDA8761A

for digital video

Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB= 1.3 V, VRT= 3.43 V)

STEP V

I(p-p)

IR

D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0

U/F <1.46 0 0 00000000000000000

0 1.46 1 0 00000000000000000
1 . 1000000001000000001

. . ...................

. . ...................

510 . 1111111111111111110
511 3.27 1 1 11111111111111111
O/F >3.27 0 1 11111111111111111

Table 2 Mode selection

TC OE D8 to D0 IR

X 1 high impedance high impedance

0 0 active; two’s complement active
1 0 active; binary active

BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS

handbook, full pagewidth

CLK

V

l

DATA
D0 to D8

t

sample N

DATA

N - 2

CPH

t

CPL

sample N + 1

t

ds

DATA

N - 1

t

Fig.4 Timing diagram.

V

CCD

50%
0 V

sample N + 2

t

h

V

DATA

N

d

DATA

N + 1

MBG908

CCO

50%
0 V

1996 Feb 13 11

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter
for digital video

V

handbook, full pagewidth

CCD

OE

output
data

output
data

LOW

t

10 %

TDA8761A

dLZ

OE

HIGH

TDA8761A

50 %

LOW

S1

V

CCD

t

dZH

50 %

TEST

t

dLZ

t

dZL

t

dHZ

t

dZH

S1

V

CCD

V

CCD

DGND
DGND

MBG907

t

dHZ

HIGH

t

dZL

50 %

3.3 kΩ

15 pF

90 %

fOE= 100 kHz.

handbook, full pagewidth

Fig.5 Timing diagram and test conditions of 3-state output delay time.

2 ns

t

STHL

50 %

50 %

0.5 ns

code 511

code 0

CLK

MGC359

t

STLH

V

I

50 %

2 ns

50 %

0.5 ns

Fig.6 Analog input settling-time diagram.

1996 Feb 13 12

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter
for digital video

amplitude

(dB)

100

120

0

20

40

60

80

0 1.25 2.50

handbook, full pagewidth

TDA8761A

MBG912

6.263.76 5.01 7.51 8.77 10.0
f (MHz)

Effective bits: 8.70; THD = −68.68 dB.
Harmonic levels (dB): 2nd = −78.40; 3rd = −72.08; 4th = −75.85 dB; 5th = −76.26; 6th = −80.23.

amplitude

(dB)

100

120

0

20

40

60

80

0 1.87 3.75

handbook, full pagewidth

Fig.7 Typical Fast Fourier Transform (f

clk

= 30 MHz; fi= 4.43 MHz).

9.375.62 7.50 11.2 13.1 15.0
f (MHz)

MBG911

Effective bits: 8.25; THD = −56.72 dB.
Harmonic levels (dB): 2nd = −62.21; 3rd = −58.58; 4th = −80.29; 5th = −71.71; 6th = −72.04.

Fig.8 Typical Fast Fourier Transform (f

1996 Feb 13 13

= 30 MHz; fi= 10 MHz).

clk

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter
for digital video

INTERNAL PIN CONFIGURATIONS

handbook, halfpage

MGD231

V

CCO

D8 to D0

IR

OGND

handbook, halfpage

V

CCA

V

I

AGND

TDA8761A

MGC040 - 1

Fig.9 CMOS data and in range outputs.

handbook, halfpage

V



OGND

CCO

OE

(TC)

MBE557

handbook, halfpage

V

AGND

Fig.10 Analog inputs.

CCA

V

RT

V

RM

V

RB

R

LAD

MGD232

Fig.11 OE (TC) input.

1996 Feb 13 14

Fig.12 VRB, VRM and VRT.

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter
for digital video

handbook, halfpage

V

CCD

CLK

DGND

1/2V

CCD

MBE559 - 1

TDA8761A

Fig.13 CLK input.

1996 Feb 13 15

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter
for digital video

APPLICATION INFORMATION

handbook, halfpage

100 nF

AGND

100 nF

AGND

100 nF

AGND

CLK

V

CCA

AGND

V

V

V

V

CCD2

TC

n.c.

RB

RM

RT

OE

TDA8761A

V

1

2

3

4

5

(1)

6

(1)

7

I

10

11

TDA8761A

8

9

V

(1)

28

27

26

25

24

23

22

21

20

19

18

CCD1

DGND1

IR

D8

D7

D6

D5

D4

D3

D2

D1

DGND2

12

V

CCO

13

OGND

14

The analog and digital supplies should be separated and decoupled.
The external voltage regulator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the

reference ladder voltages can be derived from a well regulated V
(1) VRB, VRM and VRT are decoupled to AGND.
(2) Pins 15 and 16 should be connected to DGND in order to prevent noise influence.

supply through a resistor bridge and a decoupled capacitor.

CCA

MBG906

D0

17

(2)

n.c.

16

(2)

n.c.

15

Fig.14 Application diagram.

1996 Feb 13 16

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter
for digital video

PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

D

c

y

Z

28 15

TDA8761A

SOT341-1

E

H

E

A

X

v M

A

pin 1 index

114

w M

b

e

DIMENSIONS (mm are the original dimensions)

UNIT A

mm

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

A

max.

2.0

1

0.21

0.05

A2A3b

1.80

0.25

1.65

0.38

0.25

p

cD

0.20

0.09

p

0 2.5 5 mm

scale

(1)E(1) (1)

10.4

10.0

eHELLpQZywv θ

5.4

0.65 1.25

5.2

7.9

7.6

Q

A

2

A

1

detail X

0.9

1.03

0.7

0.63

(A )

L

p

L

0.13 0.10.2

A

3

θ

1.1

0.7

o

8

o

0

OUTLINE

VERSION

SOT341-1 MO-150AH

IEC JEDEC EIAJ

REFERENCES

1996 Feb 13 17

EUROPEAN

PROJECTION

ISSUE DATE

93-09-08
95-02-04

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter
for digital video

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering isnot recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

(order code 9398 652 90011).

TDA8761A

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Feb 13 18

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter

TDA8761A

for digital video

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Feb 13 19

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

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th

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Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCDS47 © Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

537021/1100/01/pp20 Date of release: 1996 Feb 13
Document order number: 9397 750 00636