Datasheet tda8761 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8761

9-bit analog-to-digital converter for
digital video

Preliminary specification
File under Integrated Circuits, IC02

Philips Semiconductors

1995 Mar 20

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

FEATURES

• 9-bit resolution

• Sampling rate up to 30 MHz

• DC sampling allowed

• One clock cycle conversion only

• High signal-to-noise ratio over a large analog input

frequency range (8.5 effective bits at 10 MHz full-scale
input at f

• No missing codes guaranteed

• In range (IR) 3-state TTL output

• TTL compatible digital inputs and outputs

• Low-level AC clock input signal allowed

• External reference voltage regulator

• Power dissipation only 360 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

= 30 MHz)

clk

TDA8761

APPLICATIONS

Analog-to-digital conversion for:

• Video data digitizing

• Digital Video Broadcasting (DVB)

• Cable TV.

GENERAL DESCRIPTION

The TDA8761 is a 9-bit analog-to-digital converter (ADC)
for professional video and digital video set box
applications. It converts the analog input signal into 9-bit
binary-coded digital words at a maximum sampling rate of
30 MHz. Its linearity performance ensures the required
conversion accuracy in case of 256QAM demodulator
concept and for all symbol frequencies. All digital inputs
and outputs are TTL compatible, although a low-level sine
wave clock input signal is allowed.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.4 5.0 5.25 V
analog supply current − 30 tbf mA
digital supply current − 22 tbf mA
output stages supply current − 22 tbf mA

AINL AC integral non-linearity note 1; full scale input sine wave −±0.75 tbf LSB

note 1; 50% full scale input sine wave −±0.5 tbf LSB

ADNL AC differential non-linearity note 1; full scale input sine wave −±0.5 tbf LSB

note 1; 50% full scale input sine wave −±0.3 tbf LSB

f

clk(max)

P

tot

maximum clock frequency 30 −−MHz
total power dissipation − 360 tbf mW

Note

= 11 MHz and f

1. f

i

= 30 MHz; fi= 8 MHz and f

clk

= 20 MHz.

clk

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8761M SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

1995 Mar 20 2

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

BLOCK DIAGRAM

handbook, full pagewidth

analog

voltage input

V

RT

V

V

RM

V

CCA

3

CLOCK DRIVER

9

I

8

7

ANALOG -TO - DIGITAL

CONVERTER

CLK

1

V

CCD

11

TDA8761

TTL OUTPUTSLATCHES

CE
10

2

25

D8

D7

24

D6

23

D5

22

D4

21
20 D3

19

D2

18

D1

17 D0

TDA8761

TC

MSB

data outputs

LSB

V

6

RB

4
AGND1

analog grounds digital ground

5
AGND2

12
DGND

IN RANGE LATCH

Fig.1 Block diagram.

TTL OUTPUT

14
OGND1

output grounds

27
OGND2

13

28
26

MGC355

V

CCO1

V

CCO2

IR
output

1995 Mar 20 3

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

PINNING

SYMBOL PIN DESCRIPTION

CLK 1 clock input
TC 2 two’s complement input (active LOW)
V

CCA

AGND1 4 analog ground 1
AGND2 5 analog ground 2
V

RB

V

RM

V

I

V

RT

CE 10 chip enable input (TTL level input,

V

CCD

DGND 12 digital ground
V

CCO1

OGND1 14 output ground 1
n.c. 15 not connected
n.c. 16 not connected
D0 17 data output; bit 0 (LSB)
D1 18 data output; bit 1
D2 19 data output; bit 2
D3 20 data output; bit 3
D4 21 data output; bit 4
D5 22 data output; bit 5
D6 23 data output; bit 6
D7 24 data output; bit 7
D8 25 data output; bit 8 (MSB)
IR 26 in range data output
OGND2 27 output ground 2
V

CCO2

3 analog supply voltage (+5 V)

6 reference voltage BOTTOM input
7 reference voltage MIDDLE
8 analog input voltage
9 reference voltage TOP input

active LOW)

11 digital supply voltage (+5 V)

13 supply voltage for output stages 1

(+5 V)

28 supply voltage for output stages 2

(+5 V)

handbook, halfpage

1

CLK

2

TC

V

3

CCA

V

RB

V

RM

V

RT
CE

V

CCD

DGND

CCO1

4
5
6
7

I

8

9
10
11
12
13

TDA8761

MGC356

V

AGND1
AGND2

V

OGND1

Fig.2 Pin configuration.

TDA8761

V

28

CCO2

27

OGND2
IR

26
25

D8

24

D7

23

D6

22

D5
D4

21
20

D3
D2

19
18

D1

17

D0

16

n.c.

1514

n.c.

1995 Mar 20 4

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for

TDA8761

digital video

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V
∆V

V
V

I

O

T
T
T

CCA
CCD
CCO

CC

I
i(p-p)

stg
amb
j

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output stages supply voltage note 1 −0.3 +7.0 V
supply voltage differences between

V
V
V

CCA
CCO
CCA

and V

and V

and V

CCD

CCD

CCO

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

input voltage referenced to AGND −0.3 +7.0 V
AC input voltage for switching

referenced to DGND − V

CCD

V

(peak-to-peak value)
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 +70 °C
junction temperature − +150 °C

Note

1. The supply voltages V
between V

CCA

, V

CCD

CCA

and V

and V

CCD

is between −1 and +1 V.

CCO

may have any value between −0.3 V and +7.0 V provided the difference

CCO

, V

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 110 K/W

1995 Mar 20 5

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for

TDA8761

digital video

CHARACTERISTICS

V

CCA=V3

V27= 4.4 to 5.25 V; AGND and DGND shorted together; T
V

CCA=VCCD=VCCO

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply

V

CCA

V

CCD

V

CCO

∆V

I

CCA

I

CCD

I

CCO

Inputs

to V4and V5= 4.75 to 5.25 V; V

=5V; V

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.4 5.0 5.25 V

CC

supply voltage differences between

and V

V
V
V

CCA
CCA
CCD

and V
and V

CCD
CCO
CCO

analog supply current − 30 tbf mA
digital supply current − 22 tbf mA
output stages supply current − 22 tbf mA

CCD=V11

= 1.5 V; CL= 15 pF and T

i(p-p)

to V12= 4.75 to 5.25 V; V

= 0 to +70 °C; typical values measured at

amb

=25°C; unless otherwise specified.

amb

CCO=V13

and V28to V14 and

−0.25 − +0.25 V

−0.4 − +0.4 V

−0.4 − +0.4 V

LOCK INPUT CLK (REFERENCED TO DGND); note 1

C
V

IL

V

IH

I

IL

I

IH

Z

I

C

I

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current V
HIGH level input current V
input impedance f

input capacitance f
INPUT CE (REFERENCED TO DGND); see Table 2
V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.8 V

HIGH level input voltage 2.0 − V

LOW level input current VIL= 0.4 V −400 −− µA

HIGH level input current VIH= 2.7 V −−20 µA
VI(ANALOG INPUT VOLTAGE REFERENCED TO AGND)
I

IL

I

IH

Z

I

C

I

LOW level input current VI= 1.3 V − 0 −µA

HIGH level input current VI= 3.8 V − 70 −µA

input impedance fi=10MHz − 5 − kΩ

input capacitance fi=10MHz − 8 − pF

CCD

= 0.4 V −10 +1 µA

clk

= 2.7 V −−20 µA

clk

=30MHz − 2 − kΩ

clk

=30MHz − 2 − pF

clk

CCD

V

V

1995 Mar 20 6

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for

TDA8761

digital video

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Reference voltages for the resistor ladder; see Table 1

V

RB

V

RT

V

diff

I

ref

R

LAD

TC

RLAD

V

osB

V

osT

V

i(p-p)

Outputs

IGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND)

D
V

OL

V

OH

I

OZ

Switching characteristics

reference voltage BOTTOM 1.2 1.3 − V

reference voltage TOP − 3.3 V

differential reference voltage

VRT− V

RB

1.8 2.0 3.0 V

− 0.8 V V

CCA

reference current − 30 − mA

resistor ladder − 85 −Ω

temperature coefficient of the resistor

ladder

− 1.86 − ppm

− 158 − mΩ/K

offset voltage BOTTOM note 2 − 250 − mV

offset voltage TOP note 2 − 250 − mV

analog input voltage

note 3 1.3 1.5 2.5 V

(peak-to-peak value)

LOW level output voltage IO= 1 mA 0 − 0.4 V

HIGH level output voltage IO= 0 mA 2.7 − V

= −0.4 mA 2.7 − V

I

O

= −1 mA 2.4 − V

I

O

output current in 3-state mode 0.4 V < VO<V

CCO

−20 − +20 µA

CCO
CCO
CCO

− 0.5 V

− 1.3 V

− 1.4 V

LOCK INPUT CLK; see Fig.3; note 1

C
f

clk(max)

t

CPH

t

CPL

maximum clock frequency 30 −− MHz

clock pulse width HIGH 10 −− ns

clock pulse width LOW 10 −− ns

Analog signal processing

INEARITY

L
AINL AC integral non-linearity note 5; full scale input

sine wave
note 5; 50% full scale

input sine wave

ADNL AC differential non-linearity note 5; full scale input

sine wave
note 5; 50% full scale

input sine wave

OFER offset error middle code;

= 1.3 V; VRT= 3.3 V

V

RB

GER gain error (from device to device) V

= 1.3 V;

RB

VRT= 3.3 V; note 4

−±0.75 tbf LSB

−±0.5 tbf LSB

−±0.5 tbf LSB

−±0.3 tbf LSB

−±1− LSB

−±0.1 − %

1995 Mar 20 7

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for

TDA8761

digital video

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

BANDWIDTH (f
B analog bandwidth full-scale sine wave;

t

STLH

t

STHL

HARMONICS (f
THD total harmonic distortion f
SIGNAL-TO-NOISE RATIO; see Fig.7; note 8
S/N signal-to-noise ratio (full scale) without harmonics;

EFFECTIVE BITS; see Fig 6; note 8
EB effective bits f

TWO-TONE; note 9
TTIR two-tone intermodulation rejection f
BIT ERROR RATE
BER bit error rate f

DIFFERENTIAL GAIN; note 10
G

diff

DIFFERENTIAL PHASE; note 10

ϕ

diff

= 30 MHz)

clk

analog input settling time

LOW-to-HIGH

analog input settling time

HIGH-to-LOW

=30MHZ)

clk

differential gain f

differential phase f

− 40 − MHz

note 6
75% full-scale sine

− 55 − MHz

wave; note 6
small signal at

− 700 − MHz

mid-scale;

= ±10 LSB at

V

I

code 256; note 6
full-scale square wave;

− 2.0 tbf ns

Fig.5; note 7
full-scale square wave;

− 2.5 tbf ns

Fig.5; note 7

=10MHz −−64 − dB

i

53 55 − dB

f

= 30 MHz;

clk

fi=10MHz

= 30 MHz;

clk

− 8.5 − bits

fi=10MHz

=30MHz −−64 − dB

clk

= 30 MHz;

clk

− 10

−13

− times/

fi= 10 MHz;
VI= ±16 LSB at
code 256

= 30 MHz;

clk

− tbf − %

PAL modulated ramp

= 30 MHz;

clk

− tbf − deg

PAL modulated ramp

sample

Timing (f

t

ds

t

h

t

d

C

L

= 30 MHz; CL= 15 pF); see Fig.3; note 11

clk

sampling delay time −−2ns

output hold time 5 −− ns

output delay time − 10 14 ns

digital output load − 15 40 pF

1995 Mar 20 8

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for

TDA8761

digital video

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
3-state output delay times; see Fig.4

t

dZH

t

dZL

t

dHZ

t

dLZ

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.

2. Analog input voltages producing code 0 up to and including code 511:
a) V

b) V

3. Analog input voltage range can be derived from VRT− VRB difference. It is

enable HIGH − tbf tbf ns
enable LOW − tbf tbf ns
disable HIGH − tbf tbf ns
disable LOW − tbf tbf ns

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

osB

the reference voltage BOTTOM (VRB) at T

(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

osT

produces data outputs equal to code 511 at T

amb

=25°C.

=25°C.

amb

VRTVRB–()8×

------------------------------------------­9

V

–()1.5 V–

GER

4.
= 11 MHz and f

5. f

i

511V0

---------------------------------------------------

1.5 V
= 30 MHz; fi= 8 MHz and f

clk

100×=

= 20 MHz.

clk

6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No
glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.

7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.

8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.10 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.

10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.

11. Output data acquisition: the output data is available after the maximum delay time of td.

1995 Mar 20 9

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for

TDA8761

digital video

Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB= 1.3 V, VRT= 3.3 V)

STEP V

I(p-p)

IR

D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0

U/F <1.55 0 0 00000000000000000

0 1.55 1 0 00000000000000000
1 . 1000000001000000001

. . ...................

. . ...................

510 . 1111111111111111110

511 3.05 1 1 11111111111111111

O/F >3.05 0 1 11111111111111111

Table 2 Mode selection

TC CE D8 TO D0 IR

X 1 high impedance high impedance

0 0 active; two’s complement active
1 0 active; binary active

BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS

handbook, full pagewidth

CLK

V

l

DATA
D0 to D8

t

sample N

DATA

N - 2

CPH

t

CPL

sample N + 1

t

ds

DATA

N - 1

t

Fig.3 Timing diagram.

1.4 V

sample N + 2

t

h

DATA

N

d

DATA

N + 1

2.4 V

1.4 V

0.4 V

MGC357

1995 Mar 20 10

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

V

handbook, full pagewidth

CCD

CE

output
data

output
data

LOW

t

dLZ

10 %

TDA8761

HIGH

CE

t

dZL

50 %

15 pF

HIGH

3.3 kΩ

t

90 %

dHZ

LOW

V

S1

CCD

50 %

t

dZH

50 %

TEST

t

dLZ

t

dZL

t

dHZ

t

dZH

S1

V

CCD

V

CCD

GND
GND

MGC358

TDA8761

fCE= 100kHz.

Fig.4 Timing diagram and test conditions of 3-state output delay time.

1995 Mar 20 11

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

t

handbook, full pagewidth

code 511

code 0

CLK

MGC359

V

I

STLH

50 %

2 ns

50 %

0.5 ns

2 ns

t

STHL

50 %

50 %

TDA8761

0.5 ns

Fig.5 Analog input settling-time diagram.

amplitude

(dB)

100

120

0

20

40

60

80

0 1.88 3.75

handbook, full pagewidth

Effective bits: 8.58; THD= −61.80 dB.
Harmonic levels (dB): 2nd = −64.77; 3rd = −79.30; 4th = −71.90; 5th = −66.12; 6th = −82.29.

MGC360

9.375.63 7.50 11.3 13.1 15.0
f (MHz)

Fig.6 Fast Fourier Transform (f

1995 Mar 20 12

= 30 MHz; fi= 10 MHz).

clk

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

INTERNAL PIN CONFIGURATIONS

V

handbook, halfpage

V

CCO1

D8 to D0

O/UF

OGND1

CCO2

MGC361

handbook, halfpage

V

CCA

V

I

AGND

TDA8761

MGC040

dbook, halfpage

Fig.7 TTL data and in-range outputs.

V

CCO1

CE

(TC)

OGND2

MGC041

handbook, halfpage

Fig.8 Analog inputs.

V

CCA

V

RT

V

RM

V

RB

AGND

R

LAD

MEA050

Fig.9 CE (TC) 3-state input.

1995 Mar 20 13

Fig.10 VRB, VRM and VRT.

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

V

handbook, full pagewidth

CCD

CLK

DGND

MGC042

TDA8761

V

(1.3 V)

ref

Fig.11 CLK input.

1995 Mar 20 14

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

APPLICATION INFORMATION

handbook, halfpage

V

AGND1

AGND2

V

100 nF

AGND

100 nF

AGND

100 nF

AGND

V

V

V

CLK

TC

CCA

RB

RM

RT

CE

CCD

TDA8761

V

1

2

3

4

5

(1)

6

(1)

7

V

I

(1)

TDA8761

8

9

10

11

28

27

26

25

24

23

22

21

20

19

18

CCO2

OGND2

IR

D8

D7

D6

D5

D4

D3

D2

D1

DGND

12

V

CCO1

13

OGND1

14

The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the

reference ladder voltages can be derived from a well regulated V
For applications where the input signal must remain well centred around middle scale, VRM must be decoupled and connected to analog input signal

(pin 8) through a resistor. The values must be defined in accordance with the input signal frequency in order to avoid direct coupling into the ADC ladder
(e.g. R = 5 kΩ and C = 100 nF).

, VRM and VRT are decoupled to AGND.

(1) V

RB

(2) Pins 15 and 16 should be connected to DGND in order to prevent noise influence.

supply through a resistor bridge and a decoupled capacitor.

CCA

17

16

15

MGC362

D0

n.c.

n.c.

(2)

(2)

Fig.12 Application diagram.

1995 Mar 20 15

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

D

c

y

Z

28 15

TDA8761

SOT341-1

E

H

E

A

X

v M

A

pin 1 index

114

w M

b

e

DIMENSIONS (mm are the original dimensions)

UNIT A

mm

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

A

max.

2.0

0.21

0.05

1

A2A

1.80

1.65

0.25

b

p

cD

0.20

0.09

3

0.38

0.25

p

0 2.5 5 mm

scale

(1)E(1) (1)

10.4

10.0

eHELLpQZywv θ

5.4

0.65 1.25

5.2

7.9

7.6

Q

A

2

A

1

detail X

0.9

1.03

0.7

0.63

(A )

L

p

L

0.13 0.10.2

A

3

θ

1.1

0.7

o

8

o

0

OUTLINE

VERSION

SOT341-1 MO-150AH

IEC JEDEC EIAJ

REFERENCES

1995 Mar 20 16

EUROPEAN

PROJECTION

ISSUE DATE

93-09-08
95-02-04

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

SOLDERING
Plastic small outline packages

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

Y SOLDER PASTE REFLOW

B

TDA8761

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

R

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

IRON OR PULSE

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

-HEATED SOLDER TOOL)

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1995 Mar 20 17

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

TDA8761

NOTES

1995 Mar 20 18

Philips Semiconductors Preliminary specification

9-bit analog-to-digital converter for
digital video

TDA8761

NOTES

1995 Mar 20 19

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

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th

floor, Suite 51,

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Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD39 © Philips Electronics N.V. 1995

All rights are reserved. Reproduction in whole or in part is prohibited without the
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The information presented in this document does not form part of any quotation
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use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

533061/1500/01/pp20 Date of release: 1995 Mar 20
Document order number: 9397 750 00112

Philips Semiconductors