Datasheet tda8755 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8755

YUV 8-bit video low-power
analog-to-digital interface

Product specification
Supersedes data of June 1994
File under Integrated Circuits, IC02

Philips Semiconductors

1995 Mar 09

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

FEATURES

• 8-bit resolution

• Sampling rate up to 20 MHz

• TTL compatible digital inputs

• 3-state TTL outputs

• U, V two's complement outputs

• Y binary output

• Power dissipation of 550 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• High signal-to-noise ratio over a large analog input
frequency range

• Track-and-hold included

• Clamp functions included

• UV multiplexed ADC

• 4:1:1 output data encoder

• Stable voltage regulator included.

TDA8755

APPLICATIONS

• High speed analog-to-digital conversion for video signal
digitizing

• 100 Hz improved definition TV (IDTV).

GENERAL DESCRIPTION

The TDA8755 is a bipolar 8-bit video low-power
analog-to-digital conversion (ADC) interface for YUV
signals. The device converts the YUV analog input signal
into 8-bit coded digital words in a 4 : 1 : 1 format at a
sampling rate of 20 MHz. The U/V signals are converted in
a multiplexed manner. All analog signal inputs are digitally
clamped and a fast precharge is provided for start-up.
All digital inputs and outputs are TTL compatible. Frame
synchronization is supported in a multiplexed manner.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

INL DC integral non-linearity f
DNL DC differential non-linearity f

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.75 5.0 5.25 V
analog supply current − 46 55 mA
digital supply current − 55 66 mA
output stages supply current − 912mA

= 2 MHz −±0.4 ±1 LSB

clk

= 2 MHz −±0.3 ±0.5 LSB

clk

EB effective bits − 7.1 − bits
f

clk(max)

P

tot

maximum clock frequency 20 −−MHz
total power dissipation − 550 700 mW

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

PINS PIN POSITION MATERIAL CODE

TDA8755T 32 SO32L plastic SOT287-1

1995 Mar 09 2

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

BLOCK DIAGRAM

2413

REG1 REG2 REG3

Y

D0

D7

8

24

31

TTL

I / O

8

8-BIT

PIPELINE

8

ADC

8-BIT

CLK

CE

HREF

17

14

16

TIMING GENERATOR

V

D'0

D'1

2

192021

TTL

U AND V

8

8-BIT

U

D'2

D'3

2

22

I / O

DATA

ENCODER

ADC

TDA8755

MLA734 - 1

TDA8755

CCO AGND DGND SDN n.c.

V

CCD

V

6 322310188 1

CCA

V

AND

HOLD

TRACK

Y

CLAMP

VOLTAGE REGULATOR

SUPPLY AND REFERENCE

5

3

16

COMPARATOR

LOGIC

CLAMP

15

TRACK

7

AND

HOLD

AND

HOLD

TRACK

ANALOG

MULTIPLEXER

DIGITAL

MULTIPLEXER

CLAMPUCLAMP

11

V

12

128

COMPARATOR

AND

HOLD

TRACK

9

handbook, full pagewidth

Fig.1 Block diagram.

INY

CLPY

CLP

1995 Mar 09 3

INU

CLPU

CLPV

INV

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
REG1 2 decoupling input (internal

stabilization loop decoupling)
INY 3 Y analog voltage input
REG2 4 decoupling input (internal

stabilization loop decoupling)
CLPY 5 Y clamp capacitor connection
V

CCA

INU 7 U analog voltage input
SDN 8 stabilizer decoupling node and

INV 9 V analog voltage input
AGND 10 analog ground
CLPU 11 U clamp capacitor connection
CLPV 12 V clamp capacitor connection
REG3 13 decoupling input (internal

CE 14 chip enable input (TTL level input

CLP 15 clamp control input
HREF 16 horizontal reference signal
CLK 17 clock input
DGND 18 digital ground
D'0 19 V data output; bit 0 (n−1)
D'1 20 V data output; bit 1 (n)
D'2 21 U data output; bit 0 (n−1)
D'3 22 U data output; bit 1 (n)
V

CCO

D0 24 Y data output; bit 0 (LSB)
D1 25 Y data output; bit 1
D2 26 Y data output; bit 2
D3 27 Y data output; bit 3
D4 28 Y data output; bit 4
D5 29 Y data output; bit 5
D6 30 Y data output; bit 6
D7 31 Y data output; bit 7 (MSB)
V

CCD

6 analog positive supply voltage

(+5 V)

analog reference voltage (+3.35 V)

stabilization loop decoupling)

active LOW)

23 positive supply voltage for output

stages (+5 V)

32 digital positive supply voltage (+5 V)

handbook, halfpage

1

n.c.

2

REG1

INY

3

REG2

4
5

CLPY

V

CCA

6

INU

7

SDN

8

INV

AGND

CLPU
CLPV
REG3

CE

CLP

HREF CLK

TDA8755

9
10
11
12

13
14
15
16

MLA728 - 1

V

32
31

D7
D6

30

D5

29
28

D4
D3

27

D2

26

D1

25

D0

24

V

23

D'3

22

D'2

21

D'1

20
19

D'0

18

DGND

17

Fig.2 Pin configuration.

TDA8755

CCD

CCO

1995 Mar 09 4

Philips Semiconductors Product specification

YUV 8-bit video low-power

TDA8755

analog-to-digital interface

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

CC

analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
output stages supply voltage −0.3 +7.0 V
supply voltage difference between V
supply voltage difference between V
supply voltage difference between V

CCA
CCO
CCA

and V

and V

and V

CCD

CCD

CCO

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

input voltage referenced to AGND − +5.0 V
AC input voltage for switching (peak-to-peak value) referenced to DGND − V

CCD

V
output current − +6 mA
storage temperature −55 +150 °C
operating ambient temperature 0 +70 °C
junction temperature − +150 °C

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 70 K/W

1995 Mar 09 5

Philips Semiconductors Product specification

YUV 8-bit video low-power

TDA8755

analog-to-digital interface

CHARACTERISTICS

V

CCA=V6

AGND and DGND shorted together; V
V

CCA

T

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Inputs

CLK (
V

IL

V

IH

I

IL

I

IH

Z

I

C

I

CE, CLP AND HREF (PINS 14 TO 16)
V

IL

V

IH

I

IL

I

IH

CLPY (PIN 5)
V

5

I

5

CLPU AND CLPV (PINS 11 AND 12)
V

11, 12

I

11, 12

INY (PIN 3)
V

I(p-p)

Z

I

C

I

to V10= 4.75 to 5.25 V; V

to V

= −0.25 to +0.25 V; T

CCO

CCD=V32

CCA

= 0 to +70 °C; typical values measured at V

amb

=25°C; unless otherwise specified.

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.75 5.0 5.25 V
analog supply current − 46 55 mA
digital supply current − 55 66 mA
output stages supply current − 912mA

PIN 17)

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current V
HIGH level input current V
input impedance f
input capacitance f

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current V
HIGH level input current V

clamp voltage for 16 output code − 3.725 − V
clamp output current −±50 −µA

clamp voltage for 128 output code − 3.30 − V
clamp output current −±50 −µA

input voltage, full range
(peak-to-peak value)

input impedance fi= 6 MHz − 30 − kΩ
input capacitance fi= 6 MHz − 1 − pF

to V18= 4.75 to 5.25 V; V

to V

= −0.25 to +0.25 V; V

CCD

= 0.4 V −400 −−µA

clk

= 2.7 V −−100 µA

clk

=20MHz − 4 − kΩ

clk

=20MHz − 4.5 − pF

clk

= 0.4 V −400 −−µA

clk

= 2.7 V −−100 µA

clk

fi= 4.43 MHz 0.93 1.0 1.07 V

CCO=V23

to V

CCO

to V18= 4.75 to 5.25 V;

= −0.25 to +0.25 V;

CCD

CCA=VCCD=VCCO

= 5 V and

CCD

CCD

V

V

1995 Mar 09 6

Philips Semiconductors Product specification

YUV 8-bit video low-power

TDA8755

analog-to-digital interface

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

INU AND INV (PINS 7 AND 9)
V

I(p-p)

input voltage, full range
(peak-to-peak value)

Z

I

C

I

input impedance fi= 2 MHz − 30 − kΩ
input capacitance fi= 2 MHz − 1 − pF

INPUTS ISOLATION

α

ct

crosstalk between Y, U and V −−55 −50 dB

Outputs

SDN (

PIN 8)

V
V
I

ref
REG

L

reference voltage − 3.32 − V
line regulation 4.75 V ≤ V

load current −2 −−mA
DIGITAL OUTPUTS D0 TO D7 AND D’0 TO D’3 (PINS 24 TO 31 AND 19 TO 22)
V

OL

V

OH

I

OZ

LOW level output voltage IO= 0.4 mA 0 − 0.4 V

HIGH level output voltage IO= −0.4 mA 2.4 − V

output current in 3-state mode 0.4 V < VO<V

Switching characteristics

f

clk(max)

f

clk(min)

t

CPH

t

CPL

Analog signal processing (f

G

diff

ϕ

diff

f

1

f

all

maximum clock frequency 20 −−MHz

minimum clock frequency −−2.0 MHz

clock pulse width HIGH 20 −−ns

clock pulse width LOW 20 −−ns

= 20 MHz; 50% clock duty factor)

clk

differential gain note 1; see Fig.8 − 2 − %

differential phase note 1; see Fig.8 − 3 − deg

fundamental harmonics (full-scale) note 2 −−0dB

harmonics (full-scale),

all components
SVRR1 supply voltage ripple rejection 1 note 3 −−40 − dB
SVRR2 supply voltage ripple rejection 2 note 3 − 1.0 − %/V

fi= 1.5 MHz 0.93 1.03 1.13 V

≤ 5.25 V − 4.0 − mV

CCA

= 1.5 mA 0 − 0.5 V

I

O

V

CCD

CCD

−20 − +20 µA

note 2; see Fig.10 −−54 − dB

Transfer function (50% clock duty factor)

INL DC integral non-linearity f
DNL DC differential non-linearity f

= 2 MHz −±0.4 ±1.0 LSB

clk

= 2 MHz −±0.3 ±0.5 LSB

clk

AILE AC integral non-linearity note 4 −±1.0 ±2.0 LSB
EB effective bits note 5; Fig.10 − 7.1 − bits

1995 Mar 09 7

Philips Semiconductors Product specification

YUV 8-bit video low-power

TDA8755

analog-to-digital interface

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing (f

t

ds

t

h

t

d

t

dZH

t

dZL

t

dHZ

t

dLZ

t

r

t

f

t

su

t

h

t

r

t

f

t

CLP

Notes

1. Low frequency ramp signal (V
(V

2. The input conditions are related as follows:
a) Y channel: V
b) U/V channel: V

3. Supply voltage ripple rejection:
a) SVRR1 is the variation of the input voltage producing output code 127 (code 15) for supply voltage variation

b) SVRR2 is the relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V:

4. Full-scale sinewave (f

5. The number of effective bits is measured using a 20 MHz clock frequency. This value is given for a 4.43 MHz input
frequency on the Y channel (1.5 MHz on the U and V channels). This value is obtained via a Fast Fourier Transform
(FFT) treatment taking 4 × T
harmonics and noise up to half of the clock frequency (NYQUIST frequency).

Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

6. Output data acquisition is available after the maximum delay time of td.

7. U and V output data is not valid during t

= 20 MHz); note 6; see Figs 3 to 7

clk

sampling delay time − 1 − ns
output hold time 7 −−ns
output delay time − 33 42 ns
3-state output delay time enable-to-HIGH − 10 14 ns
3-state output delay time enable-to-LOW − 10 14 ns
3-state output delay time disable-to-HIGH − 811ns
3-state output delay time disable-to-LOW − 46ns
clock rise time 3 5 − ns
clock fall time 3 5 − ns
HREF set-up time 7 −−ns
HREF hold time 3 −−ns
data output rise time − 12 − ns
data output fall time − 16 − ns
minimum time for active clamp note 7; see Fig.9 3 −−µs

= full-scale and 64 µs period) combined with a sinewave input voltage

I(p-p)

= 0.25 full-scale, fi= maximum permitted frequency) at the input.

I(p-p)

= 1.0 V; fi= 4.43 MHz

I(p-p)

= 1.0 V; fi= 1.5 MHz.

I(p-p)

of 0.5 V:

∆V

SVRR1 20 log

=

∆ V

SVVR2

-----------------------------------------------­V

I127()

---------------------­∆V

CCA

–()

I0()VI255()

–

I0()VI 255()

= 4.43 MHz for Y and fi= 1.5 MHz for U and V; f

i

(clock periods) acquisition points per period. The calculation takes into account all

clk

×=

-----------------­∆ V

1

CCA

CLP

.

= 20 MHz).

clk

1995 Mar 09 8

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

Table 1 Mode selection

CE D7 TO D0; D’3 TO D’0

1 high impedance
0 active; binary

Table 2 Output data coding

OUTPUT PORT BIT OUTPUT DATA

YD7Y

U D’3

V D’1

D6 Y
D5 Y
D4 Y
D3 Y
D2 Y
D1 Y
D0 Y

D’2 U

D’0 V

7Y

0

6Y

0

5Y

0

4Y

0

3Y

0

2Y

0

1Y

0

0Y

0

U07U

6U

0

V07V

6V

0

7Y

1

6Y

1

5Y

1

4Y

1

3Y

1

2Y

1

1Y

1

0Y

1

5U

0

4U

0

5V

0

4V

0

TDA8755

7Y

2

6Y

2

5Y

2

4Y

2

3Y

2

2Y

2

1Y

2

0Y

2

3U

0

2U

0

3V

0

2V

0

7

3

6

3

5

3

4

3

3

3

2

3

1

3

0

3

1

0

0

0

1

0

0

0

t

t

ds

DATA

N 4

sample N

CPHtCPL

sample N 1

DATA

N 3

sample N 2 sample N 3 sample N 4 sample N 5

DATA

N 2

ndbook, full pagewidth

CLK

V

l

D0 to D7

Fig.3 Timing diagram (INY signal).

1995 Mar 09 9

DATA

N 1

1.4 V

t

h

DATA

N

t

d

DATA

N 1

2.4 V

1.4 V

0.4 V

MSA646

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

V

CE

output
data

output
data

CCD

ndbook, full pagewidth

LOW

t

dLZ

10 %

TDA8755

CE

HIGH

t

dZL

50 %

15 pF

HIGH

3.3 kΩ

t

90 %

dHZ

LOW

V

S1

CCD

50 %

t

dZH

50 %

MBD874

TDA8755

TEST S1

t

dLZ

t

dZL

t

dHZ

t

dZH

V
V
GND
GND

CCD
CCD

fCE= 100kHz.

Fig.4 Timing diagram and test conditions of 3-state output delay time.

handbook, halfpage

TDA8755

15 pF

test probe
TEK P6201

D0 to D7

MLA733 - 1

Fig.5 Load circuit for the 3-state output timing

measurement.

1995 Mar 09 10

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

handbook, full pagewidth

CLK

HREF

output

data

sample N

123

t

su

N 4 N 3 N 2 N 1 N

4

sample N 4

5

sample N
output data valid

TDA8755

t

h

MLA732 - 1

The output data is valid 4 clock periods after HREF goes HIGH.

Fig.6 Timing definition for set-up and hold times (HREF signal).

4 clock periods (T )

handbook, full pagewidth

CLK

HREF

output
data

sample N sample N 4 x T

N 4 N 3 N 3

clk

clk

sample N 4 (T 1)

output data valid

clk

MLA731 - 1

When the HREF period is a multiple of 4 clock periods, the output data is valid without any clock delay.
The internal circuit always gives an internal delay of 4 clock periods as illustrated in Fig.6.

Fig.7 Timing diagram (HREF signal).

1995 Mar 09 11

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

handbook, full pagewidth

64 µs

0.3 V

0.3 V

MSA644

Y, U and V

channel

1.2 V

TDA8755

Y channel = 4.43 MHz sinewave.
U, V channel = 1.5 MHz sinewave.

handbook, full pagewidth

digital
output

level

255

Y : 16
U,V : 128

0

Fig.8 Input test signal for differential gain and phase measurements.

black-level

clamping

t

CLP

CLP

MSA645

time

Fig.9 Clamping control timing.

1995 Mar 09 12

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

amplitude

(dB)

100

120

0

20

40

60

80

0 1.25 2.50

handbook, full pagewidth

3.75

TDA8755

MBD873

8.755.00 6.25 7.50 10.00
f (MHz)

Effective bits: 7.30; THD = −53.35 dB.
Harmonic levels (dB): 2nd = −58.38; 3rd = −60.03; 4th = −57.30; 5th = −69.38; 6th = −67.09.

Fig.10 Fast Fourier Transform (f

= 20 MHz; fi= 4.43 MHz).

clk

1995 Mar 09 13

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

APPLICATION INFORMATION

ndbook, full pagewidth

AGND

AGND

AGND

5 V

10 nF

+ 3.35 V

(2)

10 nF

AGND

AGND

AGND

TDA8755

n.c.

1

10 nF

REG1

2

INY

REG2

CLPY

V

CCA

INU

SDN

INV

AGND

CLPU

CLPV

REG3

CE

3

4

5

6

7

8

TDA8755

9

10

11

12

13

14

(3)

4.7 µF

220 nF

(1)

(3)

4.7 µF

(3)

4.7 µF

(1)

(1)

220 nF

V

CCD

32

D7

31

D6

30

D5

29

D4

28

D3

27

D2

26

D1

25

D0

24

V

CCO

23

D'3

22

D'2

21

D'1

20

D'0

19

10 nF

DGND

10 nF

DGND

5 V

5 V

CLP

15

HREF

16

MLA735 - 1

The analog and digital supplies should be separated and decoupled.
(1) Clamp capacitors must be determined in accordance with the application; recommended values are CLPY = 18 nF, CLPU and CLPV = 33 nF.
(2) It is possible to use the reference output voltage pin SDN to drive other analog circuits under the limits indicated in Chapter “Characteristics”.
(3) Input signal pins have a high bandwidth. It is necessary to take special care on PCB layout to avoid any interaction from other signals (digital clocks

for example).

DGND

18

CLK

17

Fig.11 Application diagram.

1995 Mar 09 14

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

ndbook, full pagewidth

Y

U

V

VSYNC
SC1

12

TDA8755

12/13.5/16/18 MHz 32/36 MHz

VCO1

VDRAM

1 x TMS4C2970

VDRAM

1 x TMS4C2970

control

MEMORY

CONTROLLER

SAA4951

12

12

12

SAA4940

REDUCTION

INCLUDING

CROSS-COLOUR

REDUCTION

NOISE

VCO2A

TDA8755

12

12

SAA7158 Y

VIDEO

ENHANCEMENT,

LFR

PROCESSING

AND DACs

22

H2, V2

(32 kHz/100 Hz)

27 MHz

U

V

to

video

processor

to

deflection

processor

2

I C

2

VCO2B

µC bus

MSA642

control

2

MICROCONTROLLER

PCB83C652

data

8

Fig.12 Block diagram of a full-options Improved Picture Quality (IPQ) module.

1995 Mar 09 15

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

ndbook, full pagewidth

Y

U

V

VSYNC
SC1

TDA8755

12/13.5/16/18 MHz 32/36 MHz

VCO1

control

MEMORY

CONTROLLER

SAA4951

12 12

VDRAM

1 x

TMS4C2970

VCO2A

VIDEO

ENHANCEMENT

AND

DACs

SAA7165

2

2

I C bus

H2, V2

(32 kHz/100 Hz)

27 MHz

TDA8755

Y

U

video

processor

V

deflection
processor

to

to

2

I C

control

2

MICROCONTROLLER

PCB83C652

data

8

VCO2B

MSA643

Fig.13 Block diagram of an economic Improved Picture Quality (IPQ) module.

1995 Mar 09 16

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

PACKAGE OUTLINE

handbook, full pagewidth

SO32: plastic small outline package; 32 leads; body width 7.5 mm

D

y

Z

32

17

TDA8755

SOT287-1

E

c

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

2.65

0.10

A1A

0.3

0.1

0.012

0.004

2.45

2.25

0.096

0.086

2

A3b

0.25

0.01

0.49

0.36

0.02

0.01

p

0.27

0.18

0.011

0.007

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1)

cD

20.7

20.3

0.81

0.80

7.6

7.4

0.30

0.29

16

b

p

scale

eHELLpQZywv θ

1.27

0.050

10.65

10.00

0.42

0.39

w M

1.4

0.055

A

2

1.1

0.4

0.043

0.016

Q

A

1

detail X

1.2

0.25

1.0

0.047

0.039

(A )

L

p

L

0.25 0.1

0.004

0.010.01

A

3

θ

(1)

0.95

0.55

0.037

0.022

o

8

o

0

OUTLINE
VERSION

SOT287-1

IEC JEDEC EIAJ

REFERENCES

1995 Mar 09 17

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17
95-01-25

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

SOLDERING
Plastic small outline packages

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

Y SOLDER PASTE REFLOW

B

TDA8755

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

R

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

IRON OR PULSE

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

-HEATED SOLDER TOOL)

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1995 Mar 09 18

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

TDA8755

NOTES

1995 Mar 09 19

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS:

Tel. [phone], Fax. [phone]

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. [phone], Fax. [phone]

Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,

77621 BOGOTA, Tel. [phone],
Fax. [phone]

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,
Tel. [phone], Fax. [phone]

Germany: P.O. Box 10 63 23, 20043 HAMBURG,

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Tel. [phone] 911, Fax. [phone]

Hong Kong: PHILIPS HONG KONG Ltd., 15/F Philips Ind. Bldg.,

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Dr. Annie Besant Rd. Worli, Bombay 400 018
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Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS S.r.l.,

Piazza IV Novembre 3, 20124 MILANO,
Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,

Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone].

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. [phone], Fax. [phone].

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone].

Spain: Balmes 22, 08007 BARCELONA,

Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone].

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. [phone], Fax. [phone].

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors LTD.,

276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. [phone], Fax. [phone]

United States:811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD38 © Philips Electronics N.V. 1995

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

533061/30/03/pp20 Date of release: 1995 Mar 09
Document order number: 9397 750 00027

Philips Semiconductors