Datasheet tda8752a DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8752A

Triple high-speed Analog-to-Digital
Converter (ADC)

Product specification
Supersedes data of 1998 Dec 14
File under Integrated Circuits, IC02

1999 Feb 24

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

FEATURES

• Triple 8-bit ADC

• Sampling rate up to 100 MHz

• IC controllable via a serial interface, which can be either

I2C-bus or 3-wire, selected via a TTL input pin

• IC analog voltage input from 0.4 to 1.2 V (p-p) to
produce full-scale ADC input of 1 V (p-p)

• 3 clamps for programming a clamping code between

−63.5 and +64 in steps of1⁄2LSB

• 3 controllable amplifiers: gain controlled via the serial

interface to produce a full scale resolution of
peak-to-peak

• Amplifier bandwidth of 250 MHz

• Low gain variation with temperature

• PLL, controllable via the serial interface to generate the

ADC clock, which can be locked to a line frequency from
15 to 280 kHz

• Integrated PLL divider

• Programmable phase clock adjustment cells

• Internal voltage regulators

• TTL compatible digital inputs and outputs

• Chip enable high-impedance ADC output

• Power-down mode

• Possibility to use up to four ICs in the same system,

using the I2C-bus interface, or more, using the 3-wire
serial interface

• 1 W power dissipation.

1

⁄2LSB

TDA8752A

GENERAL DESCRIPTION

The TDA8752A is a triple 8-bit ADC with controllable
amplifiers and clamps for the digitizing of large bandwidth
RGB signals.

The clamp level, the gain and all of the other settings are
controlled via a serial interface (either I
serial bus, selected via a logic input).

The IC also includes a PLL that can be locked on the
horizontal line frequency and generates the ADC clock.
The PLL jitter is minimized for high resolution PC graphics
applications. An external clock can also be input to the
ADC.

It is possible to set the TDA8752A serial bus address
between four fixed values, in the event that several
TDA8752A ICs are used in a system, using the I
interface (for example, two ICs used in an odd/even
configuration).

2

C-bus or 3-wire

2

C-bus

APPLICATIONS

• R, G and B high-speed digitizing

• LCD panels drive

• LCD projection systems

• VGA and higher resolutions

• Using two ICs in parallel, higher display resolution can

be obtained; 200 MHz pixel frequency.

ORDERING INFORMATION

PACKAGE SAMPLING

TYPE NUMBER

TDA8752AH/6 QFP100 plastic quad flat package; 100 leads (lead length
TDA8752AH/8 100

1999 Feb 24 2

NAME DESCRIPTION VERSION

SOT317-2 60

1.95 mm); body 14 × 20 × 2.8 mm

FREQUENCY

(MHz)

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

DDD

V

CCD

V

CCO

V

CCA(PLL)

V

CCO(PLL)

I

CCA

I

DDD

I

CCD

I

CCO

I

CCA(PLL)

I

CCO(PLL)

f

CLK

f

ref(PLL)

f

VCO

INL DC integral non linearity from analog input to

DNL DC differential non linearity from analog input to

∆G

amp

B amplifier bandwidth −3 dB; T
t

set

DR

PLL

P

tot

j

PLL(rms)

analog supply voltage for R, G and B channels 4.75 5.0 5.25 V
logic supply voltage for I2C-bus and 3-wire 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage for R, G and B channels 4.75 5.0 5.25 V
analog PLL supply voltage 4.75 5.0 5.25 V
output PLL supply voltage 4.75 5.0 5.25 V
analog supply current − 120 − mA
logic supply current for I2C-bus and 3-wire − 1.0 − mA
digital supply current − 40 − mA
output stages supply current f

= 100 MHz;

CLK

− 6 − mA

ramp input
analog PLL supply current − 28 − mA
output PLL supply current − 5 − mA
maximum clock frequency TDA8752A/6 60 −−MHz

TDA8752A/8 100 −−MHz
PLL reference clock frequency 15 − 280 kHz
VCO output clock frequency 12 − 100 MHz

−±0.5 ±1.5 LSB
digital output; full-scale;
ramp input;
f

= 100 MHz

CLK

−±0.5 ±1.0 LSB
digital output; full-scale;
ramp input;

= 100 MHz

f

CLK

/T amplifier gain stability as a function of

temperature

settling time of the ADC block plus AGC input signal settling

V

= 2.5 V with

ref

100 ppm/°C maximum

=25°C 250 −−MHz

amb

time < 1 ns; T

amb

=25°C

−−200 ppm/°C

−−6ns

PLL divider ratio 100 − 4095
total power consumption f

= 100 MHz;

CLK

− 1.0 − W
ramp input

maximum PLL phase jitter (RMS value) f

= 66.67 kHz;

ref

f

= 100 MHz

CLK

− 0.3 − ns

1999 Feb 24 3

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1999 Feb 24 4

RAGC

RGAINC

V

CCAR

6
8

V

11

CCAG

19

V

CCAB

V

V

DDD

27

40

CCOR

V

79

V

CCOG

69

CCOB

59

V

V

CCD

CCA(PLL)

V

CCO(PLL)

95

99

book, full pagewidth

CLP

AGNDR

85

89

AGNDG

13

AGNDB

21

V

29

SSD

41

OGNDG

OGNDR

70

OGNDB

60

AGNDPLL

OGNDPLL

96

48

82

DGND

86

9
7

RCLP

RBOT

BLOCK DIAGRAM

Triple high-speed Analog-to-Digital

Converter (ADC)

Philips Semiconductors Product specification

RIN

RDEC

V

ref

GAGC

GGAINC

GIN

GDEC

BAGC

BGAINC

BIN

BDEC

TDO

TCK
ADD2
ADD1

SEN

SCL

SDA

DIS

2

I

C/3W

12
10

3

14
16

20
18

22
24

28
26

36
35

34
33
38
42
39
37
32

INTERFACE

1, 5, 30, 31, 43 , 44
50, 51, 100

SERIAL

2

I

C-BUS

OR

3-WIRE

MUX

HSYNCI

2

I

C-bus; 1-bit

(H level)

90

CLAMP

ADC

RED CHANNEL

GREEN CHANNEL

BLUE CHANNEL

TDA8752A

REGULATOR

4 2 88 97 98

PWDWN

DEC2DEC1HSYNCn.c.

CP

PLL

CZ

OUTPUTS

71 to 78

45

17
15

61 to 68

46
87

25
23

49, 52 to 58

47

84
83
81
80

92
91
93
94

FCE079

R0 to R7

ROR

GCLP
GBOT

G0 to G7
GOR

OE
BCLP
BBOT

B0 to B7
BOR

CKADCO
CKBO
CKAO

CKREFO

CKEXT
INV
COAST
CKREF

TDA8752A

Fig.1 Block diagram.

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

CLP RAGC CLKADC

handbook, full pagewidth

RCLP

V

ref

RIN

V

P

150

kΩ

3
kΩ

45
kΩ

DAC

5

REGISTER

FINE GAIN ADJUST

I2C-bus; 5 bits

(Fr)

MUX

CLAMP

CONTROL

AGC

V

CCAR

ADC

ADC

8

D

D ≥ R

R

1

1

COARSE GAIN ADJUST

8

7

REGISTER

2

I

C-bus; 7 bits

(Cr)

DAC

8

REGISTER

2

I

C-bus; 8 bits

(Or)

OUTPUTS

SERIAL

2

I

C-BUS

TDA8752A

ROR

8

R0 to R7

OE

RBOT

HSYNCI

RGAINC

Fig.2 Red channel diagram.

1999 Feb 24 5

MGG364

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

CKREF

edge selector

2

I

C-bus;
1 bit
(edge)

2

I

C-bus; 1 bit

(V level)

COAST

PHASE

FREQUENCY

DETECTOR

2

I

C-bus; 5 bits

(Ip, Up, Do)

DIV N (100 to 4095)

2

I

C-bus; 12 bits (Di)

C

z

CZ CP

loop filter

2

I

C-bus;

3 bits (Z)

2 bits (VCO)

C

p

VCO

2

I

C-bus;

12 to

100 MHz

phase selector A

2

I

C-bus;

5 bits (Pa)

phase selector B

2

I

C-bus; 5 bits (Pb)

CKEXT INV

MUX

2

I

C-bus;

1 bit (Cka)

0°/180°

CLK
ADC

TDA8752A

CKADCO

CKBO

2

C-bus;

I

1 bit (Ckb)

CKAO

Fig.3 PLL diagram.

SYNCHRO

CKREFO

MGG370

1999 Feb 24 6

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
DEC2 2 main regulator decoupling input
V

ref

DEC1 4 main regulator decoupling input
n.c. 5 not connected
RAGC 6 red channel AGC output
RBOT 7 red channel ladder decoupling input (BOT)
RGAINC 8 red channel gain capacitor input
RCLP 9 red channel gain clamp capacitor input
RDEC 10 red channel gain regulator decoupling input
V

CCAR

RIN 12 red channel gain analog input
AGNDR 13 red channel gain analog ground
GAGC 14 green channel AGC output
GBOT 15 green channel ladder decoupling input (BOT)
GGAINC 16 green channel gain capacitor input
GCLP 17 green channel gain clamp capacitor input
GDEC 18 green channel gain regulator decoupling input
V

CCAG

GIN 20 green channel gain analog input
AGNDG 21 green channel gain analog ground
BAGC 22 blue channel AGC output
BBOT 23 blue channel ladder decoupling input (BOT)
BGAINC 24 blue channel gain capacitor input
BCLP 25 blue channel gain clamp capacitor input
BDEC 26 blue channel gain regulator decoupling input
V

CCAB

BIN 28 blue channel gain analog input
AGNDB 29 blue channel gain analog ground
n.c. 30 not connected
n.c. 31 not connected
I2C/3W 32 selection input between I2C-bus (active HIGH) and 3-wire serial bus (active LOW)
ADD1 33 I2C-bus address control input 1
ADD2 34 I2C-bus address control input 2
TCK 35 scan test mode (active HIGH)

3 gain stabilizer voltage reference input

11 red channel gain analog power supply

19 green channel gain analog power supply

27 blue channel gain analog power supply

1999 Feb 24 7

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

SYMBOL PIN DESCRIPTION

TDO 36 scan test output
DIS 37 I2C-bus and 3-wire disable control input (disable at HIGH level)
SEN 38 select enable for 3-wire serial bus input (see Fig.10)
SDA 39 I2C-bus/3 W serial data input
V

DDD

V

SSD

SCL 42 I
n.c. 43 not connected
n.c. 44 not connected
ROR 45 red channel ADC output bit out of range
GOR 46 green channel ADC output bit out of range
BOR 47 blue channel ADC output bit out of range
OGNDB 48 blue channel ADC output ground
B0 49 blue channel ADC output bit 0 (LSB)
n.c. 50 not connected
n.c. 51 not connected
B1 52 blue channel ADC output bit 1
B2 53 blue channel ADC output bit 2
B3 54 blue channel ADC output bit 3
B4 55 blue channel ADC output bit 4
B5 56 blue channel ADC output bit 5
B6 57 blue channel ADC output bit 6
B7 58 blue channel ADC output bit 7 (MSB)
V

CCOB

OGNDG 60 green channel ADC output ground
G0 61 green channel ADC output bit 0 (LSB)
G1 62 green channel ADC output bit 1
G2 63 green channel ADC output bit 2
G3 64 green channel ADC output bit 3
G4 65 green channel ADC output bit 4
G5 66 green channel ADC output bit 5
G6 67 green channel ADC output bit 6
G7 68 green channel ADC output bit 7 (MSB)
V

CCOG

OGNDR 70 red channel ADC output ground
R0 71 red channel ADC output bit 0 (LSB)

40 logic I2C-bus/3 W digital power supply
41 logic I2C-bus/3 W digital ground

2

C-bus/3 W serial clock input

59 blue channel ADC output power supply

69 green channel ADC output power supply

TDA8752A

1999 Feb 24 8

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

SYMBOL PIN DESCRIPTION

R1 72 red channel ADC output bit 1
R2 73 red channel ADC output bit 2
R3 74 red channel ADC output bit 3
R4 75 red channel ADC output bit 4
R5 76 red channel ADC output bit 5
R6 77 red channel ADC output bit 6
R7 78 red channel ADC output bit 7 (MSB)
V

CCOR

CKREFO 80 reference output clock resynchronized horizontal pulse
CKAO 81 PLL clock output 3 (in phase with reference output clock)
OGNDPLL 82 PLL digital ground
CKBO 83 PLL clock output 2
CKADCO 84 PLL clock output 1 (in phase with internal ADC clock)
V

CCO(PLL)

DGND 86 digital ground
OE 87 output enable not (when OE is HIGH, the outputs are in high-impedance)
PWDWN 88 power-down control input (IC is in power-down mode when this pin is HIGH)
CLP 89 clamp pulse input (clamp active HIGH)
HSYNC 90 horizontal synchronization input pulse
INV 91 PLL clock output inverter command input (invert when HIGH)
CKEXT 92 external clock input
COAST 93 PLL coast command input
CKREF 94 PLL reference clock input
V

CCD

AGNDPLL 96 PLL analog ground
CP 97 PLL filter input
CZ 98 PLL filter input
V

CCAPLL

n.c. 100 not connected

79 red channel ADC output power supply

85 PLL output power supply

95 digital power supply

99 PLL analog power supply

1999 Feb 24 9

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

n.c.

DEC2

V

DEC1

n.c.

RAGC

RBOT

RGAINC

RCLP

RDEC

V

CCAR

RIN

AGNDR

GAGC
GBOT

GGAINC

GCLP

GDEC

V

CCAG

GIN

AGNDG

BAGC

BBOT

BGAINC

BCLP

BDEC

V

CCAB

BIN

AGNDB

n.c.

ref

CCA(PLL)

n.c.

V

CZCPAGNDPLL

99989796959493929190898887868584838281

100

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

20
21
22
23
24
25
26
27
28
29
30

CCD

V

CKREF

COAST

TDA8752AH

CKEXT

INV

HSYNC

CLP

PWDWNOEDGND

V

CCO(PLL)

CKADCO

CKBO

OGNDPLL

CKAO

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

TDA8752A

CKREFO
V

CCOR

R7
R6
R5
R4
R3
R2
R1
R0
OGNDR
V

CCOG

G7
G6
G5
G4
G3
G2
G1
G0
OGNDG
V

CCOB

B7
B6
B5
B4
B3
B2
B1
n.c.

31323334353637383940414243444546474849

n.c.

C/3W

2

I

ADD1

ADD2

TCK

TDO

DIS

SEN

SDA

DDD

V

Fig.4 Pin configuration.

1999 Feb 24 10

SSD

V

SCL

n.c.

n.c.

ROR

GOR

BOR

B0

OGNDB

50

FCE080

n.c.

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

FUNCTIONAL DESCRIPTION

This triple high-speed 8-bit ADC is designed to convert
RGB signals, from a PC or work station, into data used by
a LCD driver (pixel clock up to 200 MHz, using 2 ICs).

IC analog video inputs

The video inputs are internally DC polarized. These inputs
are AC coupled externally.

Clamps

Three independent parallel clamping circuits are used to
clamp the video input signals on the black level and to
control the brightness level. The clamping code is
programmable between code −63.5 and +64 in steps of

1

⁄2LSB. The programming of the clamp value is achieved

via an 8-bit DAC. Each clamp must be able to correct an
offset from±0.1 V to±10 mV within 300 ns, and correct the
total offset in 10 lines.

The clamps are controlled by an external TTL positive
going pulse (pin CLP). The drop of the video signal is
<1 LSB.

Normally, the circuit operates with a 0 code clamp,
corresponding to the 0 ADC code. This clamp code can be
changed from −63.5 to +64 as represented in Fig.7, in
steps of1⁄2LSB. The digitized video signal is always
between code 0 and code 255 of the ADC.

TDA8752A

The output of the multiplexer is either the normal video
signal or the 0.156 V reference signal (during HSYNC).

The corresponding ADC outputs are then compared to a
pre-set value loaded in a register. Depending on the result
of the comparison, the gain of the variable gain amplifiers
is adjusted (coarse gain control; see Figs 2 and 8).
The three 7-bit registers receive data via a serial interface
to enable the gain to be programmed.

The pre-set value loaded in the 7-bit register is chosen
between approximately 67 codes to ensure the full-scale
input range (see Fig.8). A contrast control can be achieved
using these registers. In this case care should be taken to
stay within the allowed code range (32 to 99).

A fine correction using three 5-bit DACs, also controlled via
the serial interface, is used to finely tune the gain of the
three channels (fine gain control; see Figs 2 and 9) and to
compensate the channel-to-channel gain mismatch.

With a full scale ADC input, the resolution of the fine
register corresponds to

To use these gain controls correctly, it is recommended to
fix the coarse gain (to have a full-scale ADC input signal)
to within 4 LSB and then adjust it with the fine gain.
The gain is adjusted during HSYNC. During this time the
output signal is not related to the amplified input signal.
The outputs, when the coarse gain system is stable, are
related to the programmed coarse code (see Fig.8).

1

⁄2LSB peak-to-peak variation.

Variable gain amplifier

Three independent variable gain amplifiers are used to
provide, to each channel, a full-scale input range signal to
the 8-bit ADC. The gain adjustment range is designed so
that, for an input range varying from 0.4 to 1.2 V (p-p), the
output signal corresponds to the ADC full-scale input of
1 V (p-p).

To ensure that the gain does not vary over the whole
operating temperature range, an external reference of

2.5 V DC, (V
supplied externally, is used to calibrate the gain at the
beginning of each video line before the clamp pulse using
the following principle.

A differential of 0.156 V (p-p) (1⁄16V
generated internally from the reference voltage (V
During the synchronization part of the video line, the
multiplexer, controlled by the TTL synchronization signal
(HSYNCI, coming from HSYNC; see Fig.1) with a width
equal to one of the video synchronization signals
(e.g. signal coming from a synchronization separator), is
switched between the two amplifiers.

1999 Feb 24 11

with a 100 ppm/°C maximum variation)

ref

) reference signal is

ref

ref

).

ADCs

The ADCs are 8-bit with a maximum clock frequency of
100 Msps. The ADCs input range is 1 V (p-p) full-scale.
One out of range bit exists per channel (ROR, GOR and
BOR). It will be at logic 1 when the signal is out of range
the full scale of the ADCs.

Pipeline delay in the ADCs is 1 clock cycle from sampling
to data output.

The ADCs reference ladders regulators are integrated.

ADC outputs

ADC outputs are straight binary. An output enable pin
(

OE; active LOW) enables the output status between
active and high-impedance (OE = HIGH) to be switched;
it is recommended to load the outputs with a 10 pF
capacitive load. The timing must be checked very carefully
if the capacitive load is more than 10 pF.

Philips Semiconductors Product specification



Triple high-speed Analog-to-Digital
Converter (ADC)

Phase-locked loop

The ADCs are clocked either by an internal PLL locked to
the CKREF clock, (all of the PLL is on-chip except the loop
filter capacitance) or an external clock, CKEXT. Selection
is performed via the serial interface bus.

The reference clock (CKREF) range is between
15 and 280 kHz. Consequently, the VCO minimum
frequency is 12 MHz and the maximum frequency
100 MHz for the TDA8752A/8 and 60 MHz for the
TDA8752A/6. The gain of the VCO part can be controlled
via the serial interface, depending on the frequency range
to which the PLL is locked.

To increase the bandwidth of the PLL, the charge pump
current, controlled by the serial interface, must also be
increased. The relationship between the frequency and
the current is given by the following equation:

---------------------------------- -=
Cz( CP) N+

1

≅ 0.05

K

OIP

f

1



and ξ



n

×=

--- -

-- ­2

f

z

1

f

------ -

n

2π

Where:

= the natural PLL frequency

f

n

KO= the VCO gain
N = the division number
Cz and CP= capacitors of the PLL filter.

The other PLL equation is as follows:

f

=

------------------------------

z

2 π R× Cz×

Where:

fz= loop filter zero frequency
R = the chosen resistance for the filter
ξ = the damping factor.

Different resistances for the filter can be programmed via
the serial interface. To have better performances, the PLL
parameters should be chosen so that:

fn/f

ref

ξ≅1.5.

It is possible to control (independently) the phase of the
ADC clock and the phase of an additional clock output
(which could be used to drive a second TDA8752A).
For this, two serial interface-controlled digital phase-shift
controllers are included (controlled by 5-bit registers,
phase shift controller steps are 11.25° each on the whole
PLL frequency range).

TDA8752A

CKREF is resynchronized, by the synchro block, on the
CKAO clock. The output is CKREFO (LOW during 8 clock
periods). CKAO is the clock at the output of the phase
selector A. This clock can be used as the clocks for CKBO
and CKADCO. The timing is given in Fig.5.

The COAST pin is used to disconnect the PLL phase
frequency detector during the frame flyback or the
unavailability of the CKREF signal. This signal can
normally be derived from the VSYNC signal.

The clock output is able to drive an external 10 pF load
(for the on-chip ADCs).

The PLL can be used in three different methods:

1. The IC can be used as stand-alone with a sampling
frequency of up to 100 MHz for the TDA8752A/8 and
up to 60 MHz for the TDA8752A/6.

2. When an RGB signal is at a pixel frequency exceeding
100 to 200 MHz, it is possible to follow one of the two
possibilities given below:

a) Using one TDA8752A; the sampling rate can be

reduced by a factor of two, by sampling the even
pixels in the even frame and the odd pixels in the
odd frame. The INV pin is used to toggle between
frames.

b) Using two TDA8752As the PLL of the master

TDA8752A is used to drive both ADC clocks.
The PLL of the slave TDA8752A is disconnected
and the CKBO of the master TDA8752A is
connected to pin CKEXT of both TDA8752A.

The master TDA8752A is used to sample the even
pixels and the slave TDA8752A for odd pixels,
using a 180° phase shift between the clocks
(CKADCO pins). The master chip has its INV pin
LOW while the slave chip has its INV pin HIGH,
which guarantees the 180° shift ADC clock drive.
It is then necessary to adjust phase B of the master
chip. Special care should be taken with the quality
of the input signal (input setting time).

If CKREFO output signal at the master chip is
needed, it is possible to use one of the two phase A
values in order to avoid set-up and hold problems
in the SYNCHRO function; e.g.
PHASEA = 100000 and PHASEA = 111111.

1999 Feb 24 12

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

t

CKAO=tCLK(buffer)+tphase selector

t

= either t

CKREFO

CKREF

CKAO

CKREFO

(t

if phase A ≥ 01000 or t

CKAO

CLK(buffer)

= 10 ns and t

CKAO+TCLK(pixel)

phase selector

t

CKAO

t

CKREFO

t

phase selector

= × T

------------------------------ ­2π

if phase A < 01000.

CLK(pixel)

TDA8752A

MBK773

).

Fig.5 Timing.

1999 Feb 24 13

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

COAST CKEXT INV

phase selector A

I

5 bits (Pa)

CKREF

PLL

phase selector B

2

I

C-bus; 5 bits (Pb)

Master TDA8752A

(even pixels)

12 to

100 MHz

2

C-bus;

MUX

2

I

C-bus;

1 bit (Cka)

(Cka = 1)

0°/180°

TDA8752A

CKADCO

CLK

ADC

CKBO

I2C-bus;

1 bit (Ckb)

(Ckb = 1)

CKAO

CKREF

PLL

COAST

12 to

100 MHz

phase selector A

2

I

C-bus;

5 bits (Pa)

phase selector B

2

I

C-bus; 5 bits (Pb)

Slave TDA8752A

(odd pixels)

SYNCHRO

CKEXT INV

MUX

2

I

C-bus;

1 bit (Cka)

(Cka = 1)

SYNCHRO

5 V

0°/180°

CKREFO

CKADCO

CLK
ADC

CKBO

I2C-bus;

1 bit (Ckb)

(Ckb = 0)

CKAO

CKREFO

FCE081

Slave at 180° phase shift with respect to pin CKADCO of the master TDA8752A.

Fig.6 Dual TDA8752A solution for pixel clock rate with a single phase adjustment (100 to 200 MHz).

1999 Feb 24 14

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

I2C-bus and 3-wire serial bus interface

The I2C-bus and 3-wire serial buses control the status of the different control DACs and registers. Control pin DIS
enables or disables the full serial interface function (disable at HIGH level). Four ICs can be used in the same system
and programmed by the same bus. Therefore, two pins (ADD1 and ADD2) are available to set each address respectively,
for use with the I2C-bus interface. All programming is described in Chapter “I2C-bus and 3-wire serial bus interfaces”.

handbook, full pagewidth

video signal

255

digitized

video

signal

code 64
code 0
code −63.5

clamp

programming

handbook, full pagewidth

CLP

coarse

register

value

(67 codes)

N

coarse
code

127

99

32

Fig.7 Clamp definition.

G

(max)

0

0.156 =

V

0.2

ref

16

G

(min)

0.6

MGG368

ADC output

code

255

227

160
128

V

i (p-p)

MGG366

2

Fig.8 Coarse gain control.

1999 Feb 24 15

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

coarse
register

value

(67 codes)

ADC

output code

255

227

N

COARSE

160

128

N

FINE

N

FINE

= 31

G

(max)

= 0

G

NCOARSE

G

(min)

V

ref

MGG367

TDA8752A

Fig.9 Fine gain correction for a coarse gain G

NCOARSE

.

1999 Feb 24 16

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1999 Feb 24 17

2

I

C-BUS AND 3-WIRE INTERFACES

Register definitions

The configuration of the different registers is shown in Table 1.

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

Converter (ADC)

Table 1 I

FUNCTION

NAME

SUBADDR −−−−−−−− X X X Mode Sa3 Sa2 Sa1 Sa0 xxx1 0000
OFFSETR XXXX0000Or7Or6Or5Or4Or3Or2Or1Or001111111
COARSER XXXX0001 X Cr6Cr5Cr4Cr3Cr2Cr1Cr0x010 0000
FINER XXXX0010 X X XFr4Fr3Fr2Fr1Fr0xxx0 0000
OFFSETG XXXX0011Og7Og6Og5Og4Og3Og2Og1Og001111111
COARSEG XXXX0100 X Cg6Cg5Cg4Cg3Cg2Cg1Cg0x010 0000
FINEG XXXX0101 X X XFg4Fg3Fg2Fg1Fg0xxx0 0000
OFFSETB XXXX0110Ob7Ob6Ob5Ob4Ob3Ob2Ob1Ob001111111
COARSEB XXXX0111 X Cb6Cb5Cb4Cb3Cb2Cb1Cb0x010 0000
FINEB XXXX1000 X X XFb4Fb3Fb2Fb1Fb0xxx0 0000
CONTROL XXXX1001Vlevel H level edge Up Do Ip2 Ip1 Ip0 0000 0100
VCO XXXX1010 Z2 Z1Z0Vco1 Vco0 Di11 Di10 Di9 0110 0001
DIVIDER

(LSB)
PHASEA XXXX1100 X Di0CkaPa4Pa3Pa2Pa1Pa0x000 0000
PHASEB XXXX1101 X XCkbPb4Pb3Pb2Pb1Pb0xx00 0000

2

C-bus and 3-wire registers

SUB-ADDRESS BIT DEFINITION

A7 A6 A5 A4 A3 A2 A1 A0 MSB LSB

XXXX1011Di8Di7Di6Di5Di4Di3Di2Di11001 0000

DEFAULT

VALUE

2

All the registers are defined by a subaddress of 8 bits; bit A4 refers to the mode which is used with the I
subaddresses of each register.

The bit mode, used only with the I2C-bus, enables two modes to be programmed:

• If Mode = 0, each register is programmed independently by giving its subaddress and its content

• If Mode = 1, all the registers are programmed one after the other by giving this initial condition (xxx1 1111) as the subaddress state; thus, the registers

are charged following the predefined sequence of 16 bytes (from subaddress 0000 to 1101).

C-bus interface; bits Sa3 to Sa0 are the

TDA8752A

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

OFFSET REGISTER
This register controls the clamp level for the

RGB channels. The relationship between the
programming code and the level of the clamp code is given
in Table 2.

Table 2 Coding

PROGRAMMED

CODE

0 −63.5 underflow
1 −63
2 −62.5

↓↓

127 0 0

↓↓↓

254 63.5 63 or 64
255 64 64

The default programmed value is:

• Programmed code = 127

• Clamp code = 0

• ADC output = 0.

CLAMP CODE ADC OUTPUT

TDA8752A

Table 3 Gain correspondence (COARSE)

N

COARSE

GAIN

32 0.825 1.212
99 2.5 0.4

The default programmed value is as follows:

• N

COARSE

=32

• Gain = 0.825

• Vi to be full-scale = 1.212.

To modulate this gain, the fine register is programmed
using the above equation. With a full-scale ADC input, the

1

fine register resolution is a
(see Table 4 for N

COARSE

⁄2LSB peak-to-peak

= 32).

Table 4 Gain correspondence (FINE)

N

FINE

GAIN

0 0.825 1.212

31 0.878 1.139

The default programmed value is: N

FINE

Vi TO BE

FULL-SCALE

Vi TO BE

FULL-SCALE

=0.

C

OARSE AND FINE REGISTERS

These two registers enable the gain control, the AGC gain
with the coarse register and the reference voltage with the
fine register. The coarse register programming equation is
as follows:

N

–

------------------­32 16×

1+

FINE

FINE

1+

1

×

-----­16

32×

GAIN

=

Where: V

---------------------------------------------­V

ref

N

COARSE

------------------------------------------------­V

512 N

ref

= 2.5 V.

ref

N

=

COARSE



1



–()

The gain correspondence is given in Table 3. The gain is
linear with reference to the programming code (N

FINE

= 0).

C

ONTROL REGISTER

COAST and HSYNC signals can be inverted by setting the
I2C-bus control bits V level and H level respectively. When
V level and H level are set to zero respectively, COAST
and HSYNC are active HIGH.

The bit ‘edge’ defines the rising or falling edge of CKREF
to synchronise the PLL. It will be on the rising edge if the
bit is at logic 0 and on the falling edge if the bit is at logic 1.

The bits Up and Do are used for the test, to force the
charge pump current. These bits have to be logic 0 during
normal use.

The bits Ip0, Ip1 and Ip2 control the charge pump current,
to increase the bandwidth of the PLL, as shown in Table 5.

1999 Feb 24 18

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

Table 5 Charge-pump current control

Ip2 Ip1 Ip0

0 0 0 6.25
0 0 1 12.5
01025
01150
100100
101200
110400
111700

The default programmed value is as follows:

• Charge pump current = 100 µA

• Test bits: no test mode; bits Up and Do at logic 0

• Rising edge of CKREF: bit edge at logic 0

• COAST and HSYNC inputs are active HIGH: V level and

H level at logic 0.

VCO

REGISTER

The bits Z2, Z1 and Z0 enable the internal resistance for
the VCO filter to be selected.

Table 6 VCO register bits

Z2 Z1 Z0

0 0 0 high impedance
0 0 1 128
010 32
011 16
100 8
101 4
110 2
111 1

CURRENT

(µA)

RESISTANCE

(kΩ)

TDA8752A

Table 7 VCO gain control

V

CO1

V

CO0

VCO gain

(MHz/V)

1 0 60 10 to 17
0 1 30 17 to 35
1 0 60 35 to 60
1 1 100 60 to 100

The bits V

CO1

and V

control the VCO gain.

CO0

The default programmed value is as follows:

• Internal resistance = 16 kΩ

• VCO gain = 15 MHz/V.

D

IVIDER REGISTER

This register controls the PLL frequency. The bits are the
LSB bits.

The default programmed value is 0011 0010 0000 = 800.
The MSB bits (Di11, Di10 and Di9) and the LSB bit (Di0)

have to be programmed before the bits Di8 to Di1 to have
the required divider ratio. The bit Di0 is used for the parity
divider number = Di0 = 0 = even number Di0 = 1 = odd
number. It should be noted that if the I2C-bus programming
is done in mode = 1 and the bit Di0 has to be toggled, then
the registers have to be loaded twice to have the update
divider ratio.

OWER-DOWN MODE

P

• When the supply is completely switched off, the
registers are set to their default values; in that event they
have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)

• When the device is in power-down mode, the previously
programmed register values remain unaffected.

PHASEA

AND PHASEB REGISTERS

The bit Cka is logic 0 when the used clock is the PLL clock,
and logic 1 when the used clock is the external clock.

PIXEL CLOCK

FREQUENCY

RANGE (MHz)

1999 Feb 24 19

The bit Ckb is logic 0 when the second clock is not used.
The bits Pa4 to Pa0 and Pb4 to Pb0 are used to program

the phase shift for the clock, CKADCO, CKAO and CKBO
(see Table 8).

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

Table 8 Phase registers bits

Pa4 AND Pb4 Pa3 AND Pb3 Pa2 AND Pb2 Pa1 AND Pb1 Pa0 AND Pb0 PHASE SHIFT (°)

000000

0000111.25

↓↓↓↓↓↓
↓↓↓↓↓↓

11110337.5

11111348.75

The default programmed value is as follows:

• No external clock: CKA at logic 0

• No use of the second clock: CKB at logic 0

• Phase shift for CKAO and CKADCO = 0°

• Phase shift for CKBO = 0°.

2

C-bus protocol

I

2

Table 9 I

C-bus address

A7 A6 A5 A4 A3 A2 A1 A0

10011ADD2 ADD1 0

2

C-bus address of the circuit is 10011 xx0.

The I
Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752As can be used on the same

system, using the addresses for ADD1 and ADD2 with the I2C-bus. The A0 bit must always be equal to logic 0 because
it is not possible to read the data in the register. The timing and protocol for the I2C-bus are standard. Two sequences
are available, see Tables 10 and 11.

Table 10 Address sequence for mode 0; note 1

S IC ADDRESS ACK SUBADDRESS

REGISTER1

Note

1. Where: S = START condition, ACK = acknowledge and P = STOP condition.

Table 11 Address sequence for mode 1; note 1

S IC ADDRESS ACK SUBADDRESS

xxx1 1111

Note

1. Where: S = START condition, ACK = acknowledge and P = STOP condition.

ACK DATA

REGISTER1

(see Table 1)

ACK DATA

REGISTER1

(see Table 1)

ACK SUBADDRESS

REGISTER2

ACK DATA

REGISTER2

ACK to P

ACK to P

1999 Feb 24 20

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1999 Feb 24 21

3-wire protocol

For the 3-wire serial bus the first byte refers to the register address which is programmed. The second byte refers to the data to be sent to the chosen
register (see Table 1). The acquisition is achieved via SEN.

Using the 3-wire interface, an indefinite number of ICs can operate on the same system. Pin SEN is used to validate the circuits.

SEN

t

SCL

= 600 ns

r3W

1199

t

s3W

= 100 ns

t

h3W

= 100 ns

100 ns

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

Converter (ADC)

SDA

XXXXA3A2A1A0XD7D6D5D4D3D2D1D0X

Fig.10 3-wire serial bus protocol.

MGG365

TDA8752A

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

DDD

V

CCO

∆V

V

i(RGB)

I

o

T

stg

T

amb

T

j

CC

analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
logic input voltage −0.3 +7.0 V
output stages supply voltage −0.3 +7.0 V
supply voltage differences

V
V
V
V

CCA
CCO
CCA
CCA

− V

− V

− V

− V

CCD

CCD
DDD
CCO

; V

; V

CCO

CCD

− V

− V

DDD

DDD

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

RGB input voltage range referenced to AGND −0.3 +7.0 V
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 70 °C
junction temperature − 150 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 52 K/W

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

1999 Feb 24 22

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

CHARACTERISTICS

V

= V1 1 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96 = 4.75 to 5.25 V; V

CCA

to DGND (V86) = 4.75 to 5.25 V; V

= V40 referenced to V

DDD

(V41) = 4.75 to 5.25 V; V

SSD

CCO

(or V69, V79 or V85) referenced to OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and V
short circuited together. T

=25°C; unless otherwise specified.

T

amb

= 0 to 70 °C; typical values measured at V

amb

CCA=VDDD=VCCD=VCCO

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
V
V
V
I

CCA

I

DDD

CCA
CCD
DDD
CCO

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
logic supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.75 5.0 5.25 V
analog supply current − 120 − mA
logic supply current for

− 1.0 − mA

I2C-bus and 3-wire

I

CCD

I

CCO

I

CCO(PLL)

I

CCA(PLL)

∆V

CC

P

tot

P

pd

digital supply current − 40 − mA
output stages supply current ramp input; f

= 100 MHz − 6 − mA

CLK

output PLL supply current − 5 − mA
analog PLL supply current − 28 − mA
supply voltage differences

V

− V
V
V
V

CCA
CCO
CCA
CCA

− V

− V

− V

CCD

CCD
DDD
CCO

; V

; V

CCO

CCD

− V

− V

DDD

DDD

total power consumption ramp input; f
power consumption in

= 100 MHz − 1.0 − W

CLK

−0.25 − +0.25 V

−0.25 − +0.25 V

−0.25 − +0.25 V

−0.25 − +0.25 V

− 87 − mW

power-down mode

= V95 referenced

CCD

= V59

= 5 V and

SSD

R, G and B amplifiers

B bandwidth −3 dB; T
t

set

settling time of the block ADC
plus AGC

full-scale (black-to-white)
transition; input signal

amb

settling time<1ns;

G

NCOARSE

coarse gain range V

1 to 99%; T

= 2.5 V; minimum

ref

amb

coarse gain register;
code = 32; (see Fig.8)

maximum coarse gain
register; code = 99;
(see Fig.8)

1999 Feb 24 23

=25°C 250 −−MHz

− 4.5 6 ns

=25°C

−−1.67 − dB

− 8 − dB

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

G

FINE

∆G

amp

I

GC

t

stab

V

i(p-p)

t

r(Vi)

t

f(Vi)

G

E(rms)

Clamps

P

CLP

t

COR1

t

COR2

t

W(CLP)

CLP

E

A

off

fine gain correction range fine register input code = 0;

− 0 − dB

(see Fig.9)
fine register input

−−0.5 − dB

code = 31; (see Fig.9)

/T amplifier gain stability as a

function of temperature

V

= 2.5 V with

ref

100 ppm/°C maximum

−− 200 ppm/°C

variation

gain current −±20 −µA
amplifier gain adjustment

speed
input voltage range

(peak-to-peak value)

HSYNC active; capacitors
on pins 8, 16 and 24 = 22 nF

corresponding to full-scale
output

− 25 − mdB/µs

0.4 − 1.2 V

input voltage rise time fi= 100 MHz; square wave −− 2.5 ns
input voltage fall time fi= 100 MHz; square wave −− 2.5 ns
channel-to-channel gain

matching (RMS value)

precision black level noise on RGB

maximum coarse gain;
T

=25°C

amb

minimum coarse gain;
T

=25°C

amb

− 1 − %

− 2 − %

−1 − +1 LSB

channels = 10 mV (max.)

clamp correction time to within
±10 mV

(RMS value); T
±100 mV black level input

variation; clamp

amb

=25°C

−− 300 ns

capacitor = 4.7 nF

clamp correction time to less
than 1 LSB

±100 mV black level input
variation; clamp

−− 10 lines

capacitor = 4.7 nF

clamp pulse width 500 − 2000 ns
channel-to-channel clamp

−1 − +1 LSB

matching
code clamp reference clamp register input

−−63.5 − LSB

code = 0
clamp register input

− 64 − LSB

code = 255

Phase-locked loop

j

PLL(rms)

long term PLL jitter
(RMS value)

f

= 60 MHz; see Table 13 − 450 − ps

CLK

f

= 100 MHz;

CLK

− 360 − ps

see Table 13

DR divider ratio 100 − 4095
f

ref

reference clock frequency

15 − 280 kHz

range

f

PLL

output clock frequency range 12 − 100 MHz

1999 Feb 24 24

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

COAST(max)

t

recap

t

cap

Φ

step

ADCs

f

s

INL DC integral non linearity from IC analog input to

DNL DC differential non linearity from IC analog input to

ENOB effective number of bits from IC analog input to

Signal-to-noise ratio

S/N signal-to-noise ratio maximum gain;

Spurious free dynamic range

SFDR spurious free dynamic range maximum gain;

Clock timing output (CKADCO, CKBO and CKAO)

η

ext

f

CLK(max)

maximum coast mode time −− 40 lines
PLL recapture time when coast mode is aborted − 3 − lines
PLL capture time in start-up conditions −− 5ms
phase shift step T

=25°C − 11.25 − deg

amb

maximum sampling frequency TDA8752A/6 60 −−MHz

TDA8752A/8 100 −−MHz

−±0.5 ±1.5 LSB
digital output; ramp input;
f

= 100 MHz

CLK

−±0.5 ±1.0 LSB
digital output; ramp input;

= 100 MHz

f

CLK

− 7.4 − bits
digital output; 10 kHz sine
wave input; ramp input;
f

= 100 MHz; note 1

CLK

− 45 − dB
f

= 100 MHz

CLK

minimum gain;

= 100 MHz

f

CLK

− 44 − dB

− 60 − dB

f

= 100 MHz

CLK

minimum gain;
f

= 100 MHz

CLK

− 60 − dB

ADC clock duty cycle 100 MHz output 45 50 55 %
maximum clock frequency 100 −−MHz

Clock timing input (CKEXT)

f

CLK(max)

t

CPH

t

CPL

t

d(CLKO)

maximum clock frequency 100 −−MHz
clock pulse width HIGH 3.6 −−ns
clock pulse width LOW 4.5 −−ns
delay from CKEXT to

CKADCO

INV set to LOW 13.6 14.7 15.2 ns
INV set to HIGH −−ns

1999 Feb 24 25

14.7

+

t

CLK

---------- ­2

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆t-t

Data timing (see Fig.11); f
t

d(s)

t

d(o)

t

h(o)

3-state output delay time; (see Fig.12)
t

dZH

t

dZL

t

dHZ

t

dLZ

PLL clock output

V

OL

V

OH

I

OL

I

OH

) between samples operated in

d(CLKO

the same supply and
temperature conditions

CLK

sampling delay time referenced to CKADCO −− − ns
output delay time −−3.3 −2.6 ns
output hold time 4.6 5.5 − ns

output enable HIGH − 12 − ns
output enable LOW − 10 − ns
output disable HIGH − 50 − ns
output disable LOW − 65 − ns

LOW-level output voltage Io=1mA − 0.3 0.8 V
HIGH-level output voltage Io= −1 mA 2.4 3.5 − V
LOW-level output current VOL= 0.4 V − 2 − mA
HIGH-level output current VOH= 2.7 V −−0.4 − mA

− 0.1 0.3 ns

= 100 MHz; CL= 10 pF; note 2

ADC data outputs

V

OL

V

OH

I

OL

I

OH

LOW-level output voltage Io=1mA − 0 0.8 V
HIGH-level output voltage Io= −1 mA 2.4 V

CCD

− V
LOW-level output current VOL= 0.4 V − 2 − mA
HIGH-level output current VOH= 2.7 V −−0.4 − mA

TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP)

V

IL

V

IH

LOW-level input voltage −− 0.8 V
HIGH-level input voltage 2.0 −−V

IILLOW-level input current VIL= 0.4 V 400 −−µA
IIHHIGH-level input current VIH= 2.7 V −− 100 µA
Z

i

C

i

input impedance − 4 − kΩ
input capacitance − 4.5 − pF

3-wire serial bus

t

rst

reset time of the chip before

− 600 − ns

3-wire communication

t

su

t

h

data set-up time − 100 − ns
data hold time − 100 − ns

1999 Feb 24 26

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2

I

C-bus; see note 3

f

SCL

t

BUF

t

HD;STA

t

SU;STA

t

CKL

t

CKH

t

SU;DAT

t

HD;DAT

t

r

t

f

t

SU;STOP

C

L(bus)

clock frequency 0 − 100 kHz
time the bus must be free

4.7 −−µs
before new transmission can
start

start condition hold time 4.0 −−µs
start condition set-up time repeated start 4.7 −−µs
LOW-level clock period 4.7 −−µs
HIGH-level clock period 4.0 −−µs
data set-up time 250 −−ns
data hold time 0 −−ns
SDA and SCL rise time for f
SDA and SCL fall time for f

= 100 kHz −− 1.0 µs

SCL

= 100 kHz −− 300 ns

SCL

stop condition set-up time 4.0 −−µs
capacitive load for each bus

−− 400 pF
line

Notes

1. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST
frequency). Conversion-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

2. Output data acquisition is available after the maximum delay time t

, which is the time during which the data is

d(o)

available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then
be rechecked.

3. The I2C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of
400 kbit/s (400 kHz).

handbook, full pagewidth

CKADCO

DATA
R0 to R7, ROR
G0 to G7, GOR
B0 to B7, BOR

V

lN

n

I

n − 1

t

CPH

t

d(s)

sample N

I

n

sample N + 1

t

CPL

t

d(o)

I

n + 1

sample N + 2

t

h(o)

I

n + 2

50 % = 1.4 V

2.4 V

1.4 V

0.4 V

MGL103

Fig.11 Timing diagram.

1999 Feb 24 27

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

OE

output

data

output

data

V

CCD

t

dLZ

LOW

10%

HIGH

t

dZL

handbook, full pagewidth

50%

t

dHZ

HIGH

90%

LOW

TDA8752A

50%

t

dZH

50%

3.3 kΩ

10 pF

TDA8752A

S1

V

CCD

tOE= 100 kHz.

Fig.12 Timing diagram and test conditions of 3-state output delay time.

Table 12 Test conditions for Fig.12

TEST SWITCH S1

t

dLZ

t

dZl

t

dHZ

t

dZH

V

CCD

V

CCD

GND
GND

OE

FCE170

1999 Feb 24 28

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1999 Feb 24 29

Table 13 Examples of PLL settings and performance; note 1

VIDEO

STANDARDS

CGA: 640 × 200 15.75 14.3 912 15 150 1 200 4 −− 1.2
VGA: 640 × 480 31.5 25.2 800 30 150 1 400 2 610 3.6 0.7
VESA: 800 × 600 48.08 50 1040 60 150 1 700 1 480 2.9 0.55
VESA: 1024 × 768 60.02 78.8 1312 100 150 1 700 1 380 2.3 0.3
SUN: 1152 × 900 66.67 100 1500 100 150 1 700 1 360 2.2 0.3

Notes

1. Values measured at V

2. PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.

3. Measured between 0 and 70 °C.

f

(kHz)

ref

CCA=VDDD=VCCD=VCCO

f

CLK

(MHz)

N

KO

(MHz/V)CZ(nF)CP(nF)

= 5 V and T

amb

=25°C.

IP (µA)

(kΩ)

LONG TIME JITTER

Z

ps (RMS) ns (p-p)

(2)

PLL PHASE DRIFT

(ns)

(3)

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

Converter (ADC)

TDA8752A

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

APPLICATION INFORMATION

handbook, full pagewidth

150 nF

CZ

V

CCA(PLL)

n.c.

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

n.c.

DEC2

V

ref

DEC1

n.c.

RAGC

RBOT

RCLP
RDEC
CCAR

RIN

GAGC
GBOT

GCLP
GDEC
CCAG

GIN

BAGC

BBOT

BCLP

CCAB

BIN

n.c.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 40 4132 4233 4334 4435 4536 4637 4738 4839 49 50

2.5 V

RIN

GIN

BIN

10 nF

4.7 nF

100 nF

75 Ω or 50 Ω

10 nF

4.7 nF

100 nF

75 Ω or 50 Ω

10 nF

4.7 nF

100 nF

75 Ω or 50 Ω

10 nF

1.5 nF

22 nF

10 nF

22 nF

10 nF

22 nF

10 nF

RGAINC

V

AGNDR

GGAINC

V

AGNDG

BGAINC

BCDEC

V

AGNDB

1 nF

CP

AGNDPLL

V

CCD

COAST

CKREF

CKEXT

HSYNC

INV

TDA8752A

PWDWN

CLP

OE

V

CCO(PLL)

DGND

CKBO

CKADCO

TDA8752A

OGNDPLL

CKAO

CKREFO

80

V

CCOR

79

R7

78

R6

77

R5

76

R4

75

R3

74

R2

73

R1

72

R0

71

OGNDR

70

V

CCOG

69

G7

68

G6

67

G5

66

G4

65

G3

64

G2

63

G1

62

G0

61

OGNDG

60

V

CCOB

59

B7

58

B6

57

B5

56

B4

55

B3

54

B2

53

B1

52

n.c.

51

SEN

SDA

V

DDD

V

DDD

V

SSD

4.7
kΩ

SCL

V

DDD

n.c.

4.7
kΩ

n.c.

ADD1

TCK

2

C/3W

ADD2

I

All supply pins have to be decoupled, with two capacitors:
one for high frequencies (approximately 1 nF) and one for the low frequencies (approximately 100 nF or higher).

DIS

TDO

Fig.13 Application diagram.

1999 Feb 24 30

GOR

BORRORn.c.

B0

n.c.

OGNDB

FCE082

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

PACKAGE OUTLINE

QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

80 51

81

50

Z

A

E

TDA8752A

SOT317-2

pin 1 index

100

1

w M

b

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.20

0.25

0.05

2.90

2.65

0.25

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

p

D

H

D

cE

0.25

0.14

D

20.1

19.9

p

0.40

0.25

0 5 10 mm

(1)

(1) (1)(1)

14.1

13.9

30

Z

D

scale

eH

H

24.2

0.65

23.6

31

D

e

w M

b

p

B

E

18.2

17.6

E

v M

A

v M

B

LL

p

1.0

0.6

A

H

E

2

A

A

1

detail X

Zywv θ

Z

E

D

0.8

0.15 0.10.21.95

0.4

1.0

0.6

(A )

3

θ

L

p

L

o

7

o

0

OUTLINE

VERSION

SOT317-2

IEC JEDEC EIAJ

REFERENCES

1999 Feb 24 31

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

TDA8752A

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Feb 24 32

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)
(5)

SOLDERING METHOD

(1)

suitable

suitable
suitable

.

1999 Feb 24 33

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital

TDA8752A

Converter (ADC)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1999 Feb 24 34

Philips Semiconductors Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

NOTES

1999 Feb 24 35

Philips Semiconductors – a worldwide company

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Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
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20124 MILANO, Tel. [phone], Fax. [phone]

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Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
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Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1999 SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545004/750/03/pp36 Date of release: 1999 Feb 24 Document order number: 9397 750 05307