Datasheet tda8703 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8703

8-bit high-speed analog-to-digital converter

Product speciﬁcation Supersedes data of April 1993 File under Integrated Circuits, IC02

1996 Aug 26

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter

FEATURES

• 8-bit resolution

• Sampling rate up to 40 MHz

• High signal-to-noise ratio over a large analog input

frequency range (7.1 effective bits at 4.43 MHz full-scale input)

• Binary or two's complement 3-state TTL outputs

• Overflow/underflow 3-state TTL output

• TTL compatible digital inputs

• Low-level AC clock input signal allowed

• Internal reference voltage generator

• Power dissipation only 290 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

ORDERING INFORMATION

TDA8703

APPLICATIONS

• General purpose high-speed analog-to-digital conversion

• Digital TV, IDTV

• Subscriber TV decoder

• Satellite TV decoders

• Digital VCR.

GENERAL DESCRIPTION

The TDA8703 is an 8-bit high-speed Analog-to-Digital Converter (ADC) for video and other applications. It converts the analog input signal into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible, although a low-level AC clock input signal is allowed.

TYPE

NUMBER

TDA8703 DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1 TDA8703T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

NAME DESCRIPTION VERSION

PACKAGE

1996 Aug 26 2

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

ILE DC integral linearity error −−±1 LSB DLE DC differential linearity error −−±1/2 LSB AILE AC integral linearity error note1 −−±2 LSB B −3 dB bandwidth note 2; f f

CLK/fCLK

P

tot

analog supply voltage 4.5 5.0 5.5 V digital supply voltage 4.5 5.0 5.5 V output stages supply voltage 4.2 5.0 5.5 V analog supply current − 28 36 mA digital supply current − 19 25 mA output stages supply current − 11 14 mA

= 40 MHz − 19.5 − MHz

CLK

maximum conversion rate note 3 40 −−MHz total power dissipation − 290 415 mW

Notes

1. Full-scale sinewave (f

= 4.4 MHz; f

i

CLK

; f

CLK

= 27 MHz).

2. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).

3. The circuit has two clock inputs CLK and CLK. There are four modes of operation: a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling

on the LOW-to-HIGH transition of the input clock signal.

b) TTL (mode 2); CLK decoupled to DGND by a capacitor.CLK input is TTL threshold voltage of 1.5 V and sampling

on the HIGH-to-LOW transition of the input clock signal.

c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V

(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.

d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF

capacitor.

1996 Aug 26 3

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

BLOCK DIAGRAM

clock inputs

handbook, full pagewidth

V

RT

analog

voltage input

V

RB

V

CCA

7

STABILIZER

5DEC

CLK

CLOCK DRIVER

CLK

V 181716

CCD

TC CE

21 22

TDA8703 TDA8703T

12

D7

MSB

D6

13

D5

14

D4

89VI

4

ANALOG - TO - DIGITAL

CONVERTER

3 AGND

20 DGND

LATCHES

OVERFLOW / UNDERFLOW

LATCH

TTL OUTPUTS

TTL OUTPUT

15 23 24 D2

19

11

MGA015

data outputs

D3

1

D1

2

D0

LSB

V

CCO

overflow / underflow

output

analog ground digital ground

Fig.1 Block diagram.

1996 Aug 26 4

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

PINNING

SYMBOL PIN DESCRIPTION

D1 1 data output; bit 1 D0 2 data output; bit 0 (LSB) AGND 3 analog ground V

RB

DEC 5 decoupling input (internal stabilization

n.c. 6 not connected V

CCA

VI 8 analog voltage input V

RT

n.c. 10 not connected O/UF 11 overﬂow/underﬂow data output D7 12 data output; bit7 (MSB) D6 13 data output; bit6 D5 14 data output; bit5 D4 15 data output; bit4 CLK 16 clock input CLK 17 complementary clock input V

CCD

V

CCO

DGND 20 digital ground TC 21 input for two's complement output (TTL

CE 22 chip enable input (TTL level input,

D3 23 data output; bit 3 D2 24 data output; bit 2

4 reference voltage bottom (decoupling)

loop decoupling)

7 positive supply voltage for analog

circuits (+5 V)

9 reference voltage top (decoupling)

18 positive supply voltage for digital

circuits (+5 V)

19 positive supply voltage for output

stages (+5 V)

level input, active LOW)

active LOW)

handbook, halfpage

1

D1

2

D0

V

RB

DEC

n.c.

CCA

V

RT

n.c.

O/UF

D7

VI

3 4 5 6

TDA8703/

TDA8703T

7 8

9 10 11 12

MLB034

AGND

V

Fig.2 Pin configuration.

24

D2 D3

23 22

CE TC

21

DGND

20

V

CCO

19

V

CCD

18 17

CLK CLK

16

D4

15

D5

14

D6

13

1996 Aug 26 5

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

V

CCA

V

CCO

V

CCA

V

VI

V

CLK/VCLK

I

O

T

stg

T

amb

T

j

− V

analog supply voltage −0.3 +7.0 V digital supply voltage −0.3 +7.0 V output stages supply voltage −0.3 +7.0 V supply voltage differences −1.0 +1.0 V

CCD

supply voltage differences −1.0 +1.0 V

CCD

supply voltage differences −1.0 +1.0 V

CCO

input voltage range referenced to AGND −0.3 +7.0 V AC input voltage for switching

note 1; referenced to DGND − 2.0 V

(peak-to-peak value) output current − +10 mA storage temperature −55 +150 °C operating ambient temperature 0 +70 °C junction temperature − +125 °C

Notes

1. The circuit has two clock inputs CLK and

CLK. There are four modes of operation:

a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling

on the LOW-to-HIGH transition of the input clock signal.

b) TTL (mode 2); CLK decoupled to DGND by a capacitor.CLK input is TTL threshold voltage of 1.5 V and sampling

on the HIGH-to-LOW transition of the input clock signal.

c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V

(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.

d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF

capacitor.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL RESISTANCE

SYMBOL PARAMETER VALUE UNIT

R

th j-a

from junction to ambient in free air

SOT101-1 55 K/W SOT137-1 75 K/W

1996 Aug 26 6

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

CHARACTERISTICS

V

CCA=V7−V3

DGND shorted together; V V

− V

CCA

V

CCA=VCCD=VCCO

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Inputs

= 4.5 V to 5.5 V; V

= −0.5 V to +0.5 V; T

CCD

= 5 V and T

CCA

CCD=V18

− V

CCD

amb

− V20= 4.5 V to 5.5 V; V

= −0.5 V to +0.5 V; V

CCO

− V

CCO=V19

= −0.5 V to +0.5 V;

CCD

− V20= 4.5 V to 5.5 V; AGND and

=0°C to +70 °C; unless otherwise speciﬁed (typical values measured at

=25°C).

analog supply voltage 4.5 5.0 5.5 V digital supply voltage 4.5 5.0 5.5 V output stages supply voltage 4.2 5.0 5.5 V analog supply current − 28 36 mA digital supply current − 19 25 mA output stage supply current all outputs LOW − 11 14 mA

C

LOCK INPUT CLK AND CLK (note 1; REFERENCED TO DGND)

V

IL

V

IH

I

IL

I

IH

Z

i

C

i

− V

V

CLK

LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current V HIGH level input current V

input impedance f input capacitance f AC input voltage for switching

CLK

(peak-to-peak value) TC AND CE (REFERENCED TO DGND) V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.8 V

HIGH level input voltage 2.0 − V

LOW level input current VIL= 0.4 V −400 −−µA

HIGH level input current VIH= 2.7 V −−20 µA VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) V

VI(B)

V

VI(0)

V

OS(B)

V

VI(T)

V

VI(255)

V

OS(T)

V

VI(p-p)

I

IL

I

IH

Z

i

C

i

input voltage (bottom) 1.33 1.41 1.48 V

input voltage output code = 0 1.455 1.55 1.635 V

offset voltage (bottom) V

input voltage (top) 3.2 3.36 3.5 V

input voltage output code = 255 3.115 3.26 3.385 V

offset voltage (top) V

input voltage amplitude (peak-to-peak value) 1.66 1.71 1.75 V

LOW level input current VVI= 1.4 V − 0 −µA

HIGH level input current VVI= 3.6 V 60 120 180 µA

input impedance fi= 1 MHz − 10 − kΩ

input capacitance fi= 1 MHz − 14 − pF

CCD CLK/VCLK CLK/VCLK

V

CLK/VCLK=VCCD

CLK/fCLK CLK/fCLK

= 0.4 V −400 −−µA = 0.4 V −−100 µA

−−300 µA =10MHz − 4 − kΩ =10MHz − 4.5 − pF

note 1; DC level = 1.5 V 0.5 − 2.0 V

CCD

VI(0)

VI(T)

− V

VI(B)

VI(255)

0.125 − 0.155 V

0.085 − 0.115 V

V

1996 Aug 26 7

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Reference resistance

R

ref

reference resistance VRTto V

RB

Outputs

D

IGITAL OUTPUTS (D7 - D0) (REFERENCED TO DGND)

V

OL

V

OH

I

OZ

LOW level output voltage IO= 1 mA 0 − 0.4 V HIGH level output voltage IO= −0.4 mA 2.7 − V output current in 3-state mode 0.4 V < VO< V

CCD

Switching characteristics (note 2; see Fig.3) f

CLK/fCLK

Analog signal processing (f

maximum clock frequency 40 −−MHz

= 40 MHz)

CLK

B −3 dB bandwidth note 3 − 19.5 − MHz G

d

φ

d

f

1

f

all

differential gain note 4 − 0.6 − % differential phase note 4 − 0.8 − deg fundamental harmonics (full-scale) fi= 4.43 MHz −−0dB

harmonics (full-scale), all components fi= 4.43 MHz −−55 − dB SVRR1 supply voltage ripple rejection note 5 −−28 −25 dB SVRR2 supply voltage ripple rejection note 5 − 1 2.5 %/V

− 220 −Ω

V

CCD

−20 − +20 µA

Transfer function

ILE DC integral linearity error −−±1 LSB DLE DC differential linearity error −−±1/2 LSB AILE AC integral linearity error note 6 −−±2 LSB EB effective bits f

Timing (note 7; see Figs 3 to 6; f t

dS

t

HD

t

dLH

t

dHL

t

dZH

t

dZL

t

dHZ

t

dLZ

sampling delay −−2ns

output hold time 6 −−ns

output delay time LOW-to-HIGH transition − 810ns

output delay time HIGH-to-LOW transition − 16 20 ns

3-state output delay times enable-to-HIGH − 19 25 ns

3-state output delay times enable-to-LOW − 16 20 ns

3-state output delay times disable-to-HIGH − 14 20 ns

3-state output delay times disable-to-LOW − 912ns

= 40 MHz)

CLK

= 4.43 MHz − 7.1 − bits

i

1996 Aug 26 8

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

Notes

1. The circuit has two clock inputs CLK and CLK. There are four modes of operation: a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling

on the LOW-to-HIGH transition of the input clock signal.

b) TTL (mode 2); CLK decoupled to DGND by a capacitor.CLK input is TTL threshold voltage of 1.5 V and sampling

on the HIGH-to-LOW transition of the input clock signal.

c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V

(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.

d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF

capacitor.

2. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 2 ns.

3. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at the input).

4. Low frequency ramp signal (V fi= 4.43 MHz) at the input.

5. Supply voltage ripple rejection: a) SVRR1; variation of the input voltage producing output code 127 for supply voltage variation of 1 V:

SVRR1 = 20 log (∆V

VI(127)

b) SVRR2; relative variation of the full-scale range of analog input for a supply voltage variation of 1 V:

SVR2 = {∆(V

VI(0)

− V

VI(255)

6. Full-scale sinewave (fi= 4.4 MHz; f

7. Output data acquisition: a) Output data is available after the maximum delay of t

= 1.8 V and fi= 15 kHz) combined with a sinewave input voltage (V

VI(p-p)

/ ∆V

)/(V

CCA

VI(0)

CLK

)

− V

; f

CLK

)} ÷∆V

VI(255)

= 27 MHz).

CCA

dHL

.

and t

dLH

.

VI(p-p)

= 0.5 V,

1996 Aug 26 9

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

Table 1 Output coding and input voltage (referenced to AGND; typical values)

BINARY OUTPUT BITS TWO'S COMPLEMENT OUTPUT BITS

STEP V

VI(p-p)

Underﬂow <1.55 1 0 000000010000000 0 1.55 0 0 000000010000000 1 − 0 0000000110000001

. . . ................

254 . 0 1111111001111110 255 3.26 0 1 111111101111111 Overﬂow >3.26 1 1 111111101111111

Table 2 Mode selection

TC CE D7-D0 O/UF

(1)

X

0 0 active; two’s complement active 1 0 active; binary active

O/UF D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 high impedance high impedance

Note

1. X = don’t care.

handbook, full pagewidth

CLK

D0 - D7

1.3 V

t

HD

sample N + 1

sample N + 2

2.4 V

0.4 V

MEA105

sample N

VI

t

dS

1.3 V data N + 1data N – 1 data N

t

dLH

t

dHL

Fig.3 Timing diagram.

1996 Aug 26 10

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

handbook, full pagewidth

handbook, halfpage

input

data

outputs

D0 to D7

CE

15 pF

t

dHZ

t

dLZ

Fig.4 3-state delay timing diagram.

handbook, halfpage

V

CCO

2 kΩ

IN916

or

IN3064

t

dZH

t

dZL

D0 to D7

reference level (1.4 V)

2.4 V

0.4 V

MLB035 - 1

C5

kΩ

V

CCO

2 kΩ

S1

IN916

or

IN3064

MGD691

DGND

Fig.5 Load circuit for timing measurement; data

outputs (CE = LOW).

1996 Aug 26 11

S2

MBB955

DGND

Fig.6 Load circuit for timing measurement;

3-state outputs (CE: fi= 1 MHz; VVI= 3 V); see Table 3.

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

Table 3 Mode selection

TIMING MEASUREMENT SWITCH S1 SWITCH S2 CAPACITOR

t

dZH

t

dZL

t

dHZ

t

dLZ

INTERNAL PIN CONFIGURATIONS

open closed 15 pF closed open 15 pF closed closed 5 pF closed closed 5 pF

handbook, halfpage

V

CCO

D7 to D0

O/U

DGND

MGD692

Fig.7 TTL data and overflow/underflow outputs.

handbook, halfpage

V

CCO

handbook, halfpage

V

CCA

V

I

AGND

handbook, halfpage

V

CCD

(x 90)

MLB037

Fig.8 Analog inputs.

CE

DGND

MGD693

Fig.9 CE (3-state) input.

1996 Aug 26 12

TC

DGND

MLB039

Fig.10 TC (two’s complement) input.

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

handbook, full pagewidth

V

CCA

DEC

AGND

Fig.11 VRB, VRT and DEC.

MCD188

V

RT

V

RB

V

handbook, full pagewidth

CCD

CLK

30 kΩ 30 kΩ

DGND

Fig.12 CLK and CLK inputs.

1996 Aug 26 13

MCD189 - 1

V

ref

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

APPLICATION INFORMATION

Additional application information will be supplied upon request (please quote number FTV/8901).

handbook, full pagewidth

47 pF

4.7 µF

4.7 µF 22 nF

AGND

1

D1 D2

2

D0

AGND

V

O / UF

V

RB

DEC

n.c.

CCA

V

n.c.

RT

D7

3

4

5

6

TDA8703 TDA8703T

7

VI

8

9

10

11

12

24

D3

23

CE

22

TC

21

DGND

20

V

CCO

19

V

CCD

18

CLK

17

CLK

16

D4

15

D5

14

D6

13

22 nF

22 Ω

DGND

(1)

100 pF

5 V

22 nF

MGA014 - 1

CLK should be decoupled to the DGND with a 100 nF capacitor, if a TTL signal is used on CLK (see Chapter “Characteristics”, note 1). CLK and CLK can be used in a differential mode (see Chapter “Characteristics”, note 1). VRB and VRT are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity. If it is required to use the TDA8703 in a parallel system configuration, the references (VRB and VRT) of each TDA8703 can be connected together.

Code 0 will be identical and code 255 will remain in the 1 LSB variation for each TDA8703. Analog and digital supplies should be separated and decoupled. Pins 6 and 10 should be connected to AGND in order to prevent noise influence. (1) It is recommended to decouple V

load device.

through a 22 Ω resistor especially when the output data of the TDA8703 interfaces with a capacitive CMOS

CCO

Fig.13 Application diagram.

1996 Aug 26 14

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

PACKAGE OUTLINES

DIP24: plastic dual in-line package; 24 leads (600 mil)

D

seating plane

L

Z

24

pin 1 index

e

b

SOT101-1

M

E

A

2

A

1

w M

b

1

13

E

c

(e )

1

M

H

1

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE VERSION

SOT101-1

1 2

min.

max.

0.066

0.051

IEC JEDEC EIAJ

051G02 MO-015AD

1.7

1.3

b

1

0.53

0.38

0.021

0.015

0.32

0.23

0.013

0.009

REFERENCES

cD E e M

32.0

31.4

1.26

1.24

1996 Aug 26 15

12

14.1

13.7

0.56

0.54

(1)(1)

e

L

3.9

3.4

EUROPEAN

PROJECTION

M

E

15.80

15.24

0.62

0.60

17.15

15.90

0.68

0.63

1

0.15

0.13

H

w

0.252.54 15.24

0.010.10 0.60

ISSUE DATE

92-11-17 95-01-23

Z

max.

2.25.1 0.51 4.0

0.0870.20 0.020 0.16

(1)

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

SO24: plastic small outline package; 24 leads; body width 7.5 mm

D

c

y

Z

24

pin 1 index

1

e

13

12

w M

b

p

SOT137-1

E

H

E

Q

A

2

A

1

L

p

L

detail X

(A )

A

X

v M

A

3

θ

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE VERSION

SOT137-1

A

A1A2A3b

max.

0.30

2.65

0.10

0.012

0.10

0.004

p

2.45

2.25

0.096

0.089

IEC JEDEC EIAJ

075E05 MS-013AD

0.25

0.01

0.49

0.36

0.019

0.014

0.32

0.23

0.013

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

15.6

7.6

7.4

0.30

0.29

1.27

0.050

15.2

0.61

0.60

REFERENCES

1996 Aug 26 16

eHELLpQ

10.65

10.00

0.42

0.39

1.4

0.055

1.1

0.4

0.043

0.016

1.1

1.0

0.043

0.039

PROJECTION

0.25

0.25 0.1

0.01

EUROPEAN

ywv θ

Z

0.9

0.4

8

0.004

ISSUE DATE

0.035

0.016

92-11-17

95-01-24

0

o o

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

SOLDERING Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“IC Package Databook”

(order code 9398 652 90011).

DIP

OLDERING BY DIPPING OR BY WA VE

S The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T

stg max

). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

R Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING Reflow soldering techniques are suitable for all SO

packages.

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.

AVE SOLDERING

W Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.

• The longitudinal axis of the package footprint must be parallel to the solder flow.

• The package footprint must incorporate solder thieves at the downstream end.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

EPAIRING SOLDERED JOINTS

R Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

1996 Aug 26 17

Philips Semiconductors Product speciﬁcation

8-bit high-speed analog-to-digital converter TDA8703

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1996 Aug 26 18