Product specification
Supersedes data of 1998 May 29
File under Integrated Circuits, IC02
1999 Aug 30
Page 2
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
FEATURES
• Direct conversion QPSK demodulation (Zero IF)
• 920 to 2200 MHz range
• On-chip loop-controlled 0 or 90° phase shifter
• Variable gain on RF input
• 60 MHz, at −1 dB, bandwidth for baseband
I and Q amplifiers
• Local oscillator output to PLL satellite or terrestrial
• 5 V supply voltage.
APPLICATIONS
• Direct Broadcasting Satellite (DBS) QPSK
demodulation
• Digital VideoBroadcasting (DVB) QPSK deSupersedes
data of 1998 May 29
modulation.
GENERAL DESCRIPTION
The direct conversion QPSK demodulator is the front-end
receiver dedicated to digital TV broadcasting, satisfying
both DVB and DBS TV standards. The 920 to 2200 MHz
wide range oscillator covers American, European and
Asian satellite bands as well as the future SMA-TV US
standard.
Accurate QPSK demodulation is ensured by the on-chip
loop-controlled phase shifter. The Zero-IF concept
discardstraditionalIFfilteringand intermediate conversion
techniques. It also simplifies the signal path.
The baseband I and Q signal bandwidth only depends, to
a certain extent, on the external filter used in the
application.
Optimum signal level is guaranteed by a gain-controlled
amplifier at the RF input. The GAIN pin sets the gain for
both I and Q channels, providing a 30 dB range.
The chip also offers a selectable internal LO prescaler
(divide-by-2) and buffer that has been designed to be
compatible with the input of a terrestrial or satellite
frequency synthesizer.
QUICK REFERENCE DATA
SYMBOLPARAMETERMIN.TYP.MAX.UNIT
V
CC
supply voltage4.755.005.25V
∆Φquadrature error−−3deg
f
V
T
osc
o(p-p)
amb
oscillator frequency920−2200MHz
output voltage (peak-to-peak value)−0.75−V
operating ambient temperature−20−+85°C
ORDERING INFORMATION
TYPE
NUMBER
NAMEDESCRIPTIONVERSION
PACKAGE
TDA8060TSSSOP24plastic shrink small outline package; 24 leads; body width 5.3 mmSOT340-1
1999 Aug 302
Page 3
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1999 Aug 303
BLOCK DIAGRAM
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
handbook, full pagewidth
RFA 8
RFB 7
COMGAIN 4
PEN 5
V
CC(RF)
6
LNA
QUADRATURE
GENERATOR
20
LOOUT21LOOUTC
RFGND
9
V
CC(LO1)
16
LOGND1
15
CONVERSION STAGE
×
×
STABILIZED LO
PLL AND
AMPLIFIER
OSCILLATORDIVIDE-BY-2
18
TKA17TKB
V
19
100 MHz
100 MHz
CC(LO2)
LOGND2
22
I CONVERTER
SYM
ASYMAMP
Q CONVERTER
ASYMSYM
TDA8060TS
LOW-PASS
FILTER
IOUT2IBBIN
BASEBAND
11
QOUT
LOW-PASS
FILTER
24
STAGE
AMP
13
QBBIN
12
1
IBBOUT23
QBBOUT14
V
CC(BB1)
V
CC(BB2)
BBGND13
BBGND210
MGM318
Fig.1 Block diagram.
Page 4
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
PINNING
SYMBOLPINDESCRIPTION
V
CC(BB1)
IOUT2‘I’ output from demodulator
BBGND13ground 1 for baseband circuit
COMGAIN4RF amplifier gain control input
PEN5prescaler enable
V
CC(RF)
RFB7RF signal input B
RFA8RF signal input A
RFGND9ground for RF circuit
BBGND210ground 2 for baseband circuit
QOUT11‘Q’ output from demodulator
V
CC(BB2)
QBBIN13‘Q’ baseband amplifier input
QBBOUT14‘Q’ baseband amplifier output
LOGND115ground 1 for local oscillator circuit
V
CC(LO1)
TKB17tank circuit input B
TKA18tank circuit input A
V
CC(LO2)
LOOUT20local oscillator output to
LOOUTC21
LOGND222ground 2 for local oscillator circuit
IBBOUT23‘I’ baseband amplifier output
IBBIN24‘I’ baseband amplifier input
1supply voltage 1 for baseband
circuit (+5 V)
6supply voltage for RF circuit (+5 V)
12supply voltage 2 for baseband
circuit (+5 V)
16supply voltage 1 for local oscillator
circuit (+5 V)
19supply voltage 2 for local oscillator
circuit (+5 V)
synthesizer divided or not
according to PEN voltage
handbook, halfpage
V
COMGAIN
V
IOUT
PEN
RFB
RFA
QOUT
1
2
3
4
5
6
TDA8060TS
7
8
9
10
11
12
CC(BB1)
BBGND1
V
CC(RF)
RFGND
BBGND2
CC(BB2)
Fig.2 Pin configuration.
MGM317
24
23
22
21
20
19
18
17
16
15
14
13
IBBIN
IBBOUT
LOGND2
LOOUTC
LOOUT
V
CC(LO2)
TKA
TKB
V
CC(LO1)
LOGND1
QBBOUT
QBBIN
1999 Aug 304
Page 5
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOLPARAMETERMIN.MAX.UNIT
V
CC
V
i(max)
t
sc(max)
T
amb
T
stg
T
j
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
supply voltage−0.3+6.0V
maximum input voltage on all pins−0.3V
CC
V
maximum short-circuit time−10s
operating ambient temperature−20+85°C
storage temperature−55+150°C
junction temperature−150°C
SYMBOLPARAMETERCONDITIONSVALUEUNIT
R
th(j-a)
thermal resistance from junction to ambientin free air120K/W
DC input voltage on pin RFA−0.9−V
DC input voltage on pin RFB−0.9−V
DC output voltage on pin IOUT−2.0−V
DC output voltage on pin QOUT−2.0−V
Quadrature generator
V
O(LOOUT)
V
O(LOOUTC)
DC output voltage on pin LOOUT−4.7−V
DC output voltage on pin LOOUTC−4.7−V
Baseband stage
V
I(IBBIN)
V
I(QBBIN)
V
O(IBBOUT)
V
O(QBBOUT)
DC input voltage on pin IBBIN−2.5−V
DC input voltage on pin QBBIN−2.5−V
DC output voltage on pin IBBOUT−2.5−V
DC output voltage on pin QBBOUT−2.5−V
1999 Aug 305
Page 6
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
AC CHARACTERISTICS
T
=25°C; VCC= 5 V; unless otherwise specified.
amb
SYMBOLPARAMETERCONDITIONSMIN.TYP. MAX.UNIT
Quadrature generator
f
osc
ΦN
osc
∆Φabsolute quadrature errornote 2−03deg
f
LOOUT
V
o(diff)(LOOUT)
Z
o(diff)(LOOUT)
Conversion stage
R
i(diff)
L
i(diff)
P
i(max)
P
i(min)
∆Gv/∆V
∆G
∆t
∆t
t
B
B
B
B
Z
Z
V
V
R
R
(slope)
v(I-Q)
d(g)(RF-IOUT)
d(g)(RF-QOUT)
d(g)(I-Q)(40)
(−1dB)(RF-IOUT)
(−1dB)(RF-QOUT)
(−3dB)(RF-IOUT)
(−3dB)(RF-QOUT)
o(IOUT)
o(QOUT)
o(IOUT)
o(QOUT)
oL(IOUT)
oL(QOUT)
oscillator frequency range920−2200 MHz
oscillator phase noiseat 10 kHz offset;
−−80−75dBc/Hz
note 1
output frequencyV
differential output voltage at pin LOOUTRL= 100 Ω
=0V−f
PEN
V
PEN=VCC
−MHz
osc
−
1
⁄2f
−MHz
osc
−30−22−dBm
differential
differential output impedance at pin LOOUT−60−Ω
series real part of differential input
note 3−34−Ω
impedance at pins RFA and RFB
series inductance of differential input
note 3−5−nH
impedance at pins RFA and RFB
maximum input power per channel−−22−dBm
minimum input power per channel−−52−dBm
AGC slope at G
v(RF-IOUT)(min)
−3040dB/V
voltage gain mismatch between I and Q−−1dB
group delay variation per channel (40 MHz)
−0.52ns
from RF input to pin IOUT
group delay variation per channel (40 MHz)
−0.52ns
from RF input to pin QOUT
group delay mismatch per channel (40 MHz)
−00.5ns
between I and Q
channel −1 dB bandwidth from RF input to
4050−MHz
pin IOUT
channel −1 dB bandwidth from RF input to
4050−MHz
pin QOUT
channel −3 dB bandwidth from RF input to
7080−MHz
pin IOUT
channel −3 dB bandwidth from RF input to
7080−MHz
pin QOUT
output impedance at pin IOUT−65−Ω
output impedance at pin QOUT−65−Ω
nominal output voltage level at pin IOUTper channel−25−dBmV
nominal output voltage level at pin QOUTper channel−25−dBmV
resistive load at pin IOUT400−−Ω
resistive load at pin QOUT400−−Ω
1999 Aug 306
Page 7
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
SYMBOLPARAMETERCONDITIONSMIN.TYP. MAX.UNIT
SYMMETRICAL RF INPUT (Fig.3)
G
v(RF-IOUT)(min)
G
v(RF-IOUT)(max)
G
v(RF-QOUT)(min)
G
v(RF-QOUT)(max)
IP
3i(I)
IP
2i(I)
IP
3i(Q)
IP
2i(Q)
F
i
ASYMMETRICAL RF INPUT (Fig.4)
G
v(RF-IOUT)(min)
G
v(RF-IOUT)(max)
G
v(RF-QOUT)(min)
G
v(RF-QOUT)(max)
IP
3i(I)
IP
2i(I)
IP
3i(Q)
IP
2i(Q)
F
i
Baseband stages
Z
i
V
i
NTX
i
G
v(IBBIN-IBBOUT)
G
v(QBBIN-QBBOUT)
G
v(I-Q)
IP
3i
IP
2i
∆t
d(g)(40)
t
d(g)(I-Q)(40)
minimum voltage gain from RF input to
pin IOUT
maximum voltage gain from RF input to
pin IOUT
minimum voltage gain from RF input to
pin QOUT
maximum voltage gain from RF input to
pin QOUT
V
AGC
note 4
V
AGC
note 4
V
AGC
note 4
V
AGC
note 4
= 0.1 x VCC;
= 0.9 x VCC;
= 0.1 x VCC;
= 0.9 x VCC;
−−−1dB
2829−dB
−−−1dB
2829−dB
I 3rd-order interception point at RF input14−dBm
I 2nd-order interception point at RF input1215−dBm
Q 3rd-order interception point at RF input14−dBm
Q 2nd-order interception point at RF input1215−dBm
noise figure at maximum gainV
minimum voltage gain from RF input to
pin IOUT
maximum voltage gain from RF input to
pin IOUT
minimum voltage gain from RF input to
pin QOUT
maximum voltage gain from RF input to
pin QOUT
AGC
Z
source
V
AGC
note 5
V
AGC
note 5
V
AGC
note 5
V
AGC
note 5
= 0.9 x VCC;
=50Ω
= 0.1 x VCC;
= 0.9 x VCC;
= 0.1 x VCC;
= 0.9 x VCC;
−1215dB
−−−1dB
−29−dB
−−−1dB
−29−dB
I 3rd-order interception point at RF input−3−dBm
I 2nd-order interception point at RF input−15−dBm
Q 3rd-order interception point at RF input−3−dBm
Q 2nd-order interception point at RF input−15−dBm
noise figure at maximum gainV
AGC
Z
source
= 0.9 x VCC;
=50Ω
−13−dB
input impedance−10−kΩ
nominal input voltage levelper channel−25−dBmV
number of channels at input−2−−
voltage gain from pin IBBIN to pin IBBOUT192022dB
voltage gain from pin QBBIN to pin QBBOUT192022dB
voltage gain mismatch between I and Q−01dB
3rd-order interception point at IQBBIN input5459−dBmV
2nd-order interception point at IQBBIN input7279−dBmV
group delay variation in 40 MHz bandwidth−0.52ns
group delay mismatch in 40 MHz band
−0.52ns
between I and Q
1999 Aug 307
Page 8
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
SYMBOLPARAMETERCONDITIONSMIN.TYP. MAX.UNIT
B
(−1dB)
B
(−3dB)
Z
o
V
o(p-p)
R
o(L)
Overall with a 100 nF capacitor instead of LP1 and LP2
t
d(g)(I-Q)(40)
t
d(g)(I-Q)(R40)
G
v(I-Q)(40)
G
R(I-Q)(40)
SYMMETRICAL RF INPUT
G
v(RF-IBBOUT)(min)
G
v(RF-IBBOUT)(max)
G
v(RF-QBBOUT)(min)
G
v(RF-QBBOUT)(max)
F
i
ASYMMETRICAL RF INPUT
G
v(RF-IBBOUT)(min)
G
v(RF-IBBOUT)(max)
G
v(RF-QBBOUT)(min)
G
v(RF-QBBOUT)(max)
F
i
Notes
1. Measured in baseband (at pin IOUT or pin QOUT) on a carrier at 2 MHz and 25 dBmV.
2. Quadrature error with respect to 90°.
3. The differential input impedance of the IC is 34 Ω in series with the IC pins which give an inductance of 5 nH.
For optimum performance, this inductance should be cancelled by a matching network. Coupling capacitors of 1 pF
give an acceptable result.
4. Gain = V
5. Gain = V
o(dB)
o(dB)
channel −1 dB bandwidth4065−MHz
channel −3 dB bandwidth70100−MHz
output impedance−50−Ω
nominal output voltage level−750−mV
resistive load at output400−−Ω
group delay mismatch in 40 MHz band
−0.52ns
between I and Q
group delay ripple in 40 MHz band for I or Q−0.51ns
voltage gain mismatch in 40 MHz band
−−1dB
between I and Q
voltage gain ripple in 40 MHz band for I or Q−−1dB
minimum voltage gain from RF input to
V
= 0.1 x VCC;−−19dB
AGC
pin IBBOUT
maximum voltage gain from RF input to
V
= 0.9 x VCC;48 49 −dB
AGC
pin IBBOUT
minimum voltage gain from RF input to
V
= 0.1 x VCC;−−19dB
AGC
pin QBBOUT
maximum voltage gain from RF input to
V
= 0.9 x VCC;48 49 −dB
AGC
pin QBBOUT
noise figure at maximum gainV
minimum voltage gain from RF input to
AGC
Z
source
V
AGC
= 0.9 x VCC;
=50Ω
= 0.1 x V
CC
−1316dB
−−19dB
pin IBBOUT
maximum voltage gain from RF input to
V
AGC
= 0.9 x V
−49−dB
CC
pin IBBOUT
minimum voltage gain from RF input to
V
AGC
= 0.1 x V
−−19dB
CC
pin QBBOUT
maximum voltage gain from RF input to
V
AGC
= 0.9 x V
−49−dB
CC
pin QBBOUT
noise figure at maximum gainV
− V
(see Fig.3). Gain for symmetrical RF input
i(dB)
− V
(see Fig.3). Gain for asymmetrical RF input
i(dB)
AGC
Z
source
= 0.9 x VCC;
=50Ω
−14−dB
1999 Aug 308
Page 9
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
handbook, full pagewidth
50 Ω
RF
SOURCE
50 Ω
RF
SOURCE
1 pF
1 pF
Vi (dB)
RFA
RFB
TDA8060TS
MGM319
IOUT
IOUT
QOUT
QOUT
100 Ω
50 Ω
50 Ω
Fig.3 Gain control diagram for symmetrical RF input.
high
impedance
probe
Vo (dB)
handbook, full pagewidth
50 Ω
1.5 pF
1.5 pF
RFB
RFA
Vi (dB)
50 Ω
RF
SOURCE
50 Ω
RF
SOURCE
Fig.4 Gain control diagram for asymmetrical RF input
1999 Aug 309
TDA8060TS
FCE406
IOUT
IOUT
QOUT
QOUT
high
impedance
probe
Vo (dB)
Page 10
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
APPLICATION INFORMATION
Closeattention should be paid tothedesign of the external
tank circuit of the VCO so that it covers the
920 to 2200 MHz frequency range. Both series 6 Ω
resistors kill all parasitic oscillations that could alter this
frequency range. The BB835 Siemens varicap diodes are
mentioned because they provide the highest C
ratio as well as the least parasitic elements in our
frequencyrange. The U-shaped inductance canbeprinted
with a total length of approximately 20 mm.
Filters LP1 and LP2 are not detailed in this data sheet
because their design only depends on the global system.
As the TDA8060 has beendesigned to be compatible with
DVB, DSS andAsian DVB, the cut-off frequenciesand the
tolerance in groupdelay, the orders of thefilters cannot be
globally established.
max/Cmin
Nevertheless, TDA8060 internally filters the baseband at
100 MHz and the nominal levels at inputs and outputs
mentioned in the specification table should be respected.
The input impedance of LP1 and LP2 must exceed 400 Ω
to avoid signal distortion.
The converter outputs (pin IOUT and pin QOUT) must be
AC-coupled via the low-pass filter to the baseband
amplifiers inputs (pin IBBIN and pin QBBIN). Because of
the high impedance at pin IQBBIN, a 100 nF capacitor
gives a high-pass frequency of 160 Hz.
1999 Aug 3010
Page 11
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CC(LO2)
pagewidth
LOGND2
22
LOW-PASS
(3)
FILTER
IOUT2IBBIN
100 nF
24
1999 Aug 3011
V
CC(RF)
6
RFGND
9
V
CC(LO1)
16
LOGND1
15
V
19
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
(2)
gain
0 to 5 V
RF
RF
(1)
1 pF
1 pF
COMGAIN
100 nF
RFA 8
RFB
PEN
CONVERSION STAGE
LNA
7
4
QUADRATURE
GENERATOR
5
20
LOOUT21LOOUTC18TKA17TKB
to PLL
synthesizer IC
STABILIZED LO
PLL AND
AMPLIFIER
OSCILLATORDIVIDE-BY-2
6 Ω6 Ω
1 pF
BB835
20
(2×)
kΩ
×
×
100 MHz
100 MHz
20
kΩ
I CONVERTER
ASYM
SYM
Q CONVERTER
ASYMSYM
TDA8060TS
BASEBAND
11
QOUT
LOW-PASS
(3)
FILTER
AMP
STAGE
AMP
13
QBBIN
100 nF
14
1
12
IBBOUT23
QBBOUT
V
CC(BB1)
V
CC(BB2)
BBGND13
BBGND210
MGM320
LOW-PASS
(3)
FILTER
LOW-PASS
(3)
FILTER
to
I channel
ADC
to
Q channel
ADC
V
from PLL synthesizer IC
tune
(1) Gain control voltage; minimum gain at 0.1 x VCC, maximum gain at 0.9 x VCC; 30 dB range.
(2) Differential RF input 950 to 2200 MHz; level = −22 to −52 dBm per channel.
(3) The filter input impedance is 400 Ω minimum.
Fig.5 Application diagram.
Page 12
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
PACKAGE OUTLINE
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
c
y
Z
2413
A
2
A
pin 1 index
112
w M
b
e
p
1
E
H
E
detail X
A
X
v M
A
Q
(A )
L
p
L
A
3
θ
02.55 mm
scale
DIMENSIONS (mm are the original dimensions)
UNITA1A2A
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
A
max.
0.21
mm
2.0
OUTLINE
VERSION
SOT340-1 MO-150AG
0.05
1.80
1.65
IEC JEDEC EIAJ
0.25
b
3
p
0.38
0.20
0.25
0.09
(1)E(1)(1)
cD
8.4
5.4
8.0
REFERENCES
0.651.25
5.2
1999 Aug 3012
eHELLpQZywvθ
7.9
7.6
1.03
0.63
0.9
0.7
EUROPEAN
PROJECTION
0.130.10.2
0.8
0.4
ISSUE DATE
93-09-08
95-02-04
o
8
o
0
Page 13
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
SOLDERING
Introduction to soldering surface mount packages
Thistextgives a very brief insighttoacomplex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board byscreenprinting, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• Forpackageswith leads on four sides, the footprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Aug 3013
Page 14
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
Suitability of surface mount IC packages for wave and reflow soldering methods
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
2. Thesepackages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wavesoldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wavesoldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Aug 3014
Page 15
Philips SemiconductorsProduct specification
Satellite ZERO-IF QPSK down-converterTDA8060TS
NOTES
1999 Aug 3015
Page 16
Philips Semiconductors – a w orldwide compan y
Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
1999
Internet: http://www.semiconductors.philips.com
67
Printed in The Netherlands545004/25/03/pp16 Date of release: 1999 Aug 30Document order number: 9397 750 04984
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