Datasheet TDA8050T-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1999 Jun 21
File under Integrated Circuits, IC02

1999 Dec 14

INTEGRATED CIRCUITS

TDA8050

QPSK transmitter

1999 Dec 14 2

Philips Semiconductors Product specification

QPSK transmitter TDA8050

FEATURES

• Programmable gain

• PLL controlled carrier frequency

• 3-wire transmission bus

• 5 V supply voltage.

APPLICATIONS

• QPSK modulation.

GENERAL DESCRIPTION

The QuadraturePhaseShift Keying(QPSK) transmitter is
a monolithic bipolar IC dedicated for quadrature
modulation of the I and Q signals. It includes:

• Two double-balanced mixers

• Symmetrical Voltage Controlled Oscillator (VCO) with

0 to 90 degree signal generation for modulation

• Phase-Locked Loop (PLL) for IF frequency control

• Conversion mixer

• PLL for RF frequency control

• Gain controlled output amplifier

• 3-wire bus and an output buffer.

Two PLLs are incorporated, the first PLL includes:

• Fixed main divider

• Crystal oscillator and its programmable reference

divider

• Phase/frequency detector combined with afixed charge
pump.

The second PLL includes:

• Divide-by-four preamplifier

• 12-bit programmable divider

• Crystal oscillator and its programmable reference

divider

• Phase/frequency detector combined with a ‘clever’
chargepump which drivesthe tuning amplifier,including
9 V output.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

CC

supply voltage 4.75 5.00 5.25 V

f

c

output centre frequency 5 − 40 MHz

V

o(max)

maximum output level − 55 − dBmV

f

xtal

crystal frequency 1 − 4 MHz

f

ref(MOD)

reference frequency for modulator synthesizer − 250 − kHz

f

step

frequency step size for convertor synthesizer 50 − 500 kHz

T

amb

operating ambient temperature 0 − 70 °C

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8050T SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1

1999 Dec 14 3

Philips Semiconductors Product specification

QPSK transmitter TDA8050

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BLOCK DIAGRAM

handbook, full pagewidth

FCE181

1/2

90° 0°

×

×

Σ

27

×

TDA8050

MODULATOR CONVERTER

2524 28

1
3

2

30 31

RF_OUT

OUTEN

BUF_OUT

BUF_OUTC

26

AVCC1

4

AGND2

18

DVCC13DGND

9

AGND1

32

SW_CAP

29

AVCC2

8

7

6

5

CLK

I_IN

I_INC

Q_IN

Q_INC

15

14

DATA

16

EN

RF_OUTC

RF_INIF_FILT

RF_INCIF_FILTC

FIXED

MAIN DIVIDER

DAC

3-WIRE BUS TRANCEIVER

DIGITAL

PHASE

COMPARATOR

DIGITAL

PHASE

COMPARATOR

CHARGE

PUMP

PROGRAM-

MABLE

CHARGE

PUMP

PROGRAMMABLE

REF DIVIDER

PROGRAMMABLE

MAIN DIVIDER

PROGRAMMABLE

REF DIVIDER

101211 17 22 21

20 19

CP_MOD

TKAMOD

TKBMOD TKACONV

OSC_IN TKBCONV

TUNECONV CP_CONV

23

LOCK

Fig.1 Block diagram.

1999 Dec 14 4

Philips Semiconductors Product specification

QPSK transmitter TDA8050

PINNING

SYMBOL PIN DESCRIPTION

OUTEN 1 output enable
BUF_OUT 2 output amplifier balanced output
BUF_OUTC 3 output amplifier balanced output
AGND2 4 converter analog ground 2
I_IN 5 I balanced input
I_INC 6 I balanced input
Q_IN 7 Q balanced input
Q_INC 8 Q balanced input
AGND1 9 modulator analog ground 1
TKAMOD 10 modulator VCO tank circuit input 2
TKBMOD 11 modulator VCO tank circuit input 1
CP_MOD 12 modulator charge pump output for

PLL loop filter
DVCC 13 digital supply voltage
CLK 14 3-wire bus serial control clock
DATA 15 3-wire bus serial control data input
EN 16 3-wire bus serial control enable
OSC_IN 17 crystal oscillator input
DGND 18 digital ground
CP_CONV 19 converter charge pump output for

PLL loop filter
TUNECONV 20 tuning voltage output for converter

VCO
TKBCONV 21 converter VCO tank circuit input 1
TKACONV 22 converter VCO tank circuit input 2
LOCK 23 lock detect signal
IF_FILT 24 IF balanced output to filter
IF_FILTC 25 IF balanced output to filter
AVCC1 26 modulator analog supply voltage
RF_OUTC 27 RF balanced output to filter
RF_OUT 28 RF balanced output to filter
AVCC2 29 converter analog supply voltage
RF_IN 30 RF balancedinputto programmable

amplifier
RF_INC 31 RF balanced input toprogrammable

amplifier
SW_CAP 32 switch capacitor

Fig.2 Pin configuration.

handbook, halfpage

TDA8050

FCE182

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OUTEN

BUF_OUT

BUF_OUTC

AGND2

I_IN

I_INC

Q_IN

Q_INC

AGND1
TKAMOD
TKBMOD
CP_MOD

DVCC

CLK

SW_CAP
RF_INC
RF_IN
AVCC2

RF_OUTC
AVCC1

RF_OUT

IF_FILTC
IF_FILT
LOCK
TKACONV
TKBCONV
TUNECONV
CP_CONV

DATA

DGND
OSC_IN

EN

1999 Dec 14 5

Philips Semiconductors Product specification

QPSK transmitter TDA8050

FUNCTIONAL DESCRIPTION

The I and Q are balanced analog signals at a level of
400 mV (p-p). These are mixed by two double balanced
mixers with the output signal generated by a first local
oscillator providing the modulated signal.

The modulated signal is then filtered by an IF filter. This
filteredsignal together with asignalgenerated by asecond
local oscillator is converted by a balanced mixer to
produce the QPSK signal.

TheQPSK signal isamplified by again controlled amplifier
to a level suitable for transmission. The gain of the
controlled amplifier is buscontrolled and this amplifier can
be disabled when not transmitting to provide signal
attenuation.

The amplified signal is applied to an on-chip amplifier
having two balanced outputs (open collector) linked totwo
chip resistors (values 150 Ω), and 9 V. The balanced
outputs are designed to drive a 2 : 1 transformer
(Siemens V944) with a 75 Ω load giving an output level
of 55 dBmV.The output frequencyrange of the transmitter
is 5 to 40 MHz.

The frequency of the first local oscillator operates at twice
the frequency (i.e. 280 MHz) fixed by a Phase-Locked
Loop (PLL) implemented in the circuit.

Thefrequencyof the second localoscillatoroperatesin the
bandwidth 145 to 180 MHz and programmable due to a
PLL implemented in the circuit.

The VCO of both first and secondlocal oscillatorsrequires
an external LC tank circuit with two varicap diodes.

The data to the PLL is loaded in bursts framed by the
signal EN. Programming rising clock edges and their
appropriate data bits are ignored until EN goes active
(LOW). The internal latches are updated with the latest
programming data when EN returns inactive (HIGH).
The last 14 bits are stored in the programming register.

No check is made on the number of clock pulses received
during the time programming is enabled. A wrong active

clock edge will be generated causing a shift of data
bits, if EN goes HIGH while CLK is still LOW. At power

up, EN should beHIGH. The lock detector output LOCK is
HIGH when both PLLs are in lock.

The main divider ratio and the reference divider ratios are
provided via the serial bus. A control register controls the
Digital-to-Analog Converter (DAC), the output amplifier
and the charge pump currents (Tables 1, 2 and 3).

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

supply voltage −0.3 +6.0 V

t

sc

short-circuit time (every pin to VCCor GND) − 10 s

V

max

voltage on all pins except BUF_OUT, BUF_OUTC and TUNECONV −0.3 V

CC

V

V

o(tune)

output tuning voltage −0.3 +30 V

V

o(buf)

output buffer voltage on pins BUF_OUTand BUF_OUTC − 10 V

P

tot

maximum power dissipation − 800 mW

T

amb

operating ambient temperature 0 70 °C

T

stg

storage temperature −40 +150 °C

T

j(max)

junction temperature − 150 °C

1999 Dec 14 6

Philips Semiconductors Product specification

QPSK transmitter TDA8050

THERMAL CHARACTERISTICS

HANDLING

Human Body Model (HBM): The IC pins withstand 2 kV except pins 27 and 28 (1750 V).
Machine Model (MM): The IC pins withstand 100 V.

CHARACTERISTICS

Measured in application circuit (see Fig.9) with the following conditions: V

CC

=5V; T

amb

=25°C; all AC units are RMS

values; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 63 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA(mod)

modulator analog supply voltage 4.75 5 5.25 V

I

CCA(mod)

modulator analog supply current − 41 − mA

V

CCA(conv)

converter analog supply voltage 4.75 5 5.25 V

I

CCA(conv)

converter analog supply current − 48 − mA

I

CC(buf)

buffer output supply current − 44 − mA

V

CCD

digital supply voltage 4.75 5 5.25 V

I

CCD

digital supply current − 22 − mA

V

CC(tune)

tuning supply voltage −−9V

Quadrature modulator I and Q inputs

V

I(DC)

input DC level over the complete range of

temperature

− 0.5VCC− V

V

i(p-p)

signal input level (balanced)
(peak-to-peak value)

indicative − 400 500 mV

f

i(max)

I and Q maximum input frequency indicative − 10 − MHz

Z

i(dif)

differential input impedance − 4.4 − kΩ

B

(1dB)

1 dB amplifier bandwidth indicative − 10 − MHz
MODULATOR
f

c

output centre frequency −−140 MHz

∆A amplitude imbalance see Fig.3 −−±1dB
∆Φ phase imbalance −−±2 deg

LO

(sup)

LO suppression see Fig.3 −−28 − dBc
Z

o(dif)

differential output impedance − 1.8 − kΩ
MODULATOR VOLTAGE CONTROLLED OSCILLATOR
f

osc(mod)

oscillation frequency VCO −−280 MHz

1999 Dec 14 7

Philips Semiconductors Product specification

QPSK transmitter TDA8050

Converter output

V

o

output level fi= 30 MHz; V

i(dif)

= 100 mV

at I and Q inputs

37.5 40 42.5 dBmV

∆V

o

output flatness fi= 5 to 40 MHz;

V

i(dif)

= 100 mV at I and Q

inputs

−−2dB

f

c

output centre frequency 5 − 40 MHz
Z

o(dif)

differential output impedance − 150 −Ω
IM3 3rd-order intermodulation distortion see Fig.4 −−−35 dBc
H

2

2nd-order harmonic of 5 to 40 MHz

signal

fi= 10 to 80 MHz;
V

i(dif)

= 100 mV at I and Q

inputs

−−−45 dBc

H

3

3rd-order harmonic of 5 to 40 MHz

signal

fi= 15 to 120 MHz;
V

i(dif)

= 100 mV at I and Q

inputs

−−−45 dBc

S

o

mixer spurious outputs of

5 to 40 MHz signal

fi= 5 to 40 MHz;
V

i(dif)

= 100 mV at I and Q

inputs

−−−50 dBc

Converter voltage controlled oscillator

f

osc(min)

minimum oscillation frequency −−145 MHz
f

osc(max)

maximum oscillation frequency 180 −−MHz
Programmable gain and output buffer; note 1
Z

i(dif)

differential input impedance − 5.6 − kΩ

∆G output level step size −−2dB
∆Buf

o

output level adjust range Vi= 30 dBmV sine wave;

40 MHz at pin
RF_IN and RF_INC;
DAC = 0 to 31

32 −−dB

V

o

output level − 55 − dBmV
∆V

o

output flatness fi= 5 to 40 MHz;

Vi= 30 dBmV sine wave;
DAC = 28

−−2dB

V

O(ENL)

output controlled enable LOW output buffer on −−0.8 V
V

O(ENH)

output controlled enable HIGH output buffer off 2.4 −−V
ISO disable isolation V

i(dif)

= 100 mV;
Vo= 55 dBmV; DAC = 28;
fi= 40 MHz; OE = 0.5

−35 −−dBc

G

(max)

maximum gain see Fig.5 − 22 − dB

V

o(1dB)

1 dB compression point see Fig.5 60 −−dBmV

H

2

2nd-order harmonic of 5 to 40 MHz
signal

see Fig.6

f

i

=10to40MHz −−−45 dBc

f

i

= 54 to 120 MHz −−−35 dBc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Dec 14 8

Philips Semiconductors Product specification

QPSK transmitter TDA8050

H

3

3rd-order harmonic of 5 to 40 MHz
signal

Fig.6

f

i

=15to40MHz −−−45 dBc

f

i

= 54 to 120 MHz −−−35 dBc

Overall; note 1

Φ

osc

phase noise note 2;

at 10 kHz −−70 − dBc/Hz
at 100 kHz −−90 − dBc/Hz

S

o

spurious signals of 5 to 40 MHz
signal

fi= 5 to 40 MHz;
V

i(dif)

= 100 mV at I and Q
inputs; Vo= 30 to 55 dBmV

−−−50 dBc

ISO

tot

total isolation at I/Q mid-range see Fig.7 −−−65 dBc

C/N carrier to noise ratio at final output

at 2 MHz from carrier

V

i(dif)

= 100 mV
Vo= 35 to 55 dBmV;
fi= 26.5 MHz

− 113 − dBc/Hz

Crystal oscillator

f

xtal

crystal frequency note 3 1 − 4 MHz

Z

i

input impedance f

xtal

= 4 MHz 600 1200 −Ω

V

I(DC)

DC input level − 2.9 − V

Modulator synthesizer

f

ref(mod)

reference frequency − 250 − kHz

RDR1 reference divider ratio

programmable

4 − 16

ND1 fixed main divider ratio − 1120 −
I

cp

charge-pump current fixed − 0.30 − mA

Converter synthesizer

f

step

frequency step size 50 − 500 kHz
RD2 fixed reference divider ratio − 2 −
RDR2 reference divider ratio

programmable

see Table 4 4 − 160

ND2 fixed main divider ratio − 4 −
NDR2 programmable main divider ratio see Table 4 290 − 3600

Three wire bus

V

IL

LOW-level input voltage −−0.8 V
V

IH

HIGH-level input voltage 2.4 −−V

Lock detect pin

V

o(lock)

output voltage (lock) − 5 − V
V

o(unlock)

output voltage (unlock) − 0.02 − V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Dec 14 9

Philips Semiconductors Product specification

QPSK transmitter TDA8050

Notes

1. All specification points of the output section and the overall circuit are measured after the 2 : 1 transformer
(siemens V944) connected with a load of 75 Ω.

2. Overall phase noise converter: Icp= 0.36 mA; f

ref

= 12.5 kHz; V

I(diff)

= 100 mV; V

O(diff)

= 100 mV; VO= 55 dBmV;

DAC = 28; fi= 26.5 MHz.

3. Crystal oscillator; the crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is serial
resonant with load a capacitance of 18 to 20 pF. The connection to VCCis preferred but can also be to GND.

Notes to the characteristics

Serial control clock

f

clk

clock frequency − 330 − kHz

t

su

input data to CLK set-up time see Fig.3 − 2 −µs

t

h(CLK)

input data to CLK hold time see Fig.3 − 1 −µs

t

d(strt)

delay to rising clock edge see Fig.3 − 3 −µs

t

d(stp)

delay from last clock edge see Fig.3 − 3 −µs

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Fig.3 Imbalance and LO suppression.

The amplitude imbalance and the LO suppression are measured in the spectrum of the signal measured at the output IF_FILT and are defined in the
following conditions:

Measure 1: I input frequency = 500 kHz. I input level = 400 mV (p-p) sine wave. Unused input as 0 V differential.
Measure 2: Q input frequency = 500 kHz. Q input level = 400 mV (p-p) sine wave. Unused input as 0 V differential.

handbook, full pagewidth

FCE183

LO

(sup)

measure 2 f

i(Q)

imbalance

measure 1 f

i(I)

frequency

IF_FILT

1999 Dec 14 10

Philips Semiconductors Product specification

QPSK transmitter TDA8050

3rd-order intermodulation distortion;

Two tones of 260 mV (p-p) at each I and Q input:

2 sine waves with a total RMS values of 128 mV give:

90 mV (RMS) = 260 mV (p-p) and f1= 300 kHz,

f

2

= 500 kHz and fRF= 40 MHz.

V

av()

400

2

--------- -

10

4–

20

------

× 128 mV RMS()==

2x

2

× 128=

x

128

2

--------- -

==

Fig.4 3rd-order intermodulation distortion in I and Q channels (IM3).

handbook, full pagewidth

500 kHz 300 kHz

I_IN

RF_OUT

Q_IN

I_INC

RF_OUTC

Q_INC

50 Ω
50 Ω

FCE184

f (MHz)

39.1 39.5 39.7 39.9 40 40.1 40.3 40.5 40.7

1999 Dec 14 11

Philips Semiconductors Product specification

QPSK transmitter TDA8050

handbook, full pagewidth

50 Ω

gain
(dB)

V

o(−1 dB)

V

o

G

max − 1

G

max

FCE185

RF_IN

BUF_OUT

RF_INC

BUF_OUTC

150 Ω

150 Ω

Siemens V944

9 V

75 Ω

V

o2

Fig.5 Maximum gain and compression point.

DAC = 31.
f = 26.5 MHz.
Vi is variable to have a variable output voltage.

Fig.6 Harmonics of output section H2 and H3.

DAC = 28.
f

i

= 5 to 40 MHz.

V

i

= 200 mV sine wave.

V

o

= 55 dBmV (RMS value).

handbook, full pagewidth

FCE186

RF_IN

BUF_OUT

RF_INC

BUF_OUTC

150 Ω

150 Ω

Siemens V944

9 V

75 Ω

1999 Dec 14 12

Philips Semiconductors Product specification

QPSK transmitter TDA8050

Fig.7 Isolation total.

ISO

tot=Vo1

(dB) − Vo2(dB).

handbook, full pagewidth

FCE187

I_IN

BUF_OUT

V

i(dif)

= 100 mV

OUTEN = 0 V

I_INC

Q_IN
Q_INC

BUF_OUTC

DAC = 28

150 Ω

150 Ω

Siemens V944

9 V

75 Ω

V

i(dif)

= 100 mV

V

o1

I_IN

BUF_OUT

0 V

OUTEN = 5 V

I_INC

Q_IN
Q_INC

BUF_OUTC

DAC = 28

150 Ω

150 Ω

Siemens V944

9 V

75 Ω

0 V

V

o2

1999 Dec 14 13

Philips Semiconductors Product specification

QPSK transmitter TDA8050

APPLICATION INFORMATION

Table 1 Data format; note 1

Notes

1. X = don’t care.

2. MP1 and MP0: modulator reference divider ratio (see Table 2).

3. When OEN (output enable) is at logic 0, output is disabled, at logic 1 output is enabled.

4. CR2 to CR0: converter synthesizer charge pump current (see Table 3).

5. When DAC4 to DAC0 is at logic 0 minimum gain is programmed, at logic 1 maximum gain is programmed.

DATA ADDRESS

D11

first in

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 AD1 AD0

last in

Modulator reference divider
ratio

Converter reference divider ratio

X X MP1

(2)

MP0

(2)

R7 R6 R5 R4 R3 R2 R1 R0 0 1

Control register

X X X OEN

(3)

CR2

(4)

CR1 CR0

(4)

DAC4

(5)

DAC3 DAC2 DAC1 DAC0 1 0

Main divider ratio

P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 1

handbook, full pagewidth

MBL113

CLK

DATA

EN

t

d(strt)

t

d(stp)

t

h(CLK)

t

su

T

cy

Fig.8 3-wire bus timing.

1999 Dec 14 14

Philips Semiconductors Product specification

QPSK transmitter TDA8050

Table 2 Modulator reference divider ratio

Table 3 Converter synthesizer charge pump current

Note

1. LOCK_CONV is an internal signal.
When at logic 0 converter PLL is out-of-lock. When at logic 1 converter PLL is in-lock.

Table 4 Converter synthesizer: f

comp=fosc

/RD

Table 5 Converter synthesizer; ND = 4; f

lo

=ND×NDR × f

comp

= NDR × step

MP1 MP0 PROGRAMMED RATIO

11 4
10 8
01 16

CR2 CR1 CR0 LOCK_CONV

(1)

Icp (mA)

00001.2

00010.36

00100.36

00110.1
010−0.1
011−0.36
100−1.2

f

osc\fcomp

12.5 kHz 25 kHz 50 kHz 125 kHz

1 MHz 80 40 20 8
4 MHz 320 160 80 32

f

lo

\step 50 kHz 100 kHz 200 kHz 500 kHz

145 MHz 2900 1450 725 290
180 MHz 3600 1800 900 360

1999 Dec 14 15

Philips Semiconductors Product specification

QPSK transmitter TDA8050

handbook, full pagewidth

22 kΩ

680 Ω

+9 V

+5 V

27 kΩ

10 nF

100
nF

18 pF

100 nF

100 nF

100 nF

100 nF

100 pF

330 pF

8.2
pF

820 pF

BB132

(2×)

56 nH

68 nH

140 MHz

10 kΩ

10 kΩ

10 kΩ

22 kΩ

39 pF

27 pF

47 pF

39 pF

TDA8050

MBK982

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OUTEN

BUF_OUT

BUF_OUTC

AGND2

I_IN

I_INC

Q_IN

Q_INC

AGND1

TKAMOD

TKBMOD

CP_MOD

DVCC

CLK

SW_CAP

RF_INC

RF_IN

AVCC2

RF_OUTC

AVCC1

RF_OUT

IF_FILTC

IF_FILT

LOCK

TKACONV

TKBCONV

TUNECONV

CP_CONV

DATA DGND

OSC_IN

4 MHz

EN

18 pF

8.2 nF

330pF370

pF

10
pF

BB133

(2×)

22 nH

18 kΩ

100 Ω

10 kΩ

10 kΩ

22 kΩ

22 kΩ

15 pF

100 nF

100 nF

100 Ω

150 Ω

150 Ω

Siemens

V944

100 nF

100 nF

15 pF

+5 V

390 nH 390 nH

+5 V

+9 V

Fig.9 Application diagram.

1999 Dec 14 16

Philips Semiconductors Product specification

QPSK transmitter TDA8050

INTERNAL PIN CONFIGURATION

SYMBOL PIN DESCRIPTION DC VOLTAGE

OUTEN 1 −
SW_CAP 32 1.7 V

BUF_OUT 2 5.8 V
BUF_OUTC 3 5.8 V

AGND2 4 0

I_IN 5 2.5 V
I_INC 6 2.5 V

1

32

FCE004

2 3

FCE005

FCE023

4

5

6

FCE006

1999 Dec 14 17

Philips Semiconductors Product specification

QPSK transmitter TDA8050

Q_IN 7 2.5 V
Q_INC 8 2.5 V

AGND1 9 0 V

TKAMOD 10 3.1 V
TKBMOD 11 3.1 V

CP_MOD 12 2.1 V

DVCC 13 supply voltage 5 V

SYMBOL PIN DESCRIPTION DC VOLTAGE

7

8

FCE007

FCE008

9

10 11

FCE009

12

FCE010

1999 Dec 14 18

Philips Semiconductors Product specification

QPSK transmitter TDA8050

CLK 14 −

DATA 15 −

EN 16 −

OSC_IN 17 2.9 V

DGND 18 0

SYMBOL PIN DESCRIPTION DC VOLTAGE

14

FCE011

15

FCE012

16

FCE013

V

CC

17

FCE014

FCE015

18

1999 Dec 14 19

Philips Semiconductors Product specification

QPSK transmitter TDA8050

CP_CONV 19 2.1 V

TUNECONV 20 V

VT

TKBCONV 21 3.1 V
TKACONV 22 3.1 V

LOCK 23 0 V

5V

SYMBOL PIN DESCRIPTION DC VOLTAGE

V

CC

down

up

19

FCE016

20

FCE017

21

22

FCE018

23

FCE019

1999 Dec 14 20

Philips Semiconductors Product specification

QPSK transmitter TDA8050

IF_FILT 24 2.1 V
IF_FILTC 25 2.1 V

AVCC1 26 supply voltage 5 V
RF_OUTC 27 3.7 V
RF_OUT 28 3.7 V

AVCC2 29 supply voltage 5 V
RF_IN 30 2.1 V
RF_INC 31 2.1 V

SYMBOL PIN DESCRIPTION DC VOLTAGE

24

25

FCE020

FCE021

27

28

30

31

FCE022

1999 Dec 14 21

Philips Semiconductors Product specification

QPSK transmitter TDA8050

PACKAGE OUTLINE

UNIT

A

max.

A1A2A3b

p

cD

(1)E(1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

2.65

0.10

0.25

0.01

1.4

0.055

0.3

0.1

2.45

2.25

0.49

0.36

0.27

0.18

20.7

20.3

7.6

7.4

1.27

10.65

10.00

1.2

1.0

0.95

0.55

8
0

o
o

0.25 0.1

0.004

0.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT287-1

(1)

0.012

0.004

0.096

0.086

0.02

0.01

0.050

0.047

0.039

0.419

0.394

0.30

0.29

0.81

0.80

0.011

0.007

0.037

0.022

0.010.01

0.043

0.016

w M

b

p

D

H

E

Z

e

c

v M

A

X

A

y

32

17

16

1

θ

A

A

1

A

2

L

p

Q

detail X

L

(A )

3

E

pin 1 index

0 5 10 mm

scale

SO32: plastic small outline package; 32 leads; body width 7.5 mm

SOT287-1

95-01-25
97-05-22

1999 Dec 14 22

Philips Semiconductors Product specification

QPSK transmitter TDA8050

SOLDERING
Introduction to soldering surface mount packages

Thistext gives averybrief insight to acomplextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages.Wave soldering is not alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardby screen printing,stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering andcooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurface mount devices (SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackages with leads onfoursides, the footprintmust
be placedat a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering,the packagemust
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Dec 14 23

Philips Semiconductors Product specification

QPSK transmitter TDA8050

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOPand TSSOP packages with a pitch (e)equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

68

Philips Semiconductors – a w orldwide compan y

For all other countries apply to: Philips Semiconductors,

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

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Middle East: see Italy

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252042 KIEV, Tel. [phone], Fax. [phone]

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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

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Printed in The Netherlands 545004/25/04/pp24 Date of release:1999 Dec 14 Document order number: 9397 750 06555