Datasheet tda8050 n DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8050

QPSK transmitter

Product specification
Supersedes data of 1999 Jun 21
File under Integrated Circuits, IC02

1999 Dec 14

Philips Semiconductors Product specification

QPSK transmitter TDA8050

FEATURES

• Programmable gain

• PLL controlled carrier frequency

• 3-wire transmission bus

• 5 V supply voltage.

APPLICATIONS

• QPSK modulation.

GENERAL DESCRIPTION

The QuadraturePhaseShift Keying(QPSK) transmitter is
a monolithic bipolar IC dedicated for quadrature
modulation of the I and Q signals. It includes:

• Two double-balanced mixers

• Symmetrical Voltage Controlled Oscillator (VCO) with

0 to 90 degree signal generation for modulation

• Phase-Locked Loop (PLL) for IF frequency control

• Conversion mixer

QUICK REFERENCE DATA

• PLL for RF frequency control

• Gain controlled output amplifier

• 3-wire bus and an output buffer.

Two PLLs are incorporated, the first PLL includes:

• Fixed main divider

• Crystal oscillator and its programmable reference

divider

• Phase/frequency detector combined with afixed charge
pump.

The second PLL includes:

• Divide-by-four preamplifier

• 12-bit programmable divider

• Crystal oscillator and its programmable reference

divider

• Phase/frequency detector combined with a ‘clever’
chargepump which drivesthe tuning amplifier,including
9 V output.

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

CC

f

c

V

o(max)

f

xtal

f

ref(MOD)

f

step

T

amb

supply voltage 4.75 5.00 5.25 V
output centre frequency 5 − 40 MHz
maximum output level − 55 − dBmV
crystal frequency 1 − 4 MHz
reference frequency for modulator synthesizer − 250 − kHz
frequency step size for convertor synthesizer 50 − 500 kHz
operating ambient temperature 0 − 70 °C

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8050T SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1

1999 Dec 14 2

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1999 Dec 14 3

BLOCK DIAGRAM

Philips Semiconductors Product specification

QPSK transmitter TDA8050

I_IN

I_INC

Q_IN

Q_INC

CLK

DATA

EN

LOCK

5
6

7
8

14
15
16

23

CHARGE

CP_MOD

DVCC13DGND

PUMP

RF_OUTC

AVCC1

18

AGND1

26

9

RF_OUT

2524 28

RF_INCIF_FILTC

RF_INIF_FILT

27

30 31

SW_CAP

MODULATOR CONVERTER

×

Σ

×

×

3-WIRE BUS TRANCEIVER

DIGITAL

PHASE

COMPARATOR

PROGRAMMABLE

FIXED

MAIN DIVIDER

REF DIVIDER

90° 0°

1/2

TDA8050

101211 17 22 21

TKAMOD

TKBMOD TKACONV

OSC_IN TKBCONV

DAC

PROGRAMMABLE

MAIN DIVIDER

PROGRAMMABLE

REF DIVIDER

AVCC2

32

DIGITAL

PHASE

COMPARATOR

20 19

TUNECONV CP_CONV

AGND2

29

PROGRAM-

MABLE

CHARGE

PUMP

4

1

OUTEN

3

BUF_OUTC

2

BUF_OUT

FCE181

handbook, full pagewidth

Fig.1 Block diagram.

Philips Semiconductors Product specification

QPSK transmitter TDA8050

PINNING

SYMBOL PIN DESCRIPTION

OUTEN 1 output enable
BUF_OUT 2 output amplifier balanced output
BUF_OUTC 3 output amplifier balanced output
AGND2 4 converter analog ground 2
I_IN 5 I balanced input
I_INC 6 I balanced input
Q_IN 7 Q balanced input
Q_INC 8 Q balanced input
AGND1 9 modulator analog ground 1
TKAMOD 10 modulator VCO tank circuit input 2
TKBMOD 11 modulator VCO tank circuit input 1
CP_MOD 12 modulator charge pump output for

PLL loop filter
DVCC 13 digital supply voltage
CLK 14 3-wire bus serial control clock
DATA 15 3-wire bus serial control data input
EN 16 3-wire bus serial control enable
OSC_IN 17 crystal oscillator input
DGND 18 digital ground
CP_CONV 19 converter charge pump output for

PLL loop filter
TUNECONV 20 tuning voltage output for converter

VCO
TKBCONV 21 converter VCO tank circuit input 1
TKACONV 22 converter VCO tank circuit input 2
LOCK 23 lock detect signal
IF_FILT 24 IF balanced output to filter
IF_FILTC 25 IF balanced output to filter
AVCC1 26 modulator analog supply voltage
RF_OUTC 27 RF balanced output to filter
RF_OUT 28 RF balanced output to filter
AVCC2 29 converter analog supply voltage
RF_IN 30 RF balancedinput to programmable

amplifier
RF_INC 31 RF balanced input toprogrammable

amplifier
SW_CAP 32 switch capacitor

handbook, halfpage

BUF_OUTC

OUTEN

BUF_OUT

AGND2

AGND1
TKAMOD
TKBMOD
CP_MOD

I_IN

I_INC

Q_IN

Q_INC

DVCC

CLK

DATA

EN

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

TDA8050

Fig.2 Pin configuration.

FCE182

32

SW_CAP

31

RF_INC
RF_IN

30

AVCC2

29

RF_OUT

28

RF_OUTC

27

AVCC1

26
25

IF_FILTC

24

IF_FILT

23

LOCK

22

TKACONV

21

TKBCONV

20

TUNECONV

19

CP_CONV

18

DGND

17

OSC_IN

1999 Dec 14 4

Philips Semiconductors Product specification

QPSK transmitter TDA8050

FUNCTIONAL DESCRIPTION

The I and Q are balanced analog signals at a level of
400 mV (p-p). These are mixed by two double balanced
mixers with the output signal generated by a first local
oscillator providing the modulated signal.

The modulated signal is then filtered by an IF filter. This
filteredsignal together with asignalgenerated by asecond
local oscillator is converted by a balanced mixer to
produce the QPSK signal.

TheQPSK signal isamplified by again controlled amplifier
to a level suitable for transmission. The gain of the
controlled amplifier is buscontrolled and this amplifier can
be disabled when not transmitting to provide signal
attenuation.

The amplified signal is applied to an on-chip amplifier
having two balanced outputs (open collector) linked totwo
chip resistors (values 150 Ω), and 9 V. The balanced
outputs are designed to drive a 2 : 1 transformer
(Siemens V944) with a 75 Ω load giving an output level
of 55 dBmV.The output frequencyrange of the transmitter
is 5 to 40 MHz.

The frequency of the first local oscillator operates at twice
the frequency (i.e. 280 MHz) fixed by a Phase-Locked
Loop (PLL) implemented in the circuit.

Thefrequencyof the second localoscillatoroperatesin the
bandwidth 145 to 180 MHz and programmable due to a
PLL implemented in the circuit.

The VCO of both first and secondlocal oscillatorsrequires
an external LC tank circuit with two varicap diodes.

The data to the PLL is loaded in bursts framed by the
signal EN. Programming rising clock edges and their
appropriate data bits are ignored until EN goes active
(LOW). The internal latches are updated with the latest
programming data when EN returns inactive (HIGH).
The last 14 bits are stored in the programming register.

No check is made on the number of clock pulses received
during the time programming is enabled. A wrong active

clock edge will be generated causing a shift of data
bits, if EN goes HIGH while CLK is still LOW. At power

up, EN should beHIGH. The lock detector output LOCK is
HIGH when both PLLs are in lock.

The main divider ratio and the reference divider ratios are
provided via the serial bus. A control register controls the
Digital-to-Analog Converter (DAC), the output amplifier
and the charge pump currents (Tables 1, 2 and 3).

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

t

sc

V

max

V

o(tune)

V

o(buf)

P

tot

T

amb

T

stg

T

j(max)

supply voltage −0.3 +6.0 V
short-circuit time (every pin to VCCor GND) − 10 s
voltage on all pins except BUF_OUT, BUF_OUTC and TUNECONV −0.3 V

CC

V
output tuning voltage −0.3 +30 V
output buffer voltage on pins BUF_OUTand BUF_OUTC − 10 V
maximum power dissipation − 800 mW
operating ambient temperature 0 70 °C
storage temperature −40 +150 °C
junction temperature − 150 °C

1999 Dec 14 5

Philips Semiconductors Product specification

QPSK transmitter TDA8050

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

HANDLING

Human Body Model (HBM): The IC pins withstand 2 kV except pins 27 and 28 (1750 V).
Machine Model (MM): The IC pins withstand 100 V.

CHARACTERISTICS

Measured in application circuit (see Fig.9) with the following conditions: V
values; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA(mod)

I

CCA(mod)

V

CCA(conv)

I

CCA(conv)

I

CC(buf)

V

CCD

I

CCD

V

CC(tune)

Quadrature modulator I and Q inputs

V

I(DC)

V

i(p-p)

f

i(max)

Z

i(dif)

B

(1dB)

MODULATOR
f

c

∆A amplitude imbalance see Fig.3 −−±1dB
∆Φ phase imbalance −−±2 deg

LO

(sup)

Z

o(dif)

MODULATOR VOLTAGE CONTROLLED OSCILLATOR
f

osc(mod)

thermal resistance from junction to ambient in free air 63 K/W

=5V; T

CC

=25°C; all AC units are RMS

amb

modulator analog supply voltage 4.75 5 5.25 V
modulator analog supply current − 41 − mA
converter analog supply voltage 4.75 5 5.25 V
converter analog supply current − 48 − mA
buffer output supply current − 44 − mA
digital supply voltage 4.75 5 5.25 V
digital supply current − 22 − mA
tuning supply voltage −−9V

input DC level over the complete range of

− 0.5VCC− V

temperature

signal input level (balanced)

indicative − 400 500 mV

(peak-to-peak value)
I and Q maximum input frequency indicative − 10 − MHz
differential input impedance − 4.4 − kΩ
1 dB amplifier bandwidth indicative − 10 − MHz

output centre frequency −−140 MHz

LO suppression see Fig.3 −−28 − dBc
differential output impedance − 1.8 − kΩ

oscillation frequency VCO −−280 MHz

1999 Dec 14 6

Philips Semiconductors Product specification

QPSK transmitter TDA8050

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Converter output

V

o

output level fi= 30 MHz; V

at I and Q inputs

∆V

o

output flatness fi= 5 to 40 MHz;

V

= 100 mV at I and Q

i(dif)

inputs

f

c

Z

o(dif)

output centre frequency 5 − 40 MHz
differential output impedance − 150 −Ω

IM3 3rd-order intermodulation distortion see Fig.4 −−−35 dBc
H

2

2nd-order harmonic of 5 to 40 MHz
signal

fi= 10 to 80 MHz;
V

= 100 mV at I and Q

i(dif)

inputs

H

3

3rd-order harmonic of 5 to 40 MHz
signal

fi= 15 to 120 MHz;
V

= 100 mV at I and Q

i(dif)

inputs

S

o

mixer spurious outputs of
5 to 40 MHz signal

fi= 5 to 40 MHz;
V

= 100 mV at I and Q

i(dif)

inputs

Converter voltage controlled oscillator

f

osc(min)

f

osc(max)

minimum oscillation frequency −−145 MHz
maximum oscillation frequency 180 −−MHz

Programmable gain and output buffer; note 1
Z

i(dif)

differential input impedance − 5.6 − kΩ

∆G output level step size −−2dB
∆Buf

o

output level adjust range Vi= 30 dBmV sine wave;

40 MHz at pin
RF_IN and RF_INC;

DAC = 0 to 31
V
∆V

o

o

output level − 55 − dBmV
output flatness fi= 5 to 40 MHz;

Vi= 30 dBmV sine wave;

DAC = 28
V

O(ENL)

V

O(ENH)

ISO disable isolation V

output controlled enable LOW output buffer on −−0.8 V
output controlled enable HIGH output buffer off 2.4 −−V

= 100 mV;

i(dif)

Vo= 55 dBmV; DAC = 28;

fi= 40 MHz; OE = 0.5
G

(max)

V

o(1dB)

H

2

maximum gain see Fig.5 − 22 − dB
1 dB compression point see Fig.5 60 −−dBmV
2nd-order harmonic of 5 to 40 MHz

signal

see Fig.6

f

=10to40MHz −−−45 dBc

i

f

= 54 to 120 MHz −−−35 dBc

i

i(dif)

= 100 mV

37.5 40 42.5 dBmV

−−2dB

−−−45 dBc

−−−45 dBc

−−−50 dBc

32 −−dB

−−2dB

−35 −−dBc

1999 Dec 14 7

Philips Semiconductors Product specification

QPSK transmitter TDA8050

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

H

3

Overall; note 1

Φ

osc

S

o

ISO

tot

C/N carrier to noise ratio at final output

Crystal oscillator

f

xtal

Z

i

V

I(DC)

Modulator synthesizer

f

ref(mod)

RDR1 reference divider ratio

ND1 fixed main divider ratio − 1120 −
I

cp

Converter synthesizer

f

step

RD2 fixed reference divider ratio − 2 −
RDR2 reference divider ratio

ND2 fixed main divider ratio − 4 −
NDR2 programmable main divider ratio see Table 4 290 − 3600

Three wire bus

V

IL

V

IH

Lock detect pin

V

o(lock)

V

o(unlock)

3rd-order harmonic of 5 to 40 MHz
signal

Fig.6

f

=15to40MHz −−−45 dBc

i

f

= 54 to 120 MHz −−−35 dBc

i

phase noise note 2;

at 10 kHz −−70 − dBc/Hz
at 100 kHz −−90 − dBc/Hz

spurious signals of 5 to 40 MHz
signal

fi= 5 to 40 MHz;

V

= 100 mV at I and Q

i(dif)

−−−50 dBc

inputs; Vo= 30 to 55 dBmV

total isolation at I/Q mid-range see Fig.7 −−−65 dBc

V

at 2 MHz from carrier

= 100 mV

i(dif)

Vo= 35 to 55 dBmV;

− 113 − dBc/Hz

fi= 26.5 MHz

crystal frequency note 3 1 − 4 MHz
input impedance f

= 4 MHz 600 1200 −Ω

xtal

DC input level − 2.9 − V

reference frequency − 250 − kHz

4 − 16

programmable

charge-pump current fixed − 0.30 − mA

frequency step size 50 − 500 kHz

see Table 4 4 − 160

programmable

LOW-level input voltage −−0.8 V
HIGH-level input voltage 2.4 −−V

output voltage (lock) − 5 − V
output voltage (unlock) − 0.02 − V

1999 Dec 14 8

Philips Semiconductors Product specification

QPSK transmitter TDA8050

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Serial control clock

f

clk

t

su

t

h(CLK)

t

d(strt)

t

d(stp)

Notes

1. All specification points of the output section and the overall circuit are measured after the 2 : 1 transformer
(siemens V944) connected with a load of 75 Ω.

2. Overall phase noise converter: Icp= 0.36 mA; f
DAC = 28; fi= 26.5 MHz.

3. Crystal oscillator; the crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is serial
resonant with load a capacitance of 18 to 20 pF. The connection to VCCis preferred but can also be to GND.

clock frequency − 330 − kHz
input data to CLK set-up time see Fig.3 − 2 −µs
input data to CLK hold time see Fig.3 − 1 −µs
delay to rising clock edge see Fig.3 − 3 −µs
delay from last clock edge see Fig.3 − 3 −µs

= 12.5 kHz; V

ref

= 100 mV; V

I(diff)

= 100 mV; VO= 55 dBmV;

O(diff)

Notes to the characteristics

handbook, full pagewidth

The amplitude imbalance and the LO suppression are measured in the spectrum of the signal measured at the output IF_FILT and are defined in the
following conditions:

Measure 1: I input frequency = 500 kHz. I input level = 400 mV (p-p) sine wave. Unused input as 0 V differential.
Measure 2: Q input frequency = 500 kHz. Q input level = 400 mV (p-p) sine wave. Unused input as 0 V differential.

IF_FILT

measure 2 f

i(Q)

imbalance

LO

(sup)

measure 1 f

i(I)

FCE183

frequency

Fig.3 Imbalance and LO suppression.

1999 Dec 14 9

Philips Semiconductors Product specification

QPSK transmitter TDA8050

handbook, full pagewidth

50 Ω
50 Ω

500 kHz 300 kHz

I_IN
I_INC

Q_IN
Q_INC

RF_OUT

RF_OUTC

39.1 39.5 39.7 39.9 40 40.1 40.3 40.5 40.7

3rd-order intermodulation distortion;

Two tones of 260 mV (p-p) at each I and Q input:

400

V

--------- -

av()

2 sine waves with a total RMS values of 128 mV give:

2

2x

× 128=

128

x

==

--------- ­2

f

= 500 kHz and fRF= 40 MHz.

2

4–

-----­20

10

× 128 mV RMS()==

2

90 mV (RMS) = 260 mV (p-p) and f1= 300 kHz,

Fig.4 3rd-order intermodulation distortion in I and Q channels (IM3).

f (MHz)

FCE184

1999 Dec 14 10

Philips Semiconductors Product specification

QPSK transmitter TDA8050

handbook, full pagewidth

50 Ω

DAC = 31.
f = 26.5 MHz.
Vi is variable to have a variable output voltage.

o(−1 dB)

150 Ω

150 Ω

V

G

G

max − 1

gain
(dB)

max

RF_IN
RF_INC

BUF_OUT

BUF_OUTC

V

Fig.5 Maximum gain and compression point.

Siemens V944

9 V

o

FCE185

75 Ω

V

o2

handbook, full pagewidth

BUF_OUT

BUF_OUTC

DAC = 28.

= 5 to 40 MHz.

f

i

= 200 mV sine wave.

V

i

= 55 dBmV (RMS value).

V

o

RF_IN
RF_INC

Fig.6 Harmonics of output section H2 and H3.

1999 Dec 14 11

150 Ω

150 Ω

Siemens V944

9 V

75 Ω

FCE186

Philips Semiconductors Product specification

QPSK transmitter TDA8050

handbook, full pagewidth

ISO

tot=Vo1

(dB) − Vo2(dB).

OUTEN = 0 V

V

= 100 mV

i(dif)

V

= 100 mV

i(dif)

OUTEN = 5 V

0 V

0 V

I_IN
I_INC

Q_IN
Q_INC

I_IN
I_INC

Q_IN
Q_INC

BUF_OUT

BUF_OUTC

DAC = 28

BUF_OUT

BUF_OUTC

DAC = 28

Fig.7 Isolation total.

150 Ω

150 Ω

150 Ω

150 Ω

Siemens V944

9 V

Siemens V944

9 V

75 Ω

75 Ω

V

o1

V

o2

FCE187

1999 Dec 14 12

Philips Semiconductors Product specification

QPSK transmitter TDA8050

APPLICATION INFORMATION

handbook, full pagewidth

CLK

DATA

EN

t

d(strt)

t

su

t

h(CLK)

T

cy

t

d(stp)

MBL113

Fig.8 3-wire bus timing.

Table 1 Data format; note 1

DATA ADDRESS

D11

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 AD1 AD0

first in

Modulator reference divider

Converter reference divider ratio

ratio

X X MP1

(2)

MP0

(2)

R7 R6 R5 R4 R3 R2 R1 R0 0 1

Control register

X X X OEN

(3)

CR2

(4)

CR1 CR0

(4)

DAC4

(5)

DAC3 DAC2 DAC1 DAC0 1 0

Main divider ratio

P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 1

last in

Notes

1. X = don’t care.

2. MP1 and MP0: modulator reference divider ratio (see Table 2).

3. When OEN (output enable) is at logic 0, output is disabled, at logic 1 output is enabled.

4. CR2 to CR0: converter synthesizer charge pump current (see Table 3).

5. When DAC4 to DAC0 is at logic 0 minimum gain is programmed, at logic 1 maximum gain is programmed.

1999 Dec 14 13

Philips Semiconductors Product specification

QPSK transmitter TDA8050

Table 2 Modulator reference divider ratio

MP1 MP0 PROGRAMMED RATIO

11 4
10 8
01 16

Table 3 Converter synthesizer charge pump current

CR2 CR1 CR0 LOCK_CONV

00001.2

00010.36

00100.36

00110.1
010−0.1
011−0.36
100−1.2

(1)

Icp (mA)

Note

1. LOCK_CONV is an internal signal.
When at logic 0 converter PLL is out-of-lock. When at logic 1 converter PLL is in-lock.

Table 4 Converter synthesizer: f

f

osc\fcomp

12.5 kHz 25 kHz 50 kHz 125 kHz

comp=fosc

/RD

1 MHz 80 40 20 8
4 MHz 320 160 80 32

Table 5 Converter synthesizer; ND = 4; f

\step 50 kHz 100 kHz 200 kHz 500 kHz

f

lo

=ND×NDR × f

lo

= NDR × step

comp

145 MHz 2900 1450 725 290
180 MHz 3600 1800 900 360

1999 Dec 14 14

Philips Semiconductors Product specification

QPSK transmitter TDA8050

handbook, full pagewidth

22 kΩ

22 kΩ

330pF370

10 kΩ

10 kΩ

pF

+5 V

Siemens

V944

100 Ω

100 Ω

BB133

(2×)

100 nF

100 nF

100 nF

100 nF

15 pF

10
pF

15 pF

18 kΩ

8.2 nF

150 Ω

+9 V

150 Ω

OUTEN

BUF_OUT

BUF_OUTC

AGND2

I_INC

Q_IN

Q_INC

AGND1

TKAMOD

22 nH

TKBMOD

CP_MOD

DVCC

I_IN

CLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

TDA8050

SW_CAP

32

RF_INC

31

RF_IN

30

AVCC2

29

RF_OUT

28

RF_OUTC

27

AVCC1

26

IF_FILTC

25

IF_FILT

24

LOCK

23

TKACONV

22

TKBCONV

21

TUNECONV

20

CP_CONV

19

68 nH

56 nH

100 pF

100 nF

100 nF

+5 V

100 nF

100 nF

+5 V

140 MHz

330 pF

680 Ω

47 pF

390 nH 390 nH

27 pF

18 pF

BB132

(2×)

39 pF

8.2
pF

39 pF

10 kΩ

+9 V

100
nF

10 kΩ

22 kΩ

10 kΩ

820 pF

22 kΩ

27 kΩ

10 nF

DATA DGND

15

EN

16

Fig.9 Application diagram.

1999 Dec 14 15

18

17

OSC_IN

4 MHz

18 pF

MBK982

Philips Semiconductors Product specification

QPSK transmitter TDA8050

INTERNAL PIN CONFIGURATION

SYMBOL PIN DESCRIPTION DC VOLTAGE

OUTEN 1 −
SW_CAP 32 1.7 V

1

FCE004

32

BUF_OUT 2 5.8 V
BUF_OUTC 3 5.8 V

2 3

FCE005

AGND2 4 0

4

FCE023

I_IN 5 2.5 V
I_INC 6 2.5 V

5

FCE006

6

1999 Dec 14 16

Philips Semiconductors Product specification

QPSK transmitter TDA8050

SYMBOL PIN DESCRIPTION DC VOLTAGE

Q_IN 7 2.5 V
Q_INC 8 2.5 V

7

FCE007

8

AGND1 9 0 V

9

FCE008

TKAMOD 10 3.1 V
TKBMOD 11 3.1 V

10 11

FCE009

CP_MOD 12 2.1 V

12

FCE010

DVCC 13 supply voltage 5 V

1999 Dec 14 17

Philips Semiconductors Product specification

QPSK transmitter TDA8050

SYMBOL PIN DESCRIPTION DC VOLTAGE

CLK 14 −

14

FCE011

DATA 15 −

15

FCE012

EN 16 −

16

FCE013

OSC_IN 17 2.9 V

V

CC

17

FCE014

DGND 18 0

18

1999 Dec 14 18

FCE015

Philips Semiconductors Product specification

QPSK transmitter TDA8050

SYMBOL PIN DESCRIPTION DC VOLTAGE

CP_CONV 19 2.1V

V

down

up

CC

19

FCE016

TUNECONV 20 V

20

FCE017

VT

TKBCONV 21 3.1V
TKACONV 22 3.1V

21

FCE018

22

LOCK 23 0 V

23

FCE019

1999 Dec 14 19

5V

Philips Semiconductors Product specification

QPSK transmitter TDA8050

SYMBOL PIN DESCRIPTION DC VOLTAGE

IF_FILT 24 2.1 V
IF_FILTC 25 2.1 V

24

FCE020

25

AVCC1 26 supply voltage 5 V
RF_OUTC 27 3.7V
RF_OUT 28 3.7V

27

28

FCE021

AVCC2 29 supply voltage 5 V
RF_IN 30 2.1 V
RF_INC 31 2.1V

30

1999 Dec 14 20

31

FCE022

Philips Semiconductors Product specification

QPSK transmitter TDA8050

PACKAGE OUTLINE

SO32: plastic small outline package; 32 leads; body width 7.5 mm

SOT287-1

D

c

y

Z

32

pin 1 index

1

e

17

A

2

A

16

w M

b

p

E

H

E

1

L

detail X

A

X

v M

A

Q

(A )

L

p

A

3

θ

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

mm

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

A

max.

2.65

0.10

OUTLINE

VERSION

SOT287-1

A1A2A3b

0.3

2.45

0.1

0.012

0.004

0.25

2.25

0.096

0.01

0.086

IEC JEDEC EIAJ

0.49

0.36

0.02

0.01

p

0.27

0.18

0.011

0.007

(1)E(1)

cD

20.7

20.3

0.81

0.80

REFERENCES

7.6

7.4

0.30

0.29

1.27

0.050

1999 Dec 14 21

eHELLpQZywv θ

10.65

10.00

0.419

0.394

1.4

0.055

1.1

0.4

0.043

0.016

1.2

1.0

0.047

0.039

0.25 0.1

0.25

0.010.01

EUROPEAN

PROJECTION

0.004

(1)

0.95

0.55

0.037

0.022

ISSUE DATE

95-01-25
97-05-22

o

8

o

0

Philips Semiconductors Product specification

QPSK transmitter TDA8050

SOLDERING
Introduction to soldering surface mount packages

Thistext gives averybrief insight to acomplextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages.Wave soldering is not alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardby screen printing,stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering andcooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackages with leads onfoursides, the footprintmust
be placedat a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering,the packagemust
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
forsurface mount devices (SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Dec 14 22

Philips Semiconductors Product specification

QPSK transmitter TDA8050

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitablefor SSOP and TSSOP packages with apitch (e) equal to or larger than0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Dec 14 23

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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545004/25/04/pp24 Date of release: 1999 Dec 14 Document order number: 9397 750 06555