Datasheet TDA8050A Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8050A

QPSK transmitter

Product specification
File under Integrated Circuits, IC02

1999 Nov 05

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

FEATURES

• Programmable gain

• PLL controlled carrier frequency

• 3-wire transmission bus

• 5 V supply voltage.

APPLICATIONS

• QPSK modulation.

GENERAL DESCRIPTION

TheQuadraturePhaseShiftKeying(QPSK)transmitter IC
is a monolithic bipolar IC dedicated to quadrature
modulation of the I and Q signals. It includes:

• Two double balanced mixers

• A balanced voltage controlled oscillator (VCO) with

0 to 90 degrees signal generation for modulation

• A phase locked loop (PLL) for IF frequency control

• A conversion mixer

• A PLL for RF frequency control

• A gain controlled output amplifier

• A 3-wire bus and an output buffer.

Two PLLs are incorporated, the first PLL includes:

• A fixed main divider

• A crystal oscillator and its programmable reference

divider

• A phase/frequency detector, combined with a fixed
charge pump.

The second PLL includes:

• A divide-by-four preamplifier

• A 12-bit programmable divider

• A crystal oscillator and its programmable reference

divider

• A phase/frequency detector, combined with a
programmable charge pump which drives the tuning
amplifier, including 30 V output.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

CC

f

c

V

o(max)

f

xtal

f

ref(MOD)

f

step

T

amb

supply voltage 4.75 5.00 5.25 V
output centre frequency 5 − 65 MHz
maximum output level − 55 − dBmV
crystal frequency 1 − 4 MHz
reference frequency for modulator synthesizer − 250 − kHz
frequency step size for converter synthesizer 100 − 500 kHz
ambient temperature 0 − 70 °C

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8050A SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1

1999 Nov 05 2

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1999 Nov 05 3

BLOCK DIAGRAM

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

I_IN

I_INC

Q_IN

Q_INC

DVCC

DGND

CLK

DATA

EN

LOCK

5
6

7
8

13

18
14
15
16

23

CHARGE

PUMP

CP_MOD

AVCC1

26

AGND1

9

RF_OUTC

RF_OUT

2524 28

RF_INCIF_FILTC

RF_INIF_FILT

27

30 31

SW_CAP

MODULATOR CONVERTER

×

Σ

×

×

3-WIRE BUS TRANCEIVER

DIGITAL

PHASE

COMPARATOR

PROGRAMMABLE

FIXED

MAIN DIVIDER

REF DIVIDER

90 0

1/2

TDA8050A

101211 17 22 21

TKAMOD

TKBMOD TKACONV

OSC_IN TKBCONV

DAC

PROGRAMMABLE

MAIN DIVIDER

PROGRAMMABLE

REF DIVIDER

AVCC2

32

DIGITAL

PHASE

COMPARATOR

20 19

TUNECONV CP_CONV

AGND2

29

PROGRAM-

MABLE

CHARGE

PUMP

4

1

OUTEN

3

BUF_OUTC

2

BUF_OUT

FCE433

Fig.1 Block diagram.

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

PINNING

SYMBOL PIN DESCRIPTION

OUTEN 1 output enable
BUF_OUT 2 output amplifier balanced output
BUF_OUTC 3 output amplifier balanced output
AGND2 4 converter analog ground 2
I_IN 5 I balanced input
I_INC 6 I balanced input
Q_IN 7 Q balanced input
Q_INC 8 Q balanced input
AGND1 9 modulator analog ground 1
TKA_MOD 10 modulator VCO tank circuit input 2
TKB_MOD 11 modulator VCO tank circuit input 1
CP_MOD 12 modulator charge pump output for PLL loop filter
V

CCD

CLK 14 3-wire bus serial control clock
DATA 15 3-wire bus serial control data
EN 16 3-wire bus serial control enable
OSC_IN 17 crystal oscillator input
DGND 18 digital ground
CP_CONV 19 converter charge pump output for PLL loop filter
TUNE_CONV 20 tuning voltage output for converter VCO
TKB_CONV 21 converter VCO tank circuit input 1
TKA_CONV 22 converter VCO tank circuit input 2
LOCK 23 lock detect signal
IF_FILT 24 IF balanced output to filter
IF_FILTC 25 IF balanced output to filter
V

CCA1

RF_OUTC 27 RF balanced output to filter
RF_OUT 28 RF balanced output to filter
V

CCA2

RF_IN 30 RF balanced input to programmable amplifier
RF_INC 31 RF balanced input to programmable amplifier
SW_CAP 32 switch capacitor

13 digital supply voltage

26 modulator analog supply voltage

29 converter analog supply voltage

1999 Nov 05 4

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

FUNCTIONAL DESCRIPTION

The I and Q signals are balanced analog signals of
400 mV (p-p). These are mixed by two double balanced
mixers with the output signal generated by a first local
oscillator, to provide the modulated signal.

The modulated signal is then filtered by an IF filter. This
filtered signal, together a signal generated by a second
local oscillator, is converted by a balanced mixer to
produce the QPSK signal.

The QPSK signal is amplified by a gain controlled output
amplifier to a level suitable for transmission. The gain of
the amplifier is bus controlled and this amplifier can be
disabled when not transmitting, to provide signal

OUTEN

BUF_OUT

BUF_OUTC

AGND2

I_IN

I_INC

Q_IN

Q_INC

AGND1
TKAMOD
TKBMOD
CP_MOD

DVCC

CLK

DATA

EN

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

TDA8050A

FCE434

32

SW_CAP

31

RF_INC
RF_IN

30

AVCC2

29

RF_OUT

28

RF_OUTC

27

AVCC1

26
25

IF_FILTC

24

IF_FILT

23

LOCK

22

TKACONV

21

TKBCONV

20

TUNECONV

19

CP_CONV

18

DGND

17

OSC_IN

attenuation.
The amplified signal is applied to an on-chip amplifier with

two balanced outputs (open collector) connected to two
off-chip resistors (values 150 Ω), in turn connected to 9 V.
The balanced outputs drive a 2 : 1 transformer (Siemens
V944) loaded with 75 Ω, which gives an output level of
55 dBmV. The output frequency range of the transmitter is
5 to 65 MHz.

The frequency of the first local oscillator operates at twice
the frequency (i.e. 280 MHz), fixed by a PLL implemented
in the circuit.

Thefrequencyofthesecondlocaloscillatoroperatesinthe
145 to 205 MHz bandwidth and can be programmed
through the PLL implemented in the circuit.

The VCOs of both the first and second local oscillators
need an external LC tank circuit with two varicap diodes.

The data sent to the PLL is loaded in bursts framed by
signal EN. Programming rising clock edges and their
appropriate data bits are ignored until EN goes active
(LOW). The internal latches are updated with the latest
programming data when EN returns to inactive (HIGH).
Only the last 14 bits are stored in the programming
register.

Fig.2 Pin configuration.

1999 Nov 05 5

No check is made on the number of clock pulses received
during the time that programming is enabled. If EN goes
high while CLK is still LOW, a wrong active clock edge will
be generated, causing a shift of the data bits. At power up,
EN should be HIGH. The lock detector output LOCK is
HIGH when both PLLs are in lock.

The main divider ratio and the reference divider ratios are
provided via the serial bus. A control register controls the
Digital-to-Analog-Converter (DAC), the output amplifier
and the charge pump currents (see Tables 1, 2 and 3).

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

t

sc

V

MAX

V

o(tune)

V

O(buf)

P

tot

T

amb

T

stg

T

j(max)

HANDLING

supply voltage −0.3 +6.0 V
short-circuit time (every pin to VCC or GND) − 10 s
voltage on all pins except BUF_OUT, BUF_OUTC and TUNE_CONV −0.3 V

CC

V
output tuning voltage −0.3 +30 V
output buffer voltage on pins BUF_OUTand BUF_OUTC − 10 V
maximum power dissipation − 940 mW
ambient temperature 0 70 °C
storage temperature −40 +150 °C
maximum junction temperature − 150 °C

Human Body Model (HBM): The IC pins withstand 2 KV, except pins 27 and 28 (1750 V).
Machine Model (MM): The IC pins withstand 100 V.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 63 K/W

CHARACTERISTICS

Measured in application circuit with the following conditions; V

=5V, T

CC

=25°C; all AC units are RMS values,

amb

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA1

modulator analog supply

4.75 5 5.25 V

voltage

I

CCA1

modulator analog supply

33 39 45 mA

current

V

CCA2

I

CCA2

I

CC(buf)

V

CCD

I

CCD

V

CC(tune)

converter analog supply voltage 4.75 5 5.25 V
converter analog supply current 39 47 55 mA
buffer output supply current 39 43 47 mA
digital supply voltage 4.75 5 5.25 V
digital supply current 20.5 23.5 26.5 mA
tuning supply voltage −− 30 V

1999 Nov 05 6

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Quadrature modulator
I and Q inputs

V

i(DC)

V

i(p-p)

f

i(max)

Z

i(dif)

B

(1 dB)

Modulator

f

c

∆A amplitude imbalance see Fig.3 −− ±1dB
∆Φ phase imbalance −− ±2 deg

LO

(sup)

Z

o(dif)

Modulator VCO

F

OSC(mod)

Converter output

V

O

∆V

O

f

c

Z

o(dif)

IP

3

H

2

H

3

S

O

Converter VCO

f

osc(min)

f

osc(max)

input DC level − 0.5 × VCC− V
signal input level (balanced)

indicative − 400 500 mV

(peak-to-peak)
I and Q maximum input

indicative − 10 − MHz

frequency
differential input impedance − 4.4 − kΩ
1 dB bandwidth amplifier indicative − 10 − MHz

output centre frequency −− 140 MHz

LO suppression see Fig.3 −−28 − dBc
differential output impedance − 1.8 − kΩ

oscillation frequency −− 280 MHz

output level f = 5 MHz; Vi= 100 mV

at

dif

37.5 40 42.5 dBmV

I and Q inputs

output flatness f = 5 to 65 MHz; Vi= 100 mV

−− 2dB

dif

at I and Q inputs
output centre frequency 5 − 65 MHz
differential output impedance − 150 −Ω
3rd order interception point at

see Fig.4 −− 52 dBmV
I input

2nd order harmonic of
5 to 65 MHz signal

3rd order harmonic of
5 to 65 MHz signal

mixer spurious outputs of
5 to 65 MHz signal

f = 10 to 130 MHz;

Vi= 100 mV

at I and Q inputs

dif

f = 15 to 195 MHz;

Vi= 100 mV

at I and Q inputs

dif

f = 5 to 65 MHz; Vi= 100 mV

at I and Q inputs

−− −40 dBc

−− −40 dBc

−− −45 dBc

dif

minimum oscillation frequency −− 145 MHz
maximum oscillation frequency 205 −−MHz

1999 Nov 05 7

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Programmable gain and output buffer; note 1

Z

i(dif)

∆G output level step size −− 2dB
∆buf

O

V

o

∆V

o

V

IL(ENL)

V

IH(ENH)

ISO disable isolation V

G

V(max)

V

o(1dB)

H

2

H

3

Overall; note 1

Φ

osc

H

2

H

3

S

o

IP

3

ISO

tot

C/N carrier to noise ratio at final

differential input impedance − 5.6 − kΩ

output level adjust range Vi= 30 dBmV sine wave

32 39 − dB
65 MHz at pins
RF_IN and RF_INC;
DAC = 0 to 31

operational output level − 55 − dBmV
output flatness f = 5 to 65 MHz; Vi= 30 dBmV

− 35dB

sine wave; DAC = 28

output controlled enable low output buffer on −− 0.8 V
output controlled enable high output buffer off 2.4 −−V

= 100 mV

i

; DAC= 28;

dif

−35 −90 − dBc

f = 65 MHz; OE = 0,5 V

maximum gain see Fig.5 17 18.5 − dB
1 dB compression point see Fig.5 58 −−dBmV
2nd order harmonic of

5 to 65 MHz signal
3rd order harmonic

of 5 to 65 MHz signal

f = 10 to 65 MHz; see Fig.6 −− −45 dBc
f = 65 to 120 MHz; see Fig.6 −− −35 dBc
f = 15 to 65 MHz; see Fig.6 −− −45 dBc
f = 65 to 120 MHz; see Fig.6 −− −35 dBc

phase noise at 10 kHz; note 2 −−75 − dBc/Hz

at 100 kHz; note 2 −−95 − dBc/Hz

2nd order harmonic of
5 to 65 MHz signal

3rd order harmonic
of 5 to 65 MHz signal

spurious signals of 5 to 65 MHz
signal

3rd order interception point at

f = 10 to 130 MHz;
Vin= 100 mV
inputs; V

at I and Q

dif

= 55 dBmV

out

f = 15 to 195 MHz;
Vin= 100 mV
inputs; V

at I and Q

dif

= 55 dBmV

out

f = 5 to 65 MHz; Vin= 100 mV
at I and Q inputs;
V

= 55 dBmV

out

−− −40 dBc

−− −40 dBc

−− −45 dBc

dif

−− 49 dBmV

I input
total isolation at I/Q midrange see Fig.7 −−90 −65 dBc

output at 2 MHz from carrier

= 100 mV

V

in

V

= 35 to 55 dBmV;

out

;

dif

− 113 − dBc/Hz

f = 65 MHz

1999 Nov 05 8

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Crystal oscillator

f

xtal

Z

i

V

i(DC)

Modulator synthesizer

f

ref(mod)

RDR1 programmablereferencedivider

ND1 fix main divider ratio − 1120 −
I

(cp)

Converter synthesizer

f

step

RD2 fix reference divider ratio − 2 −
RDR2 programmablereferencedivider

ND2 fix main divider ratio − 4 −
NDR2 programmable main divider

3-wire bus

V

IL

V

IH

Lock detect pin

V

O(lock)

V

O(unlock)

Serial control clock

f

clk

t

su

t

h(CLK)

t

d(strt)

t

d(stp)

Notes

1. All specification points of the output section and the overall circuit are measured after the 2 : 1 transformer (Siemens
V944) loaded with 75 Ω.

2. Overall phase noise:
a) Converter: I
b) I and Q = 100 mV
c) DAC = 28.
d) f = 65 MHz.

3. The crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is serial resonant with a load
capacitance of 18 to 20 pF. The connection to VCC is preferred but it might also be to GND.

crystal frequency note 3 1 − 4 MHz
input impedance f

= 4 MHz 600 1200 −Ω

xtal

DC input level − 2.9 − V

reference frequency − 250 − kHz

4 − 16

ratio

charge-pump current fixed − 0.30 − mA

step size 100 − 500 kHz

see Tables 4 and 5 4 − 160

ratio

see Tables 4 and 5 290 − 1800

ratio

input LOW level −− 0.8 V
input HIGH level 2.4 −−V

output voltage (LOCK) − 5 − V
output voltage (UNLOCK) − 0.02 − V

clock frequency − 330 − kHz
input data to CLK set-up time see Fig.8 − 2 −µs
input data to CLK hold time see Fig.8 − 1 −µs
delay to rising clock edge see Fig.8 − 3 −µs
delay from last clock edge see Fig.8 − 3 −µs

= 0.36 mA; f

(cp)

dif

.

= 25 kHz.

ref

1999 Nov 05 9

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

IF_FILT

measure 2 f

The amplitude imbalance and the LO suppression are measured in the spectrum of the signal measured at the output IF_FILT
and are defined in the following conditions:

measure 1: I input frequency = 500 kHz; I input level = 400 mV (p-p) sine wave; unused input as 0 V differential.
measure 2: Q input frequency = 500 kHz; Q input level = 400 mV (p-p) sine wave; unused input as 0 V differential.

lo(2)

imbalance

LO

(sup)

measure 1 f

lo(2)

frequency

Fig.3 Imbalance and LO suppression.

FCE435

1999 Nov 05 10

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

handbook, full pagewidth

50 Ω
50 Ω

500 kHz 300 kHz

I_IN
I_INC

Q_IN
Q_INC

RF_OUT

RF_OUTC

SPECTRUM

ANALYZER

IM3

64.1 64.5 64.7 65 40 65.1 65.3 65.5 65.7

f1 = 300 kHz, f2 = 500 kHz and frf= 65 MHz.

f (MHz)

FCE436

Fig.4 IP3 set-up measurement.

1999 Nov 05 11

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

handbook, full pagewidth

50 Ω

G

G

max − 1

DAC = 31.
f = 65 MHz.
Vi variable to have a variable output voltage.

gain
(dB)

max

RF_IN
RF_INC

BUF_OUT

BUF_OUTC

V

o(−1 dB)

150 Ω

150 Ω

Siemens V944

9 V

V

o

FCE437

75 Ω/50 Ω

ADAPTER

SPECTRUM

ANALYZER

handbook, full pagewidth

DAC = 28.
f = 5 to 65 MHz.
Vi such that Vo= 55 dBmV (rms) at 5 MHz.

Fig.5 Maximum gain and compression point.

Siemens V944

RF_IN
RF_INC

BUF_OUT

BUF_OUTC

150 Ω

9 V

150 Ω

FCE438

Fig.6 Harmonics of output sections H2 and H3.

75 Ω/50 Ω
ADAPTER

SPECTRUM

ANALYZER

1999 Nov 05 12

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

handbook, full pagewidth

ISO

tot=Vout1(dB)

frf= 65 MHz.

− V

OUTEN = 0 V

V

i(dif)

V

i(dif)

OUTEN = 5 V

.

out2(dB)

= 100 mVdif

= 100 mVdif

0 V

0 V

I_IN
I_INC

Q_IN
Q_INC

I_IN
I_INC

Q_IN
Q_INC

BUF_OUT

BUF_OUTC

DAC = 28

BUF_OUT

BUF_OUTC

DAC = 28

Fig.7 Total isolation (ISO

150 Ω

150 Ω

150 Ω

150 Ω

Siemens V944

9 V

Siemens V944

9 V

).

tot

75 Ω/50 Ω
ADAPTER

75 Ω/50 Ω
ADAPTER

FCE439

SPECTRUM

ANALYZER

SPECTRUM

ANALYZER

1999 Nov 05 13

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

APPLICATION INFORMATION

t

h(CLK)

T

cy

t

d(stp)

FCE440

CLK

DATA

EN

t

d(strt)

t

su

Fig.8 3-wire bus timing.

Table 1 Data format; note 1

DATA ADDRESS

D11

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 AD1 AD0

first in

Modulator reference divider

Converter reference divider ratio

ratio

X X MP1

(2)

MP0

(2)

R7 R6 R5 R4 R3 R2 R1 R0 0 1

Control register

XXX OEN

(3)

CR2

(4)

CR1 CR0

(4)

DAC4

(5)

DAC3 DAC2 DAC1 DAC0 1 0

Main divider ratio

P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 1

last in

Notes

1. X = don’t care.

2. MP1 and MPO: modulator reference divider ratio (see Table 2).

3. When OEN (output enable) is at logic 0, output is disabled; at logic 1, output is enabled.

4. CR2 and CRO: converter synthesizer charge pump current (see Table 3).

5. When DAC4 to DAC0 is at logic 0, minimum gain is programmed; at logic 1, maximum gain is programmed.

1999 Nov 05 14

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

Table 2 Modulator reference divider ratio

MP1 MP0 PROGRAMMED RATIO

11 4
10 8
01 16

Table 3 Converter synthesizer charge pump current

CR2 CR1 CR0 LOCK_CONV

000 0 1.2
0 0 0 1 0.36
0 0 1 0 0.36
001 1 0.1
010 X 0.1
0 1 1 X 0.36
100 X 1.2

(1)

ICP(mA)

Note

1. LOCK_CONV is an internal signal. When at logic 0, converter PLL is out-of-lock. When at logic 1, converter PLL is
in-lock.

Table 4 Converter synthesizer
f

comp=fosc

/RD.

f

osc\fcomp

25 kHz 50 kHz 125 kHz

1 MHz 40 20 8
4 MHz 160 80 32

Table 5 Converter synthesizer;
ND = 4 f_lo = ND × NDR × f

\step 100 kHz 200 kHz 500 kHz

f

lo

= NDR × step.

comp

145 MHz 1450 725 290
205 MHz 2050 1025 410

1999 Nov 05 15

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

handbook, full pagewidth

22 kΩ

330 pF

22 kΩ

22 kΩ

10 kΩ

10 kΩ

330 pF

+5 V

Siemens

V944

100 Ω

100 Ω

BB133

(2×)

15 pF

15 pF

10 kΩ

8.2 nF

100 nF

100 nF

100 nF

100 nF

10

pF

150 Ω

+9 V

150 Ω

OUTEN

BUF_OUT

BUF_OUTC

AGND2

Q_INC

AGND1

TKAMOD

22 nH

TKBMOD

CP_MOD

I_IN

I_INC

Q_IN

DVCC

CLK

1

2

3

4

5

6

7

8

TDA8050A

9

10

11

12

13

14

32

31

30

29

28

27

26

25

24

23

22

21

20

19

SW_CAP

RF_INC

RF_IN

AVCC2

RF_OUT

RF_OUTC

AVCC1

IF_FILTC

68 nH

IF_FILT

LOCK

TKACONV

56 nH

TKBCONV

TUNECONV

CP_CONV

100 nF

100 nF

+5 V

100 nF

100 nF

140 MHz

330 pF

680 Ω

390 nH 390 nH

+5 V

18 pF

BB132

(2×)

39 pF

4.7pF

39 pF

10 kΩ

+30 V

47 pF

27 pF

100 nF

10 kΩ

10 kΩ

22 kΩ

820 pF

22 kΩ

27 kΩ

10 nF

DATA DGND

15

EN

16

Fig.9 Application diagram.

1999 Nov 05 16

18

17

OSC_IN

4 MHz

FCE441

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

INTERNAL PIN CONFIGURATION

SYMBOL PIN DESCRIPTION DC VOLTAGE

OUTEN 1 n.a.
SW_CAP 32 1.7 V

1

FCE442

32

BUF_OUT 2 5.8 V
BUF_OUTC 3 5.8 V

2 3

FCE443

AGND2 4 0

4

FCE444

I_IN 5 2.5 V
I_INC 6 2.5 V

5

FCE445

6

1999 Nov 05 17

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

SYMBOL PIN DESCRIPTION DC VOLTAGE

Q_IN 7 2.5 V
Q_INC 8 2.5 V

7

FCE446

8

AGND1 9 0

9

FCE447

TKA_MOD 10 3.1 V
TKB_MOD 11 3.1 V

10 11

FCE448

CP_MOD 12 2.1 V

12

FCE449

V

CCD

13 supply voltage 5 V

1999 Nov 05 18

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

SYMBOL PIN DESCRIPTION DC VOLTAGE

CLK 14 n.a.

14

FCE450

DATA 15 n.a.

15

FCE451

EN 16 n.a.

16

FCE452

OSC_IN 17 2.9 V

V

CC

17

FCE453

DGND 18 0 V

18

FCE454

1999 Nov 05 19

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

SYMBOL PIN DESCRIPTION DC VOLTAGE

CP_CONV 19 2.1 V

V

down

up

CC

19

FCE455

TUNE_CONV 20 V

20

FCE456

VT

TKB_CONV 21 3.1 V
TKA_CONV 22 3.1 V

21

FCE457

22

LOCK 23 0 V

23

FCE458

1999 Nov 05 20

5V

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

SYMBOL PIN DESCRIPTION DC VOLTAGE

IF_FILT 24 2.1 V
IF_FILTC 25 2.1 V

25

V

CCA1

24

FCE459

26 supply voltage 5 V
RF_OUTC 27 3.7 V
RF_OUT 28 3.7 V

28

FCE460

V

CCA2

27

29 supply voltage 5 V
RF_IN 30 2.1 V
RF_INC 31 2.1 V

30

31

1999 Nov 05 21

FCE461

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

PACKAGE OUTLINE

SO32: plastic small outline package; 32 leads; body width 7.5 mm

SOT287-1

D

c

y

Z

32

pin 1 index

1

e

17

A

2

A

16

w M

b

p

E

H

E

1

L

detail X

A

X

v M

A

Q

(A )

L

p

A

3

θ

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE
VERSION

SOT287-1

A

max.

2.65

0.10

A1A

0.3

0.1

0.012

0.004

A3b

0.49

0.36

0.02

0.01

p

0.27

0.18

0.011

0.007

2

2.45

0.25

2.25

0.096

0.01

0.086

IEC JEDEC EIAJ

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1)

cD

20.7

20.3

0.81

0.80

REFERENCES

7.6

7.4

0.30

0.29

1.27

0.050

1999 Nov 05 22

eHELLpQZywv θ

10.65

10.00

0.419

0.394

1.4

0.055

1.1

0.4

0.043

0.016

1.2

1.0

0.047

0.039

0.25 0.1

0.25

0.010.01

EUROPEAN

PROJECTION

0.004

(1)

0.95

0.55

0.037

0.022

ISSUE DATE

95-01-25
97-05-22

o

8

o

0

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

SOLDERING
Introduction to soldering surface mount packages

Thistext gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave solderingis not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
forsurface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Nov 05 23

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Nov 05 24

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

NOTES

1999 Nov 05 25

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

NOTES

1999 Nov 05 26

Philips Semiconductors Product specification

QPSK transmitter TDA8050A

NOTES

1999 Nov 05 27

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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545004/25/01/pp28 Date of release: 1999 Nov 05 Document order number: 9397 750 06123