Datasheet TDA8046 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8046

Multi-mode QAM demodulator

Product specification
Supersededs data of 1996 Jul 23
File under Integrated Circuits, IC02

1996 Nov 19

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

CONTENTS

1 FEATURES
2 APPLICATION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION

7.1 Functional description of the individual blocks

7.1.1 Quadrature demodulator and half Nyquist filter

7.1.2 Equalizer

7.1.3 Lock detector

7.1.4 Carrier recovery

7.1.5 Clock recovery

7.1.6 AGC

7.1.7 Offset control

7.1.8 Loop amplifiers

7.1.9 Output formatter

7.1.10 Boundary scan

7.1.11 I2C-bus interface

7.1.12 I2C-bus write parameters

7.1.13 I2C-bus read parameters
8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 DEMODULATOR AND HALF NYQUIST

FILTER CHARACTERISTICS
11 LOCK DETECTOR CHARACTERISTICS
12 CARRIER RECOVERY CHARACTERISTICS
13 CLOCK RECOVERY CHARACTERISTICS
14 AGC CHARACTERISTICS
15 INTEGRATED LOOP AMPLIFIERS

CHARACTERISTICS
16 CHARACTERISTICS OF DIGITAL INPUTS

AND OUTPUTS
17 PACKAGE OUTLINE
18 SOLDERING

18.1 Introduction

18.2 Reflow soldering

18.3 Wave soldering

18.4 Repairing soldered joints
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS
21 PURCHASE OF PHILIPS I2C COMPONENTS

1996 Nov 19 2

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

1 FEATURES

• Different modulation schemes: 4, 16, 32,

64 and 256-QAM

• Digital demodulator and square root raised cosine

Nyquist filter with roll-off of 15% or 20%

• High performance adaptive equalizer (no training

sequence needed)

• Digital detectors for generation of required control

voltages for carrier recovery, clock recovery and AGC

• Input format: Straight binary or 2’s complement
(up to 9 bits, TTL compatible)

• Output format: 8-bit wide bus (CMOS compatible)

2

C-bus interface to initialize and monitor the

• I
demodulator. When no I2C-bus usage; 64-QAM,
20% roll-off factor in default mode

• 5 V peripheral and analog supply voltage

• 3.3 V core supply voltage

• Boundary scan test.

• Digital-to-analog converters and operational amplifiers

allowing high flexibility for selection of the (PLL) loop

2 APPLICATION

time constants

• High maximum symbol rate (r

) of 7 Msymbols/s

s

Demodulation for digital cable TV and cable modem.

3 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDD(core)

V

DDD

V

DDA

I

DDD(core)

I

DDD

I

DDA

r

s

core supply voltage 3.00 3.30 3.60 V
digital peripheral supply voltage 4.75 5.00 5.25 V
analog supply voltage 4.75 5.00 5.25 V
core supply current V
digital peripheral supply current V
analog supply current V

DDD(core)
DDD
DDA

= 3.3 V; note 1 − 100 − mA
= 5 V; note 1 − 14 − mA
= 5 V; note 1 − 16 − mA

symbol rate −−7 Msym/s
IL implementation loss note 2 − 0.7 − dB
α Nyquist roll-off (programmable) − 15 or 20 − %
SNR

lock

signal-to-noise ratio for locking a

21 −−dB

64-QAM constellation

signal-to-noise ratio for locking a

27 −−dB

256-QAM constellation

Notes

1. The supply currents are specified for the maximum symbol frequency.

2. The implementation loss (IL) of the demodulator is defined as the distance between the measured and theoretical
BER curve as function of signal-to-noise ratio at a BER = 10
This performance depends on the chosen loop parameters (see

−6

for a back-to-back measurement at the IF frequency.

Application notes

).

4 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8046H QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);

PACKAGE

SOT319-2

body 14 × 20 × 2.8 mm

1996 Nov 19 3

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

5 BLOCK DIAGRAM

book, full pagewidth

SSD1 to 12

V

DDD1 to 9

V

TMS

TDO

TDI

TRST

TCK

TEST3

TEST2

TEST1

7, 12, 14, 17,

24, 26, 31, 34,

46, 50, 61, 64

6, 13, 16, 

25, 33, 38, 

45, 51, 63

44

47

48

42

SCAN TEST

BOUNDARY

43

39

40

41

C-BUS 

2

I

TDA8046

CONTROL

DO0

DO7 to

27 to 30

20 to 23

FINE AGC

CONTROL

OFFSET

CONTROL

SQUARE ROOT

to DACs

internal clock for

digital processing

srs

2r

s

CLOCK GENERATOR

4r

CLKSDV

CLKOUT

32

18

OUTPUT

FORMATTER

FINE AGC

EQUALIZER

OFFSET

PHASE

DIGITAL

ROTATOR

SQUARE ROOT

RAISED COSINE

RAISED COSINE

DEMODULATOR

INPUT

TATION

REPRESEN-

CARRIER

RECOVERY



NCO

CONTROL

CLOCK

RECOVERY

AGC

COARSE

ref

ref3

I

V

DAC

ref1Iref2Iref3

I

BIAS

GENERATOR

ref

ANALOG SECTION

V

ref

ref2

I

V

DAC

ref

ref1

I

V

DAC

565552

5857

59

60

5453

MGG198

CARREC

V

CARTC

V

BIAS

I

CLKREC

V

CLKTC

V

SSA

V

DDA

V

AGC

V

AGCTC

V

Fig.1 Block diagram.

15

35

36

37

SCL

SDA

62

A0

CLK

CLKADC

1 to 5,

8 to 11

DIN0

to

DIN8

1996 Nov 19 4

49

PRESET

19

CLKT

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

6 PINNING

SYMBOL PIN I/O DESCRIPTION

DIN0 1 I digital input bit 0 (LSB)
DIN1 2 I digital input bit 1
DIN2 3 I digital input bit 2
DIN3 4 I digital input bit 3
DIN4 5 I digital input bit 4
V

DDD1

V

SSD1

DIN5 8 I digital input bit 5
DIN6 9 I digital input bit 6
DIN7 10 I digital input bit 7
DIN8 11 I digital input bit 8 (MSB)
V

SSD2

V

DDD2

V

SSD3

CLKADC 15 O clock output to ADC (4 × r
V

DDD3

V

SSD4

CLKSDV 18 O clock symbol data valid output
CLKT 19 I for test purpose only
DO7 20 O parallel data output (bit 7)
DO6 21 O parallel data output (bit 6)
DO5 22 O parallel data output (bit 5)
DO4 23 O parallel data output (bit 4)
V

SSD5

V

DDD4

V

SSD6

DO3 27 O parallel data output (bit 3)
DO2 28 O parallel data output (bit 2)
DO1 29 O parallel data output (bit 1)
DO0 30 O parallel data output (bit 0)
V

SSD7

CLKOUT 32 I output formatter clock output
V

DDD5

V

SSD8

SCL 35 I serial clock input (I
SDA 36 I/O serial data input/output (I
A0 37 I hardware address input (I
V

DDD6

TEST3 39 I test input 3 (normally connected to ground)
TEST2 40 I test input 2 (normally connected to ground)

6 supply digital peripheral supply voltage 1 (+5 V)
7 supply digital ground 1; for input peripheral and core

12 supply digital ground 2; for core and clock buffers
13 supply digital supply voltage 2; for core and clock buffers (+3.3 V)
14 supply digital peripheral ground 3

)

s

16 supply digital peripheral supply voltage 3 (+5 V)
17 supply digital ground 4; for core

24 supply digital peripheral ground 5
25 supply digital peripheral supply voltage 4 (+5 V)
26 supply digital ground 6; for core

31 supply digital peripheral ground 7

33 supply digital peripheral supply voltage 5 (+5 V)
34 supply digital peripheral ground 8

2

C-bus)

2

C-bus)

2

C-bus)

38 supply digital peripheral supply voltage 6 (+5 V)

1996 Nov 19 5

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

SYMBOL PIN I/O DESCRIPTION

TEST1 41 I test input 1 input (normally connected to ground)
TRST 42 I optional asynchronous reset input
TCK 43 I dedicated test clock input
TMS 44 I input control signal
V

DDD7

V

SSD9

TDO 47 O serial test data output
TDI 48 I serial test data input
PRESET 49 I set device into default mode input
V

SSD10

V

DDD8

I

BIAS

V

AGCTC

V

AGC

V

CARTC

V

CARREC

V

CLKTC

V

CLKREC

V

SSA

V

DDA

V

SSD11

CLK 62 I clock input (4 × r
V

DDD9

V

SSD12

45 supply digital supply voltage 7; for core (+3.3 V)
46 supply digital ground 9; for core

50 supply digital ground 10; for the digital section of the analog block
51 supply digital supply voltage 8; for the digital section of the analog block (+5 V)
52 I input bias current for DACs
53 O inverted operational amplifier input voltage for loop filtering
54 O analog output voltage for AGC
55 O inverted operational amplifier input voltage for carrier recovery loop

filtering
56 O analog output voltage for carrier recovery
57 O inverted operational amplifier input voltage for clock recovery loop

filtering
58 O analog output voltage for clock recovery
59 supply analog ground
60 supply analog supply voltage (+5 V)
61 supply digital ground 11; for clock

)

s

63 supply digital supply voltage 9; for clock
64 supply digital peripheral ground 12

1996 Nov 19 6

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

DDD9

handbook, full pagewidth

DIN0
DIN1

DIN2
DIN3

DIN4

V

DDD1

V

SSD1

DIN5
DIN6
DIN7
DIN8

V

SSD2

V

DDD2

V

SSD3

CLKADC

V

DDD3

V

SSD4

CLKSDV

CLKT

SSD12

V

V
64

63
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19

20

21

CLK

62

22

SSD11

V
61

23

DDA

V
60

TDA8046

24

SSA

V
59

25

CLKREC

V

V
58

57

26

27

CLKTC

V
56

28

CARREC

CARTC

V
55

29

AGC

V
54

30

AGCTC

V
53

31

BIAS

I
52

32

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

MGG197

V

DDD8

V

SSD10

PRESET
TDI
TDO
V

SSD9

V

DDD7

TMS
TCK
TRST
TEST1
TEST2
TEST3
V

DDD6

A0
SDA
SCL
V

SSD8

V

DDD5

DO7

DO6

DO5

DO4

SSD5

V

DDD4

V

Fig.2 Pin configuration.

1996 Nov 19 7

SSD6

V

DO3

DO2

DO1

DO0

SSD7

V

CLKOUT

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

7 FUNCTIONAL DESCRIPTION

Figure 3 shows the application of the TDA8046
multi-mode QAM demodulator. The frequency of the IF
signal (IF

) is down converted to a frequency that

QAM

equals the symbol rate (rs) by a mixer which is driven from
a local oscillator with a frequency of f

CAR=fIF+rs

.
After low pass filtering this baseband signal is applied to an
external 8 or 9-bit ADC.

For 256-QAM, a 9-bit ADC is preferred, for the other
modes an 8-bit ADC is sufficient.

The multi-mode QAM demodulator has digital detectors for
AGC, carrier recovery and clock recovery. The on-chip
DACs translate the detector values to analog control

handbook, full pagewidth

IF

RF

signal

SAWTUNER

QAM

currents which are then integrated by a loop filter.
To perform this loop filtering, an operational amplifier is
integrated after each DAC.

The carrier recovery consists of a two-loop system.
The outer loop is shown in Fig.3, and controls both phase
and frequency at a low speed. The inner loop controls the
carrier phase at a high speed (wide loop bandwidth).

The AGC also consists of two loops; the outer loop is the
coarse AGC and one inner loop is the fine AGC.

The recovered symbols are converted into bits according
to a demapping scheme and represented at the output in
an 8-bit parallel output format. The QAM demodulator can

2

be initialized and monitored by the I

8 or 9 bits

f

clk

f

CAR

= fIF + r

LPF ADC

s

C-bus interface.

clock recovery

carrier recovery

AGC

TDA8046

2

I

C-BUS

Fig.3 Application with multi-mode QAM demodulator.

DO7 to DO0
CLKOUT
CLKSDV

MGG167

1996 Nov 19 8

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

7.1 Functional description of the individual blocks

The functional block diagram of the multi-mode QAM
demodulator is illustrated in Fig.1. This section describes
the individual blocks in the demodulator. After adaptation
for the used input format (2’s complement or binary), the
input signal is demodulated in the I and Q baseband
signals which are applied to the inputs of the half-Nyquist
filter (equals square root raised cosine). To avoid
overloading of the ADC, an AGC detector is placed after
the adaptation for the input format. The control value for
the clock recovery is generated after half Nyquist filtering.
The echoes created in the cable network are reduced
significantly in the equalizer.

The equalizer produces a ‘clean’ constellation diagram
from which the information for the carrier recovery is
derived. This constellation is also applied to the output
formatter which demaps the transmitted symbols in
corresponding bits. The carrier recovery and lock
detection functions are based on the equalizer output.
The output of the equalizer is applied to an output
formatter, which translates the symbol bits to a FEC input
format. The digital outputs of the clock recovery, AGC, and
carrier recovery section are converted into currents which
are integrated by the loop filters.
To make these loop filters active, operational amplifiers
are integrated on the chip.

The TDA8046 can handle five different digital modulation
schemes; 4, 16, 32, 64 and 256-QAM. These schemes

2

are selectable via the I

7.1.1 Q

UADRATURE DEMODULATOR AND HALF NYQUIST

FILTER

C-bus interface.

Quadrature demodulation is accomplished after selection
of the appropriate input format via the I2C-bus.
The in-phase and quadrature components are both
applied to a half Nyquist filter. In default mode, this filter
gives a 20% roll-off half Nyquist shaping. The basic
schematic of the quadrature demodulator followed by the
half Nyquist filter is shown in Fig.4. The signs of the
multiplication factors in the Q-branch can be inverted
(I2C-bus bit INVD).

When using an 8-bit ADC the LSB of the 9-bit input word
should be connected to the positive supply (V

DDD

).
This ensures a symmetrical 2’s complement
representation which can be multiplied by −1 in a correct
(2’s complement) way. The overall transfer function of the
square root raised cosine filters is shown in Figs 5 and 6.

For characteristics see Chapter 10.

handbook, full pagewidth

9

COMPLEMENT

BINARY OR

TWO's

I2C-BUS

+1, 0, −1, 0
0, −1, 0, +1

I2C-BUS

DIN8

to

DIN0

Fig.4 Schematic diagram of the quadrature demodulator and half Nyquist filter.

1996 Nov 19 9

9

I

9

Q

2

I

C-BUS

HALF NYQUIST

FILTER

HALF NYQUIST

FILTER

2

C-BUS

I

MGG168

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

5
0

−5

relative

gain
(dB)

−15

−25

−35

−45

−55

010.25 0.5 0.75 1.751.51.25
relative frequency

Fig.5 Half Nyquist receiver filter transfer function (20% roll-off).

MBG987

f )

(

2

r

s

handbook, full pagewidth

0

relative

gain
(dB)

−10

−20

−30

−40

−50

0 0.5 1 1.50.25 0.75 1.25 1.75

Fig.6 Half Nyquist receiver filter transfer function (15% roll-off).

relative frequency

MGG169

f )

(

2

r

s

1996 Nov 19 10

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

7.1.2 EQUALIZER
This function is realized with a T spaced 12 or 14 taps

(selected via the I2C-bus) adaptive filter with a feedback
part. The equaliser is based on a Decision Feedback
Equalizer (DFE) structure with Least Mean Square (LMS)
coefficient updating algorithm. No training sequence is
required. The block schematic of the total equalizer is
shown in Fig.8. The main tap of the equalizer is adjustable
for fine AGC function (6 dB AGC range). The settings of
the equalizer taps can be read via the I2C-bus. If the

2

equalizer diverges, an alarm bit is set (I

C-bus bit ALEQ)
and an automatic reset of the taps can be performed
(I2C-bus bit EAR).

To improve acquisition time, the convergence steps of the
FFE/DFE parts of the equalizer are programmable via the
I2C-bus. When the system locks, the steps are
automatically modified for optimum performances.

Besides reading the equalizer tap values, the main tap of
the equalizer can also be programmed. After setting the
main tap, the other coefficients can be set to zero.
The equalizer settings can also be frozen via the I2C-bus.

The equalizer has been proven to work correctly under bad
channel conditions as indicated in Table 1. It is guaranteed
that all loops (including equalizer) converge at a SNR of
21 dB for a 64-QAM modulation format and 27 dB for a
256-QAM modulation format.

Table 1 Channel echo profile

DELAY AMPLITUDE PHASE

3

⁄8× T

1

1

2 × T

5

4

7

6

⁄8× T

⁄8× T
⁄8× T

sym

sym

sym

sym
sym

0.08 130°

0.20 60°

0.05 310°

0.10 200°

0.03 200°

Figure 7 represents the QAM spectrum seen by the
equalizer. It corresponds (in the frequency domain) to the
multiplication of a full nyquist spectrum by the impulse
response of the channel specified in Table 1.

handbook, full pagewidth

1

relative

gain
(dB)

−1

−3

−5

−7

−9

−11

−0.5 0.5

−0.375 0.375−0.125 0.125−0.25 0.250

Fig.7 QAM spectrum with echo profile as seen by the equalizer.

relative frequency

MGD636

f )

(

r

s

1996 Nov 19 11

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

input

FEED

FORWARD

EQUALIZER

TAPS CALCULATION

−

Fig.8 DFE equalizer structure.

7.1.3 LOCK DETECTOR
The lock detector indicates whether all algorithms in the

demodulator are converged or not. For a symbol error rate
(at the input of the demodulator) smaller than 2 × 10−2, the
detector will give the indication ‘LOCK’ (I2C-bus bit
LK = 1). For larger symbol error rates, the detector will
generate the ‘UNLOCK’ signal (I2C-bus bit LK = 0).
It should ne noted that this ‘UNLOCK’ signal is generated
before any other part of the demodulator loses lock.
The lock detector is part of the carrier recovery loop, see
Fig.9. The Lock Detector Threshold (LDT) can be changed

2

with the help of the I

C-bus. The estimation algorithm used
in the lock detector also provides information about the
SER ratio which can be read out via the I2C-bus interface.

For characteristics see Chapter 11.

7.1.4 C

ARRIER RECOVERY

The carrier recovery detector consists of a
Phase-Frequency Detector (PFD) and Phase Detector
(PD). Depending on the mode of operation, the carrier
recovery is switched either between the phase frequency
(no lock) or the phase detector (lock). The carrier recovery
consists of the following two loops:

DECISION

FEEDBACK

EQUALIZER

TAPS CALCULATION

decision

+

MGG170

output

1. The outer loop; this loop controls the phase and
frequency of the incoming QAM signal at the IF
frequency in such a way that the constellation is
optimally positioned for detection.

2. The inner loop; the bandwidth of this loop can be large
and can therefore reduce the influence of large
bandwidth phase noise.

A fully digital carrier recovery function is also possible and
can be selected via the I

2

C-bus. Should this configuration
be used, then the external components of the loop filter will
not have to be implemented.

Four different maximum DAC output currents can be
selected via the I2C-bus. The output currents of the DAC
are defined in such a way that a VCO with a behaviour as
shown in Fig.9 can be connected directly to the output of
the integrated operational amplifier. Should the VCO slope
be negative then the sign of the current can be inverted by
the I2C-bus. Figure 10 defines the DAC output currents.

For characteristics see Chapter 12.

1996 Nov 19 12

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

IF

QAM

VCO

LPF

ADC

external

DAC

I

CAR

V

I2C-BUS

DEMODULATION

AND

FILTERING

I2C-BUS

ref

DIGITAL

INNER LOOP

r

EQUALIZER

I

s

ref1

lock

LOCK

PHASE

FREQUENCY

DETECTOR

PHASE

DETECTOR

lock

Fig.9 Schematic diagram of the carrier recovery.

I2C-BUS

I2C-BUS

0

2

I

C-BUS

MGG171

1996 Nov 19 13

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

CARI = 1

I

= positive output current.

pos

I

= negative output current.

neg

I

–()

posIneg

I

=

------------------------------ -

O

∆ I

-------------------------------- -

O

2

I

+()

posIneg

–()

I

posIneg

I

CAR

DAC output

current

f

VCO

CARI = 0

1

/

I

CAR

2

V

CARREC

MGG180

−1/

−I

I

2

CAR

digital input

CAR

100×=

Fig.10 Definition of the DAC currents and the expected frequency behaviour of the VCO.

1996 Nov 19 14

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

7.1.5 CLOCK RECOVERY
The clock recovery function uses the unequalized I and Q

signals, i.e. the half Nyquist filter outputs (see Fig.4).
The clock recovery section generates a control value each
symbol period. As this algorithm is based on the energy
maximization, both main and mid symbols are required at
the input. Consequently, the input data rate is twice the
symbol rate. The schematic diagram of this detector is
illustrated in Fig.11.

handbook, full pagewidth

I

Q

external

CLOCK

RECOVERY

DETECTOR

DAC

rsI

The clock generator generates the required internal clocks
from the VCXO clock signal at 4 × r

. The input stage

s

amplifier of this generator enables the designer to supply
a low amplitude oscillator signal to the TDA8046. The DAC
output current range (I

) can be varied via the I2C-bus.

CLK

The sign of the output current can also be inverted to
adjust for the correct sign of the VCXO slope.

For characteristics see Chapter 13.

to

VCXO

ref3

I

CLK

V

ref

4r

s

2r

s

r

s

2
4

Fig.11 Schematic diagram of the clock recovery.

from

VCXO

MGG172

1996 Nov 19 15

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

CLKI = 1

I

= positive output current; I

pos

I

= negative output current; −I

neg

I

–()

oCLK

posIneg

=

------------------------------ -

I

posIneg

-------------------------------- ­I

2

posIneg

I

oCLK

∆ I

CLK

+()

100×=

–()

CLK

I

CLK

DAC output

current

f

VCXO

CLKI = 0

1

/

I

CLK

2

digital input

1

−

/

I

CLK

2

−I

CLK

V

CLKREC

MGG181

.

.

Fig.12 The definition of the DAC currents and the expected frequency behaviour of the VCXO for clock recovery.

1996 Nov 19 16

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

2

C-bus data on address 08 is a factor 16 smaller than

7.1.6 AGC
The AGC estimates the mean power based on the digital

input signal and relates this to a peak value for a given
constellation. To avoid overloading of the ADC, this
estimation of the peak signals is used to control the AGC
loop. The implemented AGC covers a range of ±20 dB in
gain variance. A schematic diagram of the AGC is
illustrated in Fig.13.

If the SAW filter does not have sufficient adjacent channel
attenuation, the AGC threshold can be varied to avoid
clipping of the ADC. To do this, the threshold is made

2

programmable via the I

C-bus (byte ATH). Table 2 shows
that for each mode, a new ATH value (on address 08)
must be set with the help of the I2C-bus.

Table 2 AGC threshold values

MODE ATH (AGC THRESHOLD) I

256, 64, 16 and 4-QAM 2040 7F
32-QAM 1442 5A

The I
the used AGC threshold ATH.

The DAC output current range can be varied via the
I2C-bus interface (bits AGCA and AGCB) and the sign of
the current can be inverted (bit AGCI). The definition of the
DAC currents and the expected frequency behaviour of
the AGC is illustrated in Fig.14.

For characteristics see Chapter 14.

2

C-BUS DATA FOR ADDRESS 08

handbook, full pagewidth

2

C-BUS

I

DIN8
DIN0

I

BIAS

external

to

AGC

DETECTOR

I2C-BUS

BIAS

GENERATOR

I

r

s

ref2

DAC

I

ref2

I

AGC

to AGC

amplifier

V

ref

ADC

I2C-BUS

MGG173

Fig.13 AGC schematic diagram.

1996 Nov 19 17

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

AGCI = 1

I

= positive output current; I

pos

I

= negative output current; −I

neg

I

–()

oAGC

posIneg

=

------------------------------ -

I

posIneg

-------------------------------- ­I

posIneg

2

I

oAGC

∆ I

CLK

+()

100×=

–()

1

CLK

DAC output

I

AGC

current

gain

AGCI = 0

/

I

AGC

14

digital input

1

−

/

I

ACG

14

−I

AGC

V

AGC

MGG182

.

.

Fig.14 Definition of the DAC currents and the expected frequency behaviour of the AGC.

1996 Nov 19 18

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

7.1.7 OFFSET CONTROL
To compensate offsets in the I and Q branch, due to

spurious signals at the symbol frequency at the ADC input,
an offset compensation loop is included. This loop forces
the constellation to be symmetrically distributed over its
four quadrants. This function can be switched off by
I2C-bus bit OFFS.

7.1.8 L

OOP AMPLIFIERS

Analog switches are integrated to discharge the loop filter
capacitors or for test purposes on application boards (a
reference voltage equal to the half of the positive supply
voltage V

is available at the output of the amplifier

DDA

when the switches are closed). The I2C-bus bit ANAS
controls the three switches simultaneously. A schematic
diagram of the loop amplifier and analog switch is
illustrated in Fig.15.

For characteristics see Chapter 15.

andbook, halfpage

external

7.1.9 OUTPUT FORMATTER
The output formatter transforms the detected symbols into

bits in accordance with the selected mapping. The
TDA8046 has four possible mapping formats which can be
selected via the I2C-bus interface. The demapping
procedure and the corresponding bits are defined in
Fig.16. After demapping the bits are allocated to the
output. This output allocation corresponds to one of the
selected demapping schemes.

By using the I2C-bus, it is possible to obtain the following
output formats:

• 8 bits parallel

• semi-serial

• I and Q 8 bits multiplexed.

The implemented demapping formats and output bit
allocation are illustrated in Figs 17 to 30.

7.1.10 B

OUNDARY SCAN

The TDA8046H offers the possibility of boundary scan
test. The IEEE Standard Test Access Port and Boundary
Scan Architecture allows board manufacturers to test
board interconnections by using the boundary scan
functions.

I2C-BUS

DAC

V

ref

MGG174

Fig.15 Loop amplifier and analog switch.

Complete information on boundary scan test is available in

“Application note AN96048”

.

1996 Nov 19 19

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

8

I

Q

I2C-BUS

8

DEMAPPING

SCHEMES

1 to 4

MUX

Fig.16 Schematic diagram of the output formatter.

7.1.10.1 Demapping scheme 1; differential decoding

handbook, full pagewidth

Q

010100011100001100000100

A quadrant

PARALLEL

AND

SEMI-SERIAL

b5 b4

DO7 to DO0
CLKSCV

DO1 to DO0
CLKSCV
CLKOUT

DO7 to DO0
CLKSCV
CLKOUT

MGG175

b3 b2 b1 b0

100100101100111100110100

010101011101001101000101

010111011111001111000111

010110011110001110000110

010010011010001010000010

010011011011001011000011

010001011001001001000001

010000011000001000000000

Bit allocation for 256-QAM: b5, b4, b3, b2, b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

Fig.17 Demapping scheme 1; bit allocation: 256-QAM.

1996 Nov 19 20

100101101101111101110101

100111101111111111110111

100110101110111110110110

100010101010111010110010

100011101011111011110011

100001101001111001110001

100000101000111000110000

MGG193

I

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

b5

handbook, full pagewidth

B quadrant

Q

A quadrant

b4 b3 b2

1 0 0 01 0 0 11 0 1 11 0 1 0

1 1 0 01 1 0 11 1 1 11 1 1 0

0 1 0 00 1 0 10 1 1 10 1 1 0

0 0 0 00 0 0 10 0 1 10 0 1 0

0 0 0 00 1 0 01 1 0 01 0 0 0

0 0 0 10 1 0 11 1 0 11 0 0 1

0 0 1 10 1 1 11 1 1 11 0 1 1

0 0 1 00 1 1 01 1 1 01 0 1 0

D quadrantC quadrant

Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Bit allocation for 64-QAM: b5, b4, b3 and b2; b0 = b1 = 0; b7 and b6 differentially decoded (see Table 3).

Fig.18 Demapping scheme 1; bit allocation: 4-QAM and 64-QAM.

1 0 1 01 1 1 00 1 1 00 0 1 0

1 0 1 11 1 1 10 1 1 10 0 1 1

1 0 0 11 1 0 10 1 0 10 0 0 1

1 0 0 01 1 0 00 1 0 00 0 0 0

0 0 1 00 0 1 10 0 0 10 0 0 0

0 1 1 00 1 1 10 1 0 10 1 0 0

1 1 1 01 1 1 11 1 0 11 1 0 0

1 0 1 01 0 1 11 0 0 11 0 0 0

I

MGG183

Q

handbook, full pagewidth

Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Bit allocation for 32-QAM: not implemented.

B quadrant

1 01 1

0 00 1

0 01 0

0 11 1

A quadrant

D quadrantC quadrant

b5

1 10 1

1 00 0

0 10 0

1 11 0

Fig.19 Demapping scheme 1; bit allocation: 16-QAM and 32-QAM.

1996 Nov 19 21

b4

I

MGG184

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

7.1.10.2 Demapping scheme 2; direct translation

handbook, full pagewidth

0 1 0 0

0 0 1 1

0 0 1 0

0 0 0 1

0 0 0 0

Bit allocation for 256-QAM: b7, b6, b5, b4, b3, b2, b1, b0.

0 1 0 1

0 1 1 0

Q

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

b6b7 b5 b4

1 1 1 1

1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0

0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0

b3
b2
b1
b0

I

MGG195

Fig.20 Demapping scheme 2; bit allocation: 256-QAM.

1996 Nov 19 22

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

Bit allocation for 64-QAM: b7, b6, b5, b3, b2, b1; b4 = b0 = 0.
Bit allocation for 32-QAM: not implemented.

Q

0 1 10 1 00 0 10 0 0 1 1 11 1 01 0 11 0 0

b7 b6 b5

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

MGG185

b3
b2
b1

I

Fig.21 Demapping scheme 2; bit allocation: 64-QAM and 32-QAM.

1 1

1 0

0 1

0 0

b7 b6

b3
b2

I

MGG186

handbook, full pagewidth

Q

0 1

b7

b3

1

Q

0 10 0 1 11 0

I

0

a. Bit allocation for 4-QAM: b7 and b3; b6 = b5 = b4 = b2 = b1 = b0 = 0. b. Bit allocation for 16-QAM: b7, b6, b3 and b2; b5 = b4 = b1 = b0 = 0.

Fig.22 Demapping scheme 2; bit allocation: 4-QAM and 16-QAM.

1996 Nov 19 23

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

7.1.10.3 Demapping scheme 3; differential decoding: Draft prETS 429: 1994

b5 b4

andbook, full pagewidth

Q

A quadrant

b3 b2 b1 b0

100100100101100001100000

100110100111100011100010

101110101111101011101010

101100101101101001101000

001100001101001001001000

001110001111001011001010

000110000111000011000010

000100000101000001000000

Bit allocation for 256-QAM: b5, b4, b3, b2, b1, b0; b7 and b6 differentially decoded (see Table 3).

Fig.23 Demapping scheme 3; bit allocation: 256-QAM.

110000110001110101110100

110010110011110111110110

111010111011111111111110

111000111001111101111100

011000011001011101011100

011010011011011111011110

010010010011010111010110

010000010001010101010100

MGG194

I

1996 Nov 19 24

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

b4 b3 b2

handbook, full pagewidth

B quadrant

Q

A quadrant

b5

0 1 0 00 1 1 01 1 1 01 1 0 0

0 1 0 10 1 1 11 1 1 11 1 0 1

0 0 0 10 0 1 11 0 1 11 0 0 1

0 0 0 00 0 1 01 0 1 01 0 0 0

0 0 0 00 0 0 10 1 0 10 1 0 0

0 0 1 00 0 1 10 1 1 10 1 1 0

1 0 1 01 0 1 11 1 1 11 1 1 0

1 0 0 01 0 0 11 1 0 11 1 0 0

D quadrantC quadrant

Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Bit allocation for 64-QAM: b5, b4, b3 and b2; b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

Fig.24 Demapping scheme 3; bit allocation: 4-QAM and 64-QAM.

1 1 0 01 1 0 11 0 0 11 0 0 0

1 1 1 01 1 1 11 0 1 11 0 1 0

0 1 1 00 1 1 10 0 1 10 0 1 0

0 1 0 00 1 0 10 0 0 10 0 0 0

1 0 0 01 0 1 00 0 1 00 0 0 0

1 0 0 11 0 1 10 0 1 10 0 0 1

1 1 0 11 1 1 10 1 1 10 1 0 1

1 1 0 01 1 1 00 1 1 00 1 0 0

I

MGG187

handbook, full pagewidth

Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

B quadrant

Q

A quadrant

0 11 1

0 01 0

0 00 1

1 01 1

D quadrantC quadrant

b5

1 11 0

0 10 0

1 00 0

1 10 1

Fig.25 Demapping scheme 3; bit allocation: 16-QAM.

1996 Nov 19 25

b4

I

MGG188

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

Bit allocation for 32-QAM: b5, b4 and b3; b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

B quadrant

Q

0 1 11 1 1

0 0 1 1 0 10 1 0

0 0 01 0 01 1 0

0 0 00 0 10 1 1

1 0 01 0 11 1 1

1 1 00 1 0

A quadrant

0 1 01 1 0

1 1 10 1 1

D quadrantC quadrant

Fig.26 Demapping scheme 3; bit allocation: 32-QAM.

7.1.10.4 Demapping scheme 4; direct translation: HP8782B/K03

b4 b3

b5

1 1 11 0 11 0 0

0 1 10 0 10 0 0

1 1 01 0 00 0 0

0 1 01 0 10 0 1

I

MGG189

handbook, full pagewidth

1 1 1 0

1 1 1 1

Bit allocation for 256-QAM: b7, b6, b5, b4, b3, b2, b1, b0.

1 1 0 1

Fig.27 Demapping scheme 4; bit allocation: 256-QAM.

1 1 0 0

1 0 1 1

1 0 1 0

1 0 0 1

Q

1 0 0 0

0 1 1 1

0 1 1 0

0 1 0 1

0 1 0 0

0 0 1 1

0 0 1 0

0 0 0 1

b2b3 b1 b0

0 0 0 0

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1

1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

b4
b5
b6
b7

I

MGG196

1996 Nov 19 26

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

Bit allocation for 64-QAM: b7, b6, b5, b4, b3 and b2; b1 = b0 = 0.

Fig.28 Demapping scheme 4; bit allocation: 64-QAM.

Q

1 0 01 0 11 1 01 1 1 0 0 00 0 10 1 00 1 1

b2 b3 b4

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

MGG190

b5
b6
b7

I

handbook, full pagewidth

Bit allocation for 32-QAM: b7, b6, b5, b4 and b3; b2 = b1 = b0 = 0.

B quadrant

Q

0 1 0 1 10 1 1 1 1

0 1 0 0 10 1 1 0 10 1 1 1 0

0 1 0 0 00 1 1 0 00 1 0 1 0

1 1 0 0 01 1 0 0 11 1 0 1 1

1 1 1 0 01 1 1 0 11 1 1 1 1

1 1 0 1 01 1 1 1 0

Fig.29 Demapping scheme 4; bit allocation: 32-QAM.

1996 Nov 19 27

A quadrant

0 0 1 1 00 0 0 1 0

1 0 1 1 11 0 0 1 1

D quadrantC quadrant

b7

0 0 1 1 10 0 1 0 10 0 1 0 0

0 0 0 1 10 0 0 0 10 0 0 0 0

1 0 0 1 01 0 1 0 01 0 0 0 0

1 0 1 1 01 0 1 0 11 0 0 0 1

b6 b5 b4 b3

I

MGG191

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

0 0

0 1

1 0

1 1

b4 b5

b6
b7

I

MGG192

handbook, full pagewidth

b6

Q

1 0

a. Bit allocation for 4-QAM: b7 and b6; b5 = b4 = b3 = b2 = b1 = b0 = 0. b. Bit allocation for 16-QAM: b7, b6, b5 and b4; b3 = b2 = b1 = b0 = 0.

b7

0

I

1

Q

1 01 1 0 00 1

Fig.30 Demapping scheme 4; bit allocation: 4-QAM and 16-QAM.

Table 3 Definition of two MSB’s in modulation schemes 1 and 3

QUADRANT OF

CURRENTLY

RECEIVED SYMBOL

QUADRANT OF

PREVIOUSLY

RECEIVED SYMBOL

PHASE

CHANGE

(DEGREES)

CURRENT OUTPUT BITS

SCHEME 1 SCHEME 3

b7 b6 b7 b6

A A 0 0000
A B 270 1001
A C 180 1111
A D 90 0110
B A 90 0110
B B 0 0000
B C 270 1001

B D 180 1111
C A 180 1111
C B 90 0110
C C 0 0000
C D 270 1001
D A 270 1001
D B 180 1111
D C 90 0110
D D 0 0000

Tables 4 and 5 give the output format of the data for semi-serial mode operations.

1996 Nov 19 28

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

Table 4 Semi-serial format 256, 64 and 32-QAM; see note 1

SLOT

256-QAM 64-QAM 32-QAM

DO1 DO0 CLKSDV DO1 DO0 CLKSDV DO1 DO0 CLKSDV

0S
1S
2S
3S
4S
5S
6S
7S

(7) S

n-1

(5) S

n-1

(3) S

n-1

(1) S

n-1

(7) Sn(6) 1 Sn(5) Sn(4) 1 S

n

(5) Sn(4) 1 Sn(3) Sn(2)1S

n

(3) Sn(2) 1 Sn(1) Sn(0)1S

n

(1) Sn(0) 1 X X 0 X X 0

n

(6) 1 S

n-1

(4) 1 S

n-1

(2) 1 S

n-1

(0) 1 X X 0 X X 0

n-1

(5) S

n-1

(3) S

n-1

(1) S

n-1

(4) 1 S

n-1

(2) 1 S

n-1

(0) 1 X X 0

n-1

(4) S

n-1

(2) S

n-1

(0) Sn(4) 1

n-1

(3) Sn(2) 1

n

(1) Sn(0) 1

n

(3) 1

n-1

(1) 1

n-1

Note

1. The semi-serial format is only valid for demapping schemes 1, 3 and 4.

Table 5 Semi-serial format 16-QAM and 4-QAM; see note 1

16-QAM 4-QAM

SLOT

DO1 DO0 CLKSDV DO1 DO0 CLKSDV

0S
1S

(3) S

n-1

(1) S

n-1

(2) 1 S

n-1

(0) 1 X X 0

n-1

(1) S

n-1

(0) 1

n-1

2XX 0 XX 0
3XX 0 XX 0
4S
5S

(3) Sn(2) 1 Sn(1) Sn(0) 1

n

(1) Sn(0) 1 X X 0

n

6XX 0 XX 0
7XX 0 XX 0

Note

1. The semi-serial format is only valid for demapping schemes 1, 3 and 4.

1996 Nov 19 29

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

7.1.11 I2C-BUS INTERFACE
The TDA8046 is controlled by an I2C-bus. For programming, there is one module address (7 bits) and the R/W bit for

selecting READ or WRITE mode. It should be noted that the TDA8046 starts up in accordance with to the settings defined
in Tables 7, 8 and 9.

Table 6 Slave address

A6 A5 A4 A3 A2 A1 A0 R/

000111A0X

Table 7 WRITE (R/

FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0

DAC current
inversion/general

Demodulator 01 INP RLF OUTB OUTA INVD CONC CONB CONA
DAC/OFFS/switch 02 ANAS OFFS AGCB AGCA CLKB CLKA CARB CARA
Digital test/output

formatter
Digital loop filter

B.W.
Digital loop filter

B.W.
Lock detector

threshold
Lock detector

window size
AGC detector

threshold
Equalizer mode 09 −−EAR FFEL EDFE EFFE EFC PRESET
Equalizer tap FFEI 0A FFEI07 FFEI06 FFEI05 FFEI04 FFEI03 FFEI02 FFEI01 FFEI00
Equalizer steps 0B − FSTP2 FSTP1 FSTP0 − DSTP2 DSTP1 DSTP0

W=0)

00 AGCI CLKI CARI OUTE DEM NYQ DPHR RST

03 −− − −OUTF TSEL2 TSEL1 TSEL0

04 DCA7 DCA6 DCA5 DCA4 DCA3 DCA2 DCA1 DCA0

05 FSOL −−−−DCB2 DCB1 DCB0

06 LDT7 LDT6 LDT5 LDT4 LDT3 LDT2 LDT1 LDT0

07 −− − −− −WS1 WS0

08 ATH7 ATH6 ATH5 ATH4 ATH3 ATH2 ATH1 ATH0

W

1996 Nov 19 30

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

Table 8 Default settings after reset

FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0

DAC current inversion/
general

Demodulator 01 1 1 0 0 0 0 1 1
DAC/OFFS/switch 02 0 1 0 1 0 1 0 1
Digital test/output

formatter
Digital loop filter B.W. 04 0 1 0 0 0 0 0 0
Digital loop filter B.W. 05 1 −−−−100
Lock detector

threshold
Lock detector window

size
AGC detector

threshold
Equalizer mode 09 −−010000
Equalizer tap FFEI 0A 0 1 0 0 0 0 0 0
Equalizer steps 0B − 000−000

0001011100

03 −−−−0000

0600011000

07 −−−−−−00

0801111111

Table 9 READ (R/

W=1)

FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0

V

CARREC

V

CLKREC

V

AGC

Alarm equalizer/

(4 bits) 00 −−−−CR03 CR02 CR01 CR00

(4 bits) 01 −−−−CL03 CL02 CL01 CL00

(4 bits) 02 −−−−AG03 AG02 AG01 AG00

03 −−−ALEQ −−−LK

lock detector
SER estimation 04 LE7 LE6 LE5 LE4 LE3 LE2 LE1 LE0
FFEI3 05 b7 b6 b5 b4 b3 b2 b1 b0

.... ... b7 b6 b5 b4 b3 b2 b1 b0

FFEI0 08 b7 b6 b5 b4 b3 b2 b1 b0
DFEI1 09 b7 b6 b5 b4 b3 b2 b1 b0

.... ... b7 b6 b5 b4 b3 b2 b1 b0

DFEI7 0F b7 b6 b5 b4 b3 b2 b1 b0
DFEI8 10 b7 b6 b5 b4 b3 b2 b1 b0
FFEQ3 11 b7 b6 b5 b4 b3 b2 b1 b0

.... ... b7 b6 b5 b4 b3 b2 b1 b0

FFEQ0 14 b7 b6 b5 b4 b3 b2 b1 b0
DFEQ1 15 b7 b6 b5 b4 b3 b2 b1 b0

.... ... b7 b6 b5 b4 b3 b2 b1 b0

DFEQ8 1C b7 b6 b5 b4 b3 b2 b1 b0
FFEI5 1D b7 b6 b5 b4 b3 b2 b1 b0
FFEQ5 1E b7 b6 b5 b4 b3 b2 b1 b0

1996 Nov 19 31

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0

FFEI4 1F b7 b6 b5 b4 b3 b2 b1 b0
FFEQ4 20 b7 b6 b5 b4 b3 b2 b1 b0
IF_frequency_shift 21 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0
IF_frequency_shift 22 −−−−FS11 FS10 FS9 FS8

7.1.12 I2C-BUS WRITE PARAMETERS

Table 10 I2C-bus write parameters; 1-bit values

PARAMETER BIT VALUE DESCRIPTION

Input format INP 0 2’s complement

1 straight binary

Inversion demodulator INVD 0 Q-branch = 0 − 1, 0, +1

1 Q-branch = 0 + 1, 0, −1

Demodulator DEM 0 by-pass mode

1 normal mode

Half Nyquist filter NYQ 0 filter in by-pass mode

1 half Nyquist filter on

Roll-off factor RLF 0 15% roll-off

1 20% roll-off

Digital phase rotator DPHR 0 off: pass through mode

1on

General reset RST 0 normal operation

1 reset (with automatic return to normal operation)

Offset OFFS 0 off

1on

Outer loop activation
(carrier recovery)

Analog switches ANAS 0 open

1st and 2nd-order loop
(inner loop)

DAC current inversion CARI 0 no inversion

OUTE 0 outer loop inactive

1 outer loop active

1 closed

FSOL 0 1st-order loop

1 2nd-order loop

1 inversion

CLKI 0 no inversion

1 inversion

AGCI 0 no inversion

1 inversion

1996 Nov 19 32

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

PARAMETER BIT VALUE DESCRIPTION

Equalizer PRESET 0 normal operation

1 coefficient to zero (main tap to 1)

EDFE 0 normal operation

1 freeze coefficients of DFE part

EFFE 0 normal operation

1 freeze coefficients of FFE part

EFC
[fine AGC (equalizer
freeze centre tap)]

EAR 0 automatic reset switched OFF

FFEL 0 5 taps in FFE part

0 normal operation
1 freeze centre tap, no fine AGC

1 automatic reset switched ON

1 3 taps in FFE part

Table 11 I2C write parameters; 2-bit values

PARAMETER BITS DESCRIPTION

Window size (lock detector) WS1 WS0

0 0 256 symbols
0 1 512 symbols
1 0 1024symbols
1 1 2048symbols

Output format OUTB OUTA

0 0 scheme 1
0 1 scheme 2
1 0 scheme 3
1 1 scheme 4

DAC carrier recovery
(maximum current)

DAC clock recovery
(maximum current)

DAC AGC
(maximum current)

CARB CARA

0050µA
0 1 100 µA
1 0 150 µA
1 1 200 µA

CLKB CLKA

0050µA
0 1 100 µA
1 0 150 µA
1 1 200 µA

AGCB AGCA

0050µA
0 1 100 µA
1 0 150 µA
1 1 200 µA

1996 Nov 19 33

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

Table 12 I2C-bus write parameters; 3-bit values

PARAMETER

BITS

CONC CONB CONA

Constellation 0 0 0 4-QAM

0 0 1 16-QAM
0 1 0 32-QAM
0 1 1 64-QAM
1 0 0 256-QAM

Table 13 Convergence step for the equalizer (DFE and FFE parts)

DSTP2 FSTP2 DSTP1 FSTP1 DSTP0 FSTP0

CONVERGENCE STEP

000 2
001 2
010 2
011 2
100 2
101 2
110 2
111 2

(LOCK = 0)

-13

-13

-13

-12

-12

-12

-12

-11

DESCRIPTION

CONVERGENCE STEP

(LOCK = 1)

-15

2

-14

2

-13

2

-15

2

-14

2

-13

2

-12

2

-15

2

2

Table 14 I

C-bus write parameters; 4-bit values

BITS

PARAMETER

OUTF TSEL2 TSEL1 TSEL0

Output format 0 0 0 0 8 bits in parallel

0 1 1 1 I/Q 8 bits multiplexed (equalizer output)
1 x x x semi-serial

Special test
modes

0 x 0 1 DO7 to DO4 = carrier recovery DAC input;

DO3 to DO0 = AGC DAC input

0 x 1 0 DO7 to DO6 = fine AGC;

DO5 to DO0 = clock recovery DAC input

0 0 1 1 DO7 to DO0 = I and Q equal input

(I/Q 8 bits multiplexed format)

0 1 1 1 DO7 to DO0 = I and Q equal output

(I/Q 8 bits multiplexed format)

DESCRIPTION

1996 Nov 19 34

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

7.1.13 I2C-BUS READ PARAMETERS

Table 15 I2C-bus read parameter; 1-bit values

PARAMETER BIT VALUE DESCRIPTION

Lock detect LK 0 no lock

1 lock

Alarm equalizer ALEQ 0 normal operation (alarm off)

1 divergence detected (alarm on)

Table 16 I

2

C-bus read parameter; ADC carrier recovery; 4-bit value

PARAMETER BITS DESCRIPTION

ADC carrier
recovery

CR03 CR02 CR01 CR00

b3 b2 b1 b0 carrier recovery: V

CARREC

= 0.25 +1⁄16V

(8b3 + 4b2 + 2b1 + b0) V

2

Table 17 I

C-bus read parameter; ADC clock recovery; 4-bit value

PARAMETER BITS DESCRIPTION

ADC clock
recovery

CL03 CL02 CL01 CL00

b3 b2 b1 b0 clock recovery: V

CLKREC

= 0.25 +1⁄16V

DDD

(8b3 + 4b2 + 2b1 + b0) V

2

Table 18 I

C-bus read parameter; ADC AGC; 4-bit value

PARAMETER BITS DESCRIPTION

ADC AGC AG03 AG02 AG01 AG00

Table 19 I

b3 b2 b1 b0 AGC: V

2

C-bus read parameter; 8-bit value

= 0.25 +1⁄16V

AGC

(8b3 + 4b2 + 2b1 + b0) V

DDD

PARAMETER BITS DESCRIPTION

SER

(1)

LE7 LE6 LE5 LE4 LE3 LE2 LE1 LE0

b7 b6 b5 b4 b3 b2 b1 b0 SER = f (b7 to b0)

DDD

Note

1. The bits LE7 to LE0 give the number of symbols falling inside the lock detector active areas. The count is made during
an observation period (256 to 2048 symbols).
To obtain more details about the SER estimation, refer to

2

Table 20 I

C-bus read parameter; 12-bit value

“Application Note AN96048”

.

PARAMETER BITS DESCRIPTION

IF_FREQ_SHIFT

(1)

FS11 to FS0 frequency shift = f (FS11 to FS0)

Note

1. The bits FS11 to FS0 indicate the remaining frequency shift of the QAM spectrum (IF spectrum). This data is useful

2

if the TDA8046H does not use the outer loop of carrier recovery (bit ‘OUTE’ of the I
To obtain more details about the frequency shift calculation, refer to the

“Application Note AN96048”

C-bus table set to 0).

.

1996 Nov 19 35

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

V

max

P

tot

T

stg

T

amb

9 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

10 DEMODULATOR AND HALF NYQUIST FILTER CHARACTERISTICS

digital supply voltage −0.3 6.0 V
maximum voltage on all pins 0 V
total power dissipation T

=70°C − 1.4 W

amb

DDD

V

storage temperature −55 +150 °C
operating ambient temperature 0 70 °C

thermal resistance from junction to ambient in free air 50 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

α roll-off − 15 or 20 − %

pass-band ripple − 0.05 − dB
stop-band ripple see Figs 5 and 6

ISI

power

power inter-symbol interference (15% roll-off filter) note 1 −−43 − dB
power inter-symbol interference (20% roll-off filter) note 1 −−44 − dB

Note

1. Definition of the power inter-symbol interference:

N

1–()2⁄

ISI

power

Where N

conv

2C

×

∑

=

dB()10 log

is the number of coefficients C

conv

k1=

--------------------------------------------------------------------­C

conv

(0)

conv

2

(4k)

conv

2

. C

(k) represent the coefficient resulting from the convolution of

conv

the transmission and reception filters (K indicates the Kth coefficient).
The power ISI specified in Table 1 has been calculated on a filter resulting from the convolution of the TDA8046 filters

and a truncated half-Nyquist filter with 57 T/4 taps for the 15% roll-off filter and 41 T/4 taps for the 20% roll-of filter
(see “

Application note AN96048”

- Appendix B).

1996 Nov 19 36

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

11 LOCK DETECTOR CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SNR

lock

signal-to-noise ratio to lock the
demodulator

12 CARRIER RECOVERY CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Carrier recovery detector

ARRIER RECOVERY: BIAS CURRENT FOR DACS SET TO 37.5 µA

C
K

d

∆f

CAR

f

n(inner)

f

n(outer)

I

zero

I

CAR

detector constant SNR = 21 dB for

frequency range ±0.017rs−−MHz
loop bandwidth of inner loop rs= 5 Msym/s 10 −−kHz
loop bandwidth of outer loop −− 0.3f
zero current of DAC −100 − +100 nA
maximum DAC output current

(programmable)

f

DAC

DAC sampling rate − r
CARRIER RECOVERY DAC OUTPUT CURRENTS DURING LOCK
I

oCARlock

∆I

oCARlock

mean output current −

matching of output currents −2.5 − +2.5 %
CARRIER RECOVERY DAC OUTPUT CURRENTS DURING UNLOCK
I

oCARunlock

∆I

oCARunlock

mean output current − I

matching of output currents −2.5 − +2.5 %

4-QAM 8 −−dB
16-QAM 15 −−dB
32-QAM 18 −−dB
64-QAM 21 −−dB
256-QAM 27 −−dB

− 3I

CAR

−µA/rad

64-QAM constellation
SNR = 27 dB for

− 6.05I

−µA/rad

CAR

256-QAM constellation

n(inner)

kHz

50 − 200 µA

s

1

CAR

⁄2I

CAR

− MHz

−µA

−µA

1996 Nov 19 37

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

13 CLOCK RECOVERY CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clock recovery detector

C

LOCK RECOVERY: BIAS CURRENT FOR DACS SET TO 37.5 µA

K

d

∆f

CLK

f

n

I

CLK(max)

detector constant SNR = 21 dB for

frequency range 100 −−ppm

natural frequency − 400 − Hz

maximum DAC output current

(programmable)
f

DAC

LOCK RECOVERY DAC output currents

C
I

oCLKlock

∆I

oCLKlock

DAC sample rate − r

mean output current − I

matching of output currents −2.5 − +2.5 %

64-QAM constellation;
SNR = 27 dB for
256-QAM constellation

− 0.24I

−µA/rad

CLK

50 − 200 µA

s

CLK

− MHz

−µA

14 AGC CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

AGC detector

DETECTOR: BIAS CURRENT FOR DACS SET TO 37.5 µA

AGC
∆R

AGC

I

zero

I

AGC(max)

AGC range of detector ±20 −−dB

zero current −100 − +100 nA

maximum DAC output current

50 − 200 µA

(programmable)
f

DAC

DAC sample rate − r

s

− MHz
AGC DAC output currents
I

oAGC

∆I

oAGC

mean output current in lock −

unlock − I

matching of output current −5+5%

1

AGC

⁄14I

AGC

−µA

−µA

1996 Nov 19 38

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

15 INTEGRATED LOOP AMPLIFIERS CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Integrated loop amplifiers

LOOP AMPLIFIERS
G

OL

G

B

V

ref

V

o

R

L(VSSD)

R

L(VDDD)

ANALOG SWITCHES
Z

SW

open loop gain − 60 − dB
gain bandwidth product − 1 − MHz
reference voltage − 2.5 − V
output voltage 0.1V

− 0.9V

DDA

DDA

V
load to ground 5 −−kΩ
load to supply 6.5 −−kΩ

switch impedance closed − 5 − kΩ

open 10 −−MΩ

16 CHARACTERISTICS OF DIGITAL INPUTS AND OUTPUTS

V

DDD=VDDA

=5V; V

DDD(core)

= 3.3 V; T

=25°C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clock outputs: CLKADC and CLKSDV

V

OL

V

OH

T

CLK

t

w

t

r

t

f

R

L

LOW level output voltage 0 − 0.1V
HIGH level output voltage 0.9V

DDD

− V

DDD

DDD

cycle time 35 −−ns
pulse width 40 : 60 duty cycle 14 −−ns
rise time CL=30pF −−6ns
fall time CL=30pF −−6ns
load resistance 1 −−kΩ

Clock input: CLK

V
T
t

w

R

i(rms)
CLK

source

input voltage level (RMS value) sine wave 100 −−mV
cycle time 35 −−ns
pulse width 40 : 60 duty cycle 14 −−ns
source resistance −−50 Ω

Digital inputs: DIN8 to DIN0

V

IL

V

IH

t

SU

t

HD

C

L

LOW level input voltage −−0.8 V
High level input voltage 2.0 −−V
set-up time 15 −−ns
hold time 0 −−ns
load capacitance −−10 pF

V
V

1996 Nov 19 39

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital outputs: DO1 to DO0 with respect to CLKOUT for semi-serial mode

V

OL

V

OH

t

od

t

oHD

C

L

LOW level output voltage 0 − 0.1V
HIGH level output voltage 0.9V

DDD

output delay time −−7ns
output hold time −−10 ns
load capacitance additional 2 − 30 pF

Digital outputs: DO7 to DO0 with respect to CLKSDV for 8-bit parallel mode

V
V
t

od

t

oHD

C

OL
OH

L

LOW level output voltage 0 − 0.1V
HIGH level output voltage 0.9V

DDD

output delay time −−22 ns
output hold time −−22 ns
load capacitance additional 2 − 30 pF

Digital outputs: DO7 to DO0 with respect to CLKOUT for I/Q multiplexed mode

V
V
t

od

t

oHD

OL
OH

LOW level output voltage 0 − 0.1V
HIGH level output voltage 0.9V

DDD

output delay time −−22 ns
output hold time −−22 ns

Loop amplifier

V

o

G

v

G

B

R

L

output voltage level 0.1V

DDA

DC voltage gain (open loop) − 60 − dB
gain bandwidth product 1 −−MHz
load resistance 5 −−KΩ

− V

− V

− V

DDD

DDD

DDD

− 0.9V

DDD

DDD

DDD

DDA

V
V

V
V

V
V

1996 Nov 19 40

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

BER

no convergence

measured

−4

10

theory

MBG989

implementation

loss

SNR (dB)

Fig.31 Definition of the Implementation Loss.

handbook, full pagewidth

CLKADC

DIN 0 to

DIN 8

t

t

r

90% 90%

10% 10%

t

w

SU; DAT

t

HD; DAT

Fig.32 CMOS input data timing diagram.

1996 Nov 19 41

t

t

f

CLK

V

V

V

V

MGG176

OH

OL

IH

IL

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

CLKOUT

DO1 to DO0

CLKSDV

T

sym

t

oHD

t

od

Fig.33 CMOS semi-serial mode timing diagram.

V

OH

V

OL

V

OH

slot 3slot 2slot 1slot 0

V

OL

V

OH

V

MGG179

OL

handbook, full pagewidth

CLKSDV

DATA

OUTPUT

t

oHD

Fig.34 CMOS 8-bit symbol in parallel mode timing diagram

1996 Nov 19 42

T

sym

V

OH

V

OL

V

OH

V

t

od

OL

MGG177

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

handbook, full pagewidth

DO7 to DO0

CLKOUT

CLKSDV

T

sym

t

oHD

t

od

IQ

Fig.35 CMOS I and Q multiplexed timing diagram.

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

MGG178

1996 Nov 19 43

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

17 PACKAGE OUTLINE

QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

51 33

52

pin 1 index

64

1

32

Z

e

w M

b

p

20

19

A

E

A

H

E

E

2

A

A

1

detail X

Q

L

p

L

SOT319-2

(A )

3

θ

w M

b

e

p

Z

D

D

H

D

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.20

0.25

0.05

2.90

2.65

0.25

UNIT A1A2A3b

cE

p

0.50

0.25

0.35

0.14

(1)

(1) (1)(1)

D

20.1

19.9

eH

14.1

13.9

24.2

1

23.6

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT319-2

1996 Nov 19 44

v M

A

B

v M

B

H

D

LLpQZywv θ

E

18.2

17.6

1.0

0.6

1.4

1.2

0.2 0.10.21.95

EUROPEAN

PROJECTION

Z

D

1.2

1.2

0.8

0.8

ISSUE DATE

E

o

7

o

0

92-11-17
95-02-04

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

18 SOLDERING

18.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

18.2 Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

18.3 Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

18.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Nov 19 45

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

19 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

20 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

21 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1996 Nov 19 46

Philips Semiconductors Product specification

Multi-mode QAM demodulator TDA8046

NOTES

1996 Nov 19 47

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

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Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

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Indonesia: see Singapore
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20124 MILANO, Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

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Metro MANILA, Tel. [phone], Fax. [phone]

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Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]

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Slovenia: see Italy
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Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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Printed in The Netherlands 537021/1200/02/pp48 Date of release: 1996 Nov 19 Document order number: 9397 750 01499