Datasheet TDA8006H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8006

Multiprotocol IC Card coupler

Product specification
File under Integrated Circuits, IC02

1998 Jul 31

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

FEATURES

• 80C52 core with 16-kbyte ROM and 256-byte RAM

• Extra 1-kbyte RAM outside the core for data storage

• Control and communication through a standard RS232

full duplex interface or a parallel interface

• Specific ISO 7816 UART with parallel access on I/O for
automatic convention processing, variable baud rate
through frequency or division ratio programming, error
management at character level for T = 0, extra guard
time register

generation (5 V ±5% or 3 V ±5%, 65 mA maximum

• V

CC

with controlled rise and fall times)

• Cards clock generation (up to 10 MHz) with two times
synchronous frequency doubling

• Cards clock STOP HIGH, clock STOP LOW or

1.25 MHz (from internal oscillator) for cards power-down
mode

• CLKOUT output for clocking external devices with f

1

⁄2f

xtal

or1⁄4f

possibility

xtal

xtal

• Automatic activation and deactivation sequence through
an independent sequencer

• Supports the asynchronous protocols T = 0 and T = 1 in
accordance with ISO 7816 and Europay, Mastercard,
Visa (EMV)

• Supports synchronous cards

• Current limitations in case of short-circuit

• Special circuitry for killing spikes during power-on or off

• Supply supervisor for power-on/off reset

• Step-up converter (supply voltage from 4.2 to 6 V)

• Power-down and sleep mode for low power

consumption

• Enhanced ESD protections on card side
(6 kV minimum)

• Software library for easy integration within the
application.

APPLICATIONS

• Smart card readers for multiprotocol applications (EMV
banking, digital pay TV, access control, etc.).

GENERAL DESCRIPTION

The TDA8006 is controlled through a standard serial
interface or a parallel bus, it takes care of all ISO 7816,
EMV and GSM11.11 requirements. It gives the card and
the set a very high level of security, due to its special
hardware against ESD, short-circuiting, power failure, etc.
Its integrated step-up converter allows operation within a
supply voltage range of 4.2 to 6 V.

A special version where the internal connections to the
controller are fed outside through pins allows easy
development and evaluation, together with a 80CL580
microcontroller or development tool (emulation board
available).

A software library has been developed, taking care of all

,

actions required for T = 0, T = 1 and synchronous
protocols. This library may be either linked with the
application software before masking, or masked in the
internal ROM (see

“Application Note AN97080”

).

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8006H QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

TDA8006AH QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);

body 10 × 10 × 1.75 mm

1998 Jul 31 2

SOT319-2

SOT307-2

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

I

DD(pd)

I

DD(sm)

V

CC

I

CC

SR slew rate (rise and fall) maximum load capacitor pin V

t

de

t

act

f

xtal

f

oper

T

amb

supply voltage 4.2 − 6V
supply current in power-down mode VDD= 5 V; card inactive; note 1 −−250 µA
supply current in sleep mode card powered but clock stopped;

−−1500 µA

note 1

card supply voltage including static loads (5 V card) 4.75 5.0 5.25 V

with 40 nAs dynamic loads on

4.6 − 5.4 V

100 nF capacitor (5 V card)
including static loads (3 V card) 2.80 − 3.20 V
with 24 nAs dynamic loads on

2.75 − 3.25 V

100 nF capacitor (3 V card)

card supply current operating −−65 mA

overload detection − 80 − mA

0.10 0.16 0.22 V/µs

CC

400 nF (including typical 100 nF

decoupling)
deactivation cycle duration −−100 µs
activation cycle duration −−225 µs
crystal frequency 4 − 25 MHz
operating frequency external frequency applied on

0 − 25 MHz

pin XTAL1
operating ambient temperature −25 − +85 °C

Note

1. I

in all configurations include the current at pins VDD, V

DD

DDA

and V

DDRAM

.

1998 Jul 31 3

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

BLOCK DIAGRAM

handbook, full pagewidth

P00 to P07

P20 to P27

P11/T2EX

ALARM
CDELAY

RESET

PSEN

ALE

EA

P36/WR

P37/RD

P30/RXD

P31/TXD

P33/INT1

P10/T2

TDA8006H

(TDA8006AH)

45 (32)
44 (31)

52 (34)
7 (3)
8 (4)
11 (7)
61 (41)
62 (42)
19 to 12

(1)

(11 to 8)

63, 64, 1 to 6
(43, 44, 1, 2)

58 (38)
59 (39)
60 (40)
53 (35)
54 (36)

(2)

INT0

V

DD

100 nF

GND S1 S2

SUPPLY

AND

SUPERVISOR

CONTROLLER

C52
16-kbyte ROM
256-byte RAM

6

8

PERIPHERALS

P34

P35

P40
to P47

V

DDA

100 nF

AGND

29 (19)41(28) 40 (27)

31

(21)

STEP-UP

CONVERTER

C4

C8

ANALOG

DRIVERS

SEQUENCER

INTERNAL

OSCILLATOR

AND

30
(20)

28 (18)

(22) 32

(25) 38

(26) 39

(17) 27

(16) 26

(23) 36

(24) 37

(29) 42

VUP

100 nF

C4

C8

CLK

RST

V

CC

I/O

PRES

V

DDRAM

GNDRAM

CLKOUT

Minimum value for capacitor between V
Pin numbers in parenthesis represent the TDA8006AH.
(1) Ports P04 to P07 not applicable for QFP44 package.
(2) Ports P24 to P27 not applicable for QFP44 package.
(3) Ports K0 to K3 not applicable for QFP44 package.

23 (14)
24 (15)

43 (30)

1024
AUX
RAM

CLOCK CIRCUITRY PORT EXTENSION

10 (6)
XTAL1

and AGND is 2.2 µF.

DDA

T = 0,1

ISO

UART

9 (5)
XTAL2

Fig.1 Block diagram.

1998 Jul 31 4

I/O
OFF
3 V/5 V

CMDVCC

K0 to K3

48 to 51

(3)

MGR225

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

PINNING

SYMBOL

DESCRIPTION

QFP64 QFP44

P22 1 1 address 10/general purpose I/O port
P23 2 2 address 11/general purpose I/O port
P24 3 − address 12/general purpose I/O port
P25 4 − address 13/general purpose I/O port
P26 5 − address 14/general purpose I/O port
P27 6 − address 15/general purpose I/O port
PSEN 7 3 program store enable output
ALE 8 4 address latch enable
XTAL2 9 5 crystal connection
XTAL1 10 6 crystal connection or external clock input
EA 11 7 external access
P07 12 − address/data 7/general purpose I/O port
P06 13 − address/data 6/general purpose I/O port
P05 14 − address/data 5/general purpose I/O port
P04 15 − address/data 4/general purpose I/O port
P03 16 8 address/data 3/general purpose I/O port
P02 17 9 address/data 2/general purpose I/O port
P01 18 10 address/data 1/general purpose I/O port
P00 19 11 address/data 0/general purpose I/O port
n.c. 20 12 not connected
n.c. 21 13 not connected
n.c. 22 − not connected

PIN

V

DDRAM

23 14 supply voltage for the auxiliary RAM
GNDRAM 24 15 ground for the auxiliary RAM
n.c. 25 − not connected
RST 26 16 card reset output (ISO C2 contact)
CLK 27 17 clock output to the card (ISO C3 contact)
AGND 28 18 ground for the analog part
S1 29 19 contact 1 for the step-up converter (a ceramic capacitor of 100 nF must be

connected between S1 and S2)

V

DDA

30 20 analog supply voltage for the voltage doubler
S2 31 21 contact 2 for the step-up converter (a ceramic capacitor of 100 nF must be

connected between S1 and S2)

VUP 32 22 output of the step-up converter; must be decoupled with a 100 nF ceramic

capacitor
n.c. 33 − not connected
n.c. 34 − not connected
n.c. 35 − not connected
V

CC

36 23 card supply output voltage (ISO C1 contact)

1998 Jul 31 5

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

SYMBOL

I/O 37 24 data line to/from the card (ISO C7 contact)
C4 38 25 auxiliary I/O for ISO C4 contact (synchronous cards for instance)
C8 39 26 auxiliary I/O for ISO C8 contact (synchronous cards for instance)
GND 40 27 ground
V

DD

PRES 42 29 card presence contact input (active HIGH or LOW by mask option); see Table 12
CLKOUT 43 30 output for clocking external devices
CDELAY 44 31 external capacitor connection for delayed reset signal
ALARM 45 32 open drain reset output (active HIGH or LOW by mask option); see Table 12
TEST 46 33 test pin (must be left open-circuit in the application)
INHIB 47 − test pin (must be left open-circuit in the application)
K0 48 − output port from port extension (±2 mA push-pull)
K1 49 − output port from port extension (±2 mA push-pull)
K2 50 − output port from port extension (±2 mA push-pull)
K3 51 − output port from port extension (±2 mA push-pull)
RESET 52 34 input for resetting the microcontroller (active HIGH)
P10/T2 53 35 general purpose I/O port (connected to P10)
P11/T2EX 54 36 general purpose I/O port (connected to P11)
n.c. 55 37 not connected
n.c. 56 − not connected
n.c. 57 − not connected
P30/RXD 58 38 general purpose I/O port or serial interface receive line
P31/TXD 59 39 general purpose I/O port or serial interface transmit line

INT1 60 40 general purpose I/O port or interrupt (connected to P33)

P33/
P36/

WR 61 41 general purpose I/O port or external data memory write strobe
RD 62 42 general purpose I/O port or external data memory read strobe

P37/
P20 63 43 address 8/general purpose I/O port
P21 64 44 address 9/general purpose I/O port

QFP64 QFP44

PIN

DESCRIPTION

41 28 supply voltage

1998 Jul 31 6

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

handbook, full pagewidth

P22
P23
P24
P25
P26
P27

PSEN

ALE
XTAL2
XTAL1

EA
P07
P06
P05
P04
P03
P02
P01
P00

P21

64
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19

P20

63

P37/RD
62

61

P36/WR

P33/INT1
60

P30/RXD

P31/TXD
59

58

TDA8006H

n.c.
57

n.c.
56

n.c.
55

P11/T2EX

P10/T2

54

53

RESET
52

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

K3
K2
K1
K0
INHIB
TEST
ALARM
CDELAY
CLKOUT
PRES

V

DD

GND
C8
C4
I/O

V

CC

n.c.
n.c.
n.c.

20

21

22

23

24

25

n.c.

n.c.

n.c.

DDRAM

V

n.c.

GNDRAM

Fig.2 Pin configuration (QFP64).

1998 Jul 31 7

26

RST

27

CLK

28

AGND

29
S1

30

DDA

V

31
S2

32

VUP

MGR226

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

handbook, full pagewidth

P20

P37/RD

P36/WR

P33/INT1

P31/TXD

P30/RXD

P11/T2EX

P10/T2

P21

44

n.c.

43

42

41

40

39

38

37

RESET

36

35

34

P22
P23

PSEN

ALE
XTAL2
XTAL1

EA
P03
P02
P01
P00

22

VUP

33

TEST
ALARM

32
31

CDELAY

30

CLKOUT
PRES

29

V

28

GND

27

C8

26

C4

25
24

I/O
V

23

MGR227

DD

CC

1
2
3
4
5
6
7
8

9
10
11

12

13

n.c.

n.c.

TDA8006AH

14

15

DDRAM

V

GNDRAM

16

RST

17

CLK

18

AGND

19
S1

20

DDA

V

21
S2

Fig.3 Pin configuration (QFP44).

1998 Jul 31 8

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

FUNCTIONAL DESCRIPTION

It is assumed that the reader of this data sheet is familiar
with ISO 7816.

Microcontroller

The microcontroller is an 80C52 with 16 kbytes of ROM,
256 bytes of RAM, timers 0, 1, 2 and 5 I/O ports (port P0:
open-drain; ports P1 to P3: weak pull-up). Port P4 is as in
83CE560, except that precharge circuitries ensure fast
rising time also when leaving read mode (transition times
<0.5 µs). The ROM code content may be tested by
signature, thus avoiding read-out of the ROM code after
masking (for security bit option see Table 12). The CPU,
timers 0 and 1, serial UART, parallel I/O ports, 256-byte
RAM, 16-kbyte ROM and external bus are conventional
C51 family library elements. Timer 2 is a conventional
C52 element (interrupt enable bit ET2: bit 3 in register
IEN1 at byte address E8H and interrupt priority bit PT2:

Table 1 List of differences between TDA8006, CE560, CL580 and C52

FEATURES TDA8006 83CE560 CL580 INTEL C52

P4 address C0 C0 C1 no
Timer 2 Intel Philips Intel Intel
ROM size 16 kbytes 64 kbytes 6 kbytes 8 kbytes
External 0 interrupt

vector
External 0 interrupt

priority
Timer 0 interrupt vector 000BH 000BH 000BH 000BH
Timer 0 interrupt priority 2nd 2nd 4th 2nd
External 1 interrupt

vector
External 1 interrupt

priority
Timer 1 interrupt vector 001BH 001BH 001BH 001BH
Timer 1 interrupt priority 4th 4th 10th 4th
Serial 0 interrupt vector 0023H 0023H 0023H 0023H
Serial 0 interrupt priority 5th 5th 13th 5th
Timer 2 interrupt vector 004BH 0033H, etc. (8) 0033H 002BH
Timer 2 interrupt priority lowest (6th) miscellaneous 5th lowest (6th)

2

I

C no yes yes no
ADC no yes yes no
32 kHz oscillator no yes no no
PWM no yes yes no
Watchdog no yes yes no

0003H 0003H 0003H 0003H

highest (1st) highest (1st) highest (1st) highest (1st)

0013H 0013H 0013H 0013H

3th 3th 7th 3th

bit 3 in register IP1 at byte address F8H). Register PCON
contains an added feature: PCON.5 = RFI (reduced radio
frequency interference bit). When set to logic 1, the
toggling of pin ALE is prohibited. This pin is cleared on
RESET.

If an access to the external data memory via MOVX
instructions (see Table 1) is desired, bit PCON.6 = ARD
inside the PCON register must be set to logic 1.

Please refer for any further information to the published
specification of the 83CE560 in

80C51-Based 8-Bit Microcontrollers”

Ports P40 to P47,INT0, P12, P13, P14, P15, P16 and P17
are used internally for controlling the smart card interface
and the other peripherals. P34 and P35 are used to control
the auxiliary contacts C4 and C8.

The list of differences given in Table 1 may help to develop
the software on the dedicated emulation board for
TDA8006 or other device.

“Data Handbook IC20;

.

1998 Jul 31 9

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

FEATURES TDA8006 83CE560 CL580 INTEL C52

Interrupts on P1 no no yes no
Additional RAM 1-kbyte peripheral 2-kbyte MOVX no no
Wake-up from PDOWN reset,

Table 2 Bit addresses (special function registers)

INT0, INT1 reset, INT0,

INT1 + other

reset, INT2 to INT8 reset

REGISTER

IP1 −−−−PT2 −−− XXXX 0XXX

B 0000 0000

IEN1 −−−−ET2 −−− 0000 0000

ACC 0000 0000

PSW CY AC F0 RS1 RS0 OV F1 P 0000 0000

T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2N CP/RL2N 0000 0000

P4 1111 1111

IP0 −−−PS0 PT1 PX1 PT0 PX0 XXX0 0000

P3 1111 1111

IEN0 EA −−ES0 ET1 EX1 ET0 EX0 0XX0 0000

P2 1111 1111

S0CON SMO SM1 SM2 REN TB8 RB8 TI RI 0000 0000

P1 1111 1111

TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0000 0000

P0 1111 1111

BYTE

ADDRESS

F8H FFH FEH FDH FCH FBH FAH F9H F8H

F0H F7H F6H F5H F4H F3H F2H F1H F0H

E8H EFH EEH EDH ECH EBH EAH E9H E8H

E0H E7H E6H E5H E4H E3H E2H E1H E0H

D0H D7H D6H D5H D4H D3H D2H D1H D0H

C8H CFH CEH CDH CCH CBH CAH C9H C8H

C0H C7H C6H C5H C4H C3H C2H C1H C0H

B8H BFH BEH BDH BCH BBH BAH B9H B8H

B0H B7H B6H B5H B4H B3H B2H B1H B0H

A8H AFH AEH ADH ACH ABH AAH A9H A8H

A0H A7H A6H A5H A4H A3H A2H A1H A0H

98H 9FH 9EH 9DH 9CH 9BH 9AH 99H 98H

90H 97H 96H 95H 94H 93H 92H 91H 90H

88H 8FH 8EH 8DH 8CH 8BH 8AH 89H 88H

80H 87H 86H 85H 84H 83H 82H 81H 80H

(MSB) (LSB)

BIT ADDRESS

RESET
VALUE

1998 Jul 31 10

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

Table 3 Bit addresses (other registers)

REGISTER

BYTE

ADDRESS

RESET VALUE

SP 81H 0000 1111
DPL 82H 0000 0000
DPH 83H 0000 0000
PCON 87H 0000 0000
TMOD 89H 0000 0000
TL0 8AH 0000 0000
TL1 8BH 0000 0000
TH0 8CH 0000 0000
TH1 8DH 0000 0000
S0BUF 99H XXXX XXXX
RCAP2L CAH 0000 0000
RCAP2H CBH 0000 0000
TL2 CCH 0000 0000
TH2 CDH 0000 0000

Supply

The circuit operates within a supply voltage range of

4.2 to 6 V. The supply pins are VDD, V
V

and GNDRAM. Pins V

DDRAM

and AGND supply the

DDA

, GND, AGND,

DDA

analog drivers to the card and have to be externally
decoupled because of the large current spikes that the
card and the step-up converter can create. V

DDRAM

and
GNDRAM supply the auxiliary RAM and should be
decoupled separately. VDD and GND supply the rest of the
chip. An integrated spike killer ensures the contacts to the
card remain inactive during power-up or power-down.
An internal voltage reference is generated which is used
within the step-up converter, the voltage supervisor and
the V

generator.

CC

The voltage supervisor generates an alarm pulse, whose
length is defined by an external capacitor tied to the
CDELAY pin, when VDD is too low to ensure proper
operation (1 ms per 1 nF typical). This pulse is used as a
reset pulse by the controller, in parallel with an external
reset input, which can be tied to the system controller. It is
also used in order to either block any spurious on card
contacts during controllers reset or to force an automatic
deactivation of the contacts in the event of supply drop-out
(see Sections “Activation sequence” and “Deactivation
sequence”). It is also fed to an external open-drain output
(called ALARM) which can be chosen active HIGH or LOW
by mask option (see Table 12).

1998 Jul 31 11

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

handbook, full pagewidth

V

V

DD

CDELAY

ALARM

th(VDD)

V

th(CDELAY)

t

W

Fig.4 Voltage supervisor.

Step-up converter

Except for the VCC generator and the other card contacts
buffers, the whole circuit is powered by VDD, V
V

. If the supply voltage is 4.2 V, then a higher

DDRAM

DDA

and

voltage is needed for the ISO contacts supply. When a
card session is requested by the controller, the sequencer
first starts the step-up converter, which is a switched
capacitors type, clocked by an internal oscillator at a
frequency of approximately 2.5 MHz. The output voltage
VUP is regulated at approximately 6 V and then fed to the

generator. VCC and GND are used as a reference for

V

CC

all other cards contacts.

ISO 7816 security

The correct sequence during activation and deactivation of
the card is ensured through a specific sequencer, clocked
by a division ratio of the internal oscillator.

Activation (bit CMDVCC within the ports extension register
is HIGH) is only possible if the card is present (pin PRES
HIGH or LOW according to mask option) and if the supply
voltage is correct (ALARM signal inactive).

The presence of the card is signalled to the controller by
the OFF bit (within the status register, generating an
interrupt if enabled when toggling).

During a session, the sequencer performs an automatic
emergency deactivation in the event of card take-off,
supply voltage drop or short-circuit. The OFF bit goes
LOW, thereby warning the controller through the interrupt
line

INT0 and the status register.

MGR228

Peripheral interface (see Figs 5 and 6)
This block allows parallel communication with the four

peripherals (ISO 7816 UART, clock generator, on/off
sequencer and auxiliary RAM) through an 8-bit data bus,
6-bit address and control bus and one interrupt line to the
controller. The data bus consists of ports P40 (data 0) to
P47 (data 7). The address bus consists of ports AD0
(P12), AD1 (P13), AD2 (P14) and AD3 (P15). The control
lines are R/

W (P16) and EN (P17). The interrupt line is

INT0.
During a read operation, data is available on the bus when

EN is LOW and the controller may read them at this
moment. During a write operation, the data should be
present on the bus before assertingEN LOW, which writes
them in the registers. After resetting EN HIGH, the
controller must not omit to release the bus by setting P4
HIGH again (the transition times on port P4 are less than
500 ns).

The interrupt line is reset HIGH when reading out the
status register.

EAD OPERATION

R

• Set P4 to FFH

• Select the register with AD0, AD1, AD2, AD3

• Assert R/W HIGH

• Assert EN LOW; the data is available on data bus P4

• Read the data on P4

• Set EN HIGH: the bus is set to high impedance.

1998 Jul 31 12

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

WRITE OPERATION

• Select the correct register with AD0, AD1, AD2, AD3

• Assert R/W LOW

• Write the data on the data bus P4

• Assert EN LOW; the data is written in the register

• Set EN back HIGH

• Set P4 to FFH: the bus is back to high impedance.

handbook, full pagewidth

P4 XX FF FF FFDATA

R/W

AD0 to AD3 X AD AD

EN

read data cycle write data cycle

Fig.5 Use of peripheral interface.

Integrated precharges allow fast rising edges on P4 when
changing from read mode to write mode, thus avoiding to
trigger the active pull-ups on P4.

DATA

MGR229

1998 Jul 31 13

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1998 Jul 31 14

k, full pagewidth

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

8

P00/P07

P32/INT0

INT

SYNCHRONOUS IN REGISTER

SYNCHRONOUS OUT REGISTER

CONFIGURATION REGISTER

EN

R/W

TRANSMIT REGISTER

RECEIVE REGISTER

STATUS REGISTER

GUARD TIME REGISTER

ISO 7816 UART

8

P20/P27 ALE

P17

AD3

AD2

AD1

PSEN EA P37/RD P36/WR P33/INT1P30/RXD P31/TXD P10/T2 P11/T2EX

80C52 CORE

P15 P14 P13 P12P40 to P47P34 P35 P16 OSC

AD0

EN

R/W

AD3

AD2

AD1

PERIPHERAL EXTENSION REGISTER

ON/OFF SEQUENCER

AD0

UART

CLOCK

EN

CLOCK CONFIGURATION REGISTER

PROGRAMMABLE DIVIDER

CLOCK GENERATOR

CARD

CLOCK

R/W

AD3

EXTERNAL

CLOCK

8

AD2

AD1

MICRO CLOCK

AD0

XTAL

RESET

databus

control bus

R/W

AD3

AD2

AD1

AD0

LOW ADDRESS REGISTER
HIGH ADDRESS REGISTER
MEMORY READ REGISTER

MEMORY WRITE REGISTER

AUXILIARY RAM

EN

MGR230

I/O C4 C8 K0 K1

INTERFACE, SECURITY AND POWER CONTROL

K2 K3

CMDVCC

RST DET ERR POR CLK CLKOUT OSCINT XTAL1

Fig.6 Peripheral interface.

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

Register addresses
Table 4 Register addresses

AD3 AD2 AD1 AD0 R/

W REGISTER PERIPHERAL

00000CCR (Clock Configuration Register) clock generator
00010PDR (Program Divider Register)
00110SOR (Synchronization Out Register) ISO 7816 UART
00111SIR (Synchronization In Register)
01000UTR (UART Transmit Register)
01001URR (UART Receive Register)
01011USR (UART Status Register)
01010UCR (UART Configuration Register)
01100GTR (Guard Time Register)
01110PER (Ports Extension Register) on/off sequencer
1 1 0 X 0 MAR0 (Memory Address LOW) auxiliary RAM
1 1 1 X 0 MAR1 (Memory Address HIGH)
1 0 0 X 0 MWR (Memory Write Register)
1 0 0 X 1 MRR (Memory Read Register)

Clock circuitry

The clock to the microcontroller (OSC), the clock to the
card (CLK), the clock to the ISO 7816 UART and the clock
to the external world (CLKOUT) are derived from the main
clock signals (XTAL from 4 to 20 MHz, or an external clock
signal applied on XTAL1), or the internal oscillator (f

INT

Microcontroller clock (OSC): after power-on or reset, the
microcontroller is clocked with1⁄8f
may decide to clock it with1⁄2f

. Then, the application

INT

,1⁄2f

xtal

or f

xtal

INT

.
All frequency changes are synchronous, thereby ensuring
no hang-up due to short spikes etc.

Cards clock (CLK): the application may select to send the

1

⁄2f

,1⁄4f

,1⁄8f

card

xtal

xtal

xtal

or1⁄2f

(≈1.25 MHz), or to stop

INT

the clock HIGH or LOW. All transition are synchronous,
ensuring correct pulse length during start or change in
accordance with ISO 7816.

After power-on or reset, CLK is stopped at LOW.
External clock output (CLKOUT): CLKOUT is a permanent

clock output which may be used by the external world.
The following frequencies are possible: f

1

⁄4f

. All transitions are synchronous. After power-on or

xtal

reset, CLKOUT is fixed at1⁄4f

).

xtal

.

ISO 7816 UART clock: the clock to the ISO 7816 UART is
the same as the clock to the card.

Two items act on this clock in order to achieve the different
baud rates on I/O as defined by the F and D factors: a
prescaler by 31 or 32 and an auto-reload 8-bit
programmable counter.

All these configurations are controlled by the clock
configuration register and the programmable divider
register.

xtal

,1⁄2f

xtal

and

1998 Jul 31 15

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

Table 5 Clock Configuration Register (CCR; address 0; write-only; all bits cleared after reset)

D7 D6 D5 D4 D3 D2 D1 D0 UART PRESC CLK CLKOUT OSC

XXXXXXX0/31
XXXXXXX1/32
XXXX000X STOP LOW

1

XXXX001X
XXXX010X
XXXX011X
XXXX100X
XXXX101X STOP HIGH
XX00XXXX
XX01XXXX XTAL
XX10XXXX

00XXXXXX
01XXXXXX XTAL
10XXXXXX
11XXXXXX

⁄2XTAL

1

⁄4XTAL

1

⁄8XTAL

1

⁄2FINT

1

⁄4XTAL

1

⁄2XTAL

1

⁄8FINT

1

⁄2XTAL

1

⁄2FINT

Table 6 Programmable Divider Register (PDR; address 1; write-only; all bits cleared after reset)

D7 D6 D5 D4 D3 D2 D1 D0 DIVISION FACTOR

x7 x6 x5 x4 x3 x2 x1 x0 x7x6x5x4x3x2x1x0H

The hexadecimal value stored in the PDR is the auto-reload value of an 8-bit counter clocked by the cards clock; the
counter is loaded with this value and counts from this value till overflow; then it is reloaded with the same value and the
counter starts counting again. The output of the counter is then divided by 31 or 32 in accordance with the programmed
value of the prescaler (UART PRESC). The result is ISO 7816 UART CLK, used for shifting the data in or out on the I/O
line.

handbook, full pagewidth

CLK

8-BIT AUTO-RELOAD COUNTER

WITH PDR = F4

/31

ISO 7816

UART CLK

/32

MGR231

Fig.7 Baud rate selection on I/O.

The example shown in Fig.7 shows how to program a division factor of 372. With these registers, the baud rates given
in Table 7 are achievable according to ISO 7816 (31 or 32 depends on the choice for the prescaler, and the hexadecimal
value is the programmed value within the PDR).

1998 Jul 31 16

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

Table 7 Baud rates according to F and D and prescaler and programmable divider values

D

0001 31;F4 31;F4 31;EE 31;E8 31;DC 31;D0 31;C4 32;F0 32;E8 32;E0 32;D0 32;C0
0010 31;FA 31;FA 31;F7 31;F4 31;EE 31;E8 31;E2 32;F8 32;F4 32;F0 32;E8 32;E0
0011 31;FD 31;FD − 31;FA 31;F7 31;F4 31;F1 32;FC 32;FA 32;F8 32;F4 32;F0
0100 −−−31;FD − 31;FA − 32;FE 32;FD 32;FC 32;FA 32;F8
0101 −−−−−31;FD − 32;FF − 32;FE 32;FD 32;FC
0110 −−−−−−−−−32;FF − 32;FE
1000 31;FF 31;FF − 31;FE 31;FD 31;FC 31;FB − 32;FE − 32;FC −
1001 −−−−−−31;FD −−−−−

On/off controller (PER; address 7; write-only; all bits cleared after reset)
Table 8 Bits of on/off controller

BIT NAME DESCRIPTION

D0 CMDVCC; set and reset by software set to 1 for starting activation sequence of the card, and reset

D1 RSTIN; set and reset by software control line for card RST in manual mode (active HIGH)
D2 Force Inverse Parity (FIP); set and reset by

D3 automatic ATR processing enabling

D4
D5
D6
D7

0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101

to 0 for starting deactivation

when LOW, the UART processes the parity according to

software

(ATREN); set by software, reset by
hardware

K0; set and reset by software auxiliary ±2 mA push-pull output control (inverted output)
K1; set and reset by software auxiliary ±2 mA push-pull output control (inverted output)
K2; set and reset by software auxiliary ±2 mA push-pull output control (inverted output)
K3; set and reset by software auxiliary ±2 mA push-pull output control (inverted output)

ISO 7816; when HIGH, the UART processes the inverse parity
(which causes parity errors during transmission and ‘not
acknowledge’ signals during reception)

when HIGH, the UART counts automatically the clock pulses
during ATR and controls the RST contact; this bit is
automatically reset by hardware when a start bit is detected
on I/O or when the card is declared as mute; when LOW, this
automatic processing is disabled (manual mode)

F

The on/off controller is used for activating or deactivating
the card, for controlling the contact C2 (RST) manually
through RSTIN or automatically, for forcing inverse parity
(flow control or test purpose) and for controlling four
independent push-pull output lines K0 to K3.

After having cleared the ISO 7816 UART reset bit (see
UART configuration register) and checking the card
presence within the status register, the software may
initiate an activation sequence by setting bit CMDVCC
HIGH. It may also initiate a deactivation sequence by
resetting this bit (see activation and deactivation
sequences).

1998 Jul 31 17

The timings during the ATR may be either checked
manually (using RSTIN and t3/t5 for counting clock pulses)
or automatically by setting bit ATREN HIGH (see Section
“Activation sequence”). In this case, RST is controlled by
hardware and the count of CLK pulses is also done by
hardware. Bit ATREN is reset by hardware when a start bit
has been detected before 2 × 45000 CLK pulses, or when
the card is declared as ‘mute’. Setting this bit HIGH again
during a session will initiate a warm reset.

A warm reset may also be done manually by using RSTIN
and t3/t5 again.

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

ISO 7816 UART

The ISO 7816 UART handles all specific requirements
defined in ISO 7816 T = 0 and T = 1 protocol types. It is
also able to deal with synchronous cards (in conjunction
with C4 and C8). In addition, there is a possibility to force
parity errors for test purposes or flow control. The count of
CLK cycles during ATR is possible by hardware or by
software.

Table 9 UART Configuration Register (UCR; address 5; write-only; all bits cleared after reset)

BIT NAME DESCRIPTION

D0 Reset ISO 7816 UART (RIUN); set by

software, reset by software

D1 Start Session (SS); set by software, reset by

software

D2 Last Character to Transmit (LCT); set by

software, reset by hardware or software

D3 Transmit/Receive-N (TRN); set by software,

reset by software or hardware
D4 not used
D5 Protocol Selection (PS); set by software, reset

by software
D6 3 V/5 V-N (TFN); set by software, reset by

software
D7 Synchrone/asynchrone-N (SAN); set by

software, reset by software

The ISO 7816 UART is configurated with 2 registers:
UART Configuration Register (UCR) and Guard Time
Register (GTR).

When timings are given in terms of ETU (Elementary Time
Unit as defined by ISO 7816), then the reference is the
negative edge of the start bit of the character being
received or transmitted, unless otherwise specified.

when LOW, this bit resets the UART; must be set by software
before any use of the UART

when HIGH, this bit allows the detection of the convention
during the initial character of the card; must be reset by
software after correct reception of the first character and before
complete reception of the next character

when HIGH, this bit allows automatic toggling from
transmission to reception mode after successful transmission of
the last character; in this case, TRN is also reset by hardware

when LOW, the UAR T is in reception mode; when HIGH, it is in
transmission mode;

when LOW, the UAR T is in T = 0 mode; when HIGH, the UART
is in T = 1 mode

when LOW, the card supply voltage V
VCC=3V

when HIGH, this bit allows direct monitoring of I/O by bit D0 of
SIR or SOR; when LOW, I/O is fed to the ISO 7816 UART

INT falls down when TRN is set

CC

= 5 V; when HIGH,

RECEPTION
In order to start a session with the card bit RIUN (which

resets the ISO 7816 UART when LOW) must be set HIGH.
The UART recognizes the convention (direct or inverse)

on the characters received while bit SS (Start Session) is
HIGH. Then the UART automatically converts any
transmitted or received character according to this
convention, so the software only has to deal with
characters written in direct convention. Indeed, bit SS
must be reset by software after correct reception of the first
character of the ATR (TS) and before complete reception
of the next character.

Reception mode is selected when TRN is LOW. The bit
FSD is set within USR, and an interrupt is generated if
enabled at the start bit of the received character when SS
is HIGH, allowing the manual CLK count during ATR.

1998 Jul 31 18

The interrupt will be cleared on the rising edge of
during the status read operation.

For the next characters, bit RBF is set at 10.5 ETU and an
interrupt is generated if enabled for telling that a character
has been received, with or without parity error, and that
this character may be read within the reception register.
The interrupt is cleared on the falling edge ofEN during the
read operation of the received character.

In protocol type T = 0 (bit PS LOW), the I/O line is
automatically pulled LOW between 10.5 and 11.75 ETU if
a parity error has been detected in the character (parity
error handling at character level).

In protocol type T = 1 (bit PS HIGH), if a parity error is
detected, bit PE is set in the status register, but the I/O line
is not pulled LOW.

EN

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

handbook, full pagewidth

RIU

SS

CMDVCC

R/W

P4 FF FF FF FF FF

EN

I/O

INT

FSD

RBF

release reset

set start session

set CMDVCC

first start

read status

10.5 ETU

anything

int cleared

Fig.8 First character reception.

TRANSMISSION
Transmission mode is selected when TRN is HIGH.

If enabled, an interrupt is given on the rising edge of TRN,
telling that the transmission buffer is empty, and may be
written for transmitting a character. The interrupt is cleared
during the read status operation.

The character is written in the UTR on the falling edge
of EN during the write operation, and its transmission
starts on the rising edge of EN.

buffer full

read status

read character
and int cleared

reset start session

MGR232

The I/O line is read at 10.84 ETU for checking if the card
has detected a parity error or not. Bit TBE is set within the
USR at the same time, and an interrupt is given if enabled
to inform that the transmission buffer is empty, and that a
new character may be written.

If the parity is correct, then the transmission of the next
character will start at 12 ETU + GT +0.5 ETU after the
start bit of the previous character (see Section “Extra
guard time”).

1998 Jul 31 19

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

If the parity was not correct, then the transmission will start
at 13 ETU (the guard time GT must be programmed
before starting to transmit). This assumes that a character
has been written in the UTR.

It may be useful for some cards to change very fast from
transmission to reception mode; bit LCT may be used for
this purpose.

If LCT is set HIGH, then the UART automatically resets the
bits TRN and LCT at 10.85 ETU if no parity error has

handbook, full pagewidth

R/W

P4 FF FF FFFF

EN

TRN

LCT

occurred; the UART is ready to receive a character from
the card at 12 ETU (T = 0) or 11 ETU (T = 1) after the
previous start bit.

If a parity error has occurred during transmission of the last
character, then the UART remains in transmission mode
with LCT set, waiting for the software to rewrite the
corrupted character.

FF

TBE

INT

I/O

anything buffer empty

read status start transmit read status

int cleared

transmission

write character

Fig.9 Character transmission without or with LCT.

SYNCHRONOUS CARDS
If bit SAN (Synchronous/Asynchronous-N) is set, then the

software may deal with synchronous cards: the
information available on the I/O line is copied on bit data 0
of the data bus when the SIR or SOR registers are
selected, without entering the UART.

The synchronous clock may be controlled by selecting
STOP HIGH or STOP LOW on CLK. C4 and C8 may be

set LCT

int cleared

write character

anything buffer empty

start transmit

start receive

TRN/LCT reset

MGR233

controlled by P34 and P35 (operation depending on
synchronous card type).

Synchronous Input Register (SIR; address 3; read-only)

When this register is selected, then I/O is copied on data 0
(P40) and may be read by the controller.

1998 Jul 31 20

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

Synchronous Output Register (SOR; address 3; write-only)

When this register is selected, then data 0 (P40) is copied on I/O on the falling edge of EN.

handbook, full pagewidth

R/W

P4

P40

CLK

EN

I/O

FF FF

read write

Fig.10 Synchronous cards use.

EXTRA GUARD TIME

Table 10 Guard Time Register (GTR; address 6; write-only; all bits cleared after reset)

D7 D6 D5 D4 D3 D2 D1 D0 GUARD TIME T = 0 GUARD TIME T = 1

x7 x6 x5 x4 x3 x2 x1 x0 x7x6x5x4x3x2x1x0H x7x6x5x4x3x2x1x0H
111111110 −1

MGR234

Between the transmission of two characters to the card, the ISO 7816 UART automatically inserts a number of guard
ETUs equal to the value stored in the GTR (called GT). FFH has a special status: FFH means 0 ETU in protocol T0 and

−1 ETU in protocol T1 (which means reception and transmission possible at 11 ETU).

Reception and transmission register

UART Receive Register (URR; address 4; read-only; all bits cleared after reset)

D7 to D0 are the bits of the data received from the card. Due to the fact that the UART automatically converts the
characters according to the convention recognized during TS, all characters within the URR are in direct convention.

The received character is loaded in the URR 0.5 ETU after the shift of the parity, i.e. 10.5 ETU after the edge of the start
bit; this implies that the previous character must have been read by the controller before, otherwise it is overwritten.

1998 Jul 31 21

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

The UART checks the parity of the received characters; if
the parity is wrong, then bit PE is set within the status at
the same time than bit RBF (receive buffer full).

In protocol T = 0, I/O is pulled low between 10.5 and 11.75
ETU in case of error. Characters may be received from the
card every 12 ETU, even after a transmission (see LCT
use; Table 9). In protocol T = 1, the reception is possible at
11 ETU.

UART Transmit Register (UTR; address 4; write-only;
all bits cleared after reset)

Bits D7 to D0 are the bits of the data to be transmitted to
the card. Due to the automatic conversion performed by
the UART according to convention detected during TS, the
controller must write the characters to send to the card in
direct convention.

The character to send may be written in the UTR as soon
as bit TBE within the status register (transmit buffer empty)
is set.

Table 11 UART Status Register (USR; address 5; read-only; all bits cleared after reset except for D5)

BIT NAME DESCRIPTION

D0 TX Buffer Empty (TBE) this bit is set when the UART has finished transmitting the data written in

the UTR (at 10.8 ETU) or on the rising edge of TRN; it is reset on the rising
edge of

D1 RX Buffer Full (RBF) this bit is set when the UART has finished receiving a character from the card

(at 10.5 ETU); it is reset on the falling edge of
operation

D2 First Start Detect (FSD) this bit is set on the falling edge of the first start bit if SS = 1; it is reset on the

rising edge of

D3 Parity Error (PE) this bit is set when a parity error has been detected by the UART in

transmission or in reception mode, at the same time as TBE and RBF; it is
reset on the rising edge of

D4 Early Answer (EA) this bit is set if a start bit has been detected on I/O between the 200 and

the 400 first CLK pulses when the UART is configurated in automatic ATR
processing; it is reset on the rising edge of

D5 OFF this bit is set if the card is present and reset if the card is not present; if

CMDVCC is set HIGH, it may also be reset if a hardware problem causing an
emergency deactivation sequence has occurred

D6 Off Interrupt (OFFI) this bit is set when OFF state has changed; it is reset on the rising edge of EN

during a read status operation

D7 Mute Card (MC) this bit is set if a card has not answered after 90000 CLK pulses when the

ISO 7816 UART is configurated in automatic ATR processing; it is reset on
the rising edge of

EN during a read status operation

If the UCR writing occurs beyond 12.5 ETU + GT after the
previous start bit, then the transmission starts on the rising
edge ofEN during the write operation. If this occurs before,
then the UART will wait until 12.5 ETU + GT after the
previous start bit for starting the transmission.

In protocol T = 0, in case of parity error signalled by the
card, the previous character must be rewritten in UTR.
Then the UART will wait 13 ETU after the start bit of the
previous character before restarting the transmission.

S

TATUS REGISTER AND INTERRUPTS

The ISO 7816 UART reports its activity to the
microcontroller by means of the UART status register,
which acts upon the interrupt line INT.

EN during the read character

EN during a read status operation

EN during a read status operation

EN during a read status operation

EN during a read status operation

1998 Jul 31 22

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

All bits except for D5 generate an interrupt on INT (if
enabled) when they are set. D0, D2, D3, D4, D6 and D7
are cleared on the rising edge of EN after a read operation
of USR. D1 is cleared when the data in the reception buffer
has been read-out. D5 may be used to check the cards
presence and also to determine that reason of an
emergency deactivation during a cards session. In case of
Early Answer (EA) or Mute Card (MC) during automatic
ATR processing, the card is not automatically deactivated.
An interrupt is generated if enabled, and it is up to the
controller to deactivate or not.

Auxiliary RAM (MAR0, address C or D, write-only;
MAR1, address E or F, write-only; MRR, MWR,
address 8 or 9, read/write; all bits cleared after reset)

In order to store data, 1 kbytes of auxiliary RAM may be
accessed through the peripheral interface. The content of
the RAM is undefined after reset. It should be noted that
only AD3, AD2 and AD1 must be programmed for
addressing the RAM register, allowing faster operations if
needed.

There are two ways for addressing this memory:

• Random way: the low order address is written in MAR0,
and the high order address is written in MAR1. Then a
write operation to MWR will write the data at the
preselected address on the falling edge of

EN, and a
read operation to MRR will load on P4 the data that is
stored at the preselected address on the falling edge of
EN.

• Sequential way: once low order and high order
addresses are written in MAR0 and MAR1, every read
or write operation to MRR or MWR will increment the
address that is stored in MAR0 and MAR1. Thus it is
possible to read or write data strings within the auxiliary
RAM without rewriting the addresses between
2 databyte. The autoincrement feature is operational on
the whole length of the RAM. In case of overflow, the
count starts again at address 00H.

Activation sequence

When the card is inactive, pins V

, CLK, RST and I/O are

CC

LOW, with low impedance with respect to GND.
The step-up converter is stopped. The I/O is configured in
the reception mode with a high impedance path to the
ISO 7816 UART, subsequently no spurious pulse from the
card during power-up will be taken into account until I/O is
enabled. When requirements are fulfilled (voltage supply,
card present, no hardware problems), the microcontroller
may initiate an activation sequence by setting
bit CMDVCC HIGH (t

).

0

• The step-up converter is started (t1)

• VCC starts rising from 0 to 5 V or 3 V with a controlled
rise time of 0.16 V/µs typically (t2)

• I/O, C4 and C8 buffers are enabled (t3); integrated

pull-up resistors of 10 kΩ are connected to V

CC

• CLK is sent to the card (t4)

• RST buffer is enabled (t5).

In order to allow a precise count of clock pulses during
ATR in manual mode, a defined time window (t3/t5) is
opened where the clock may be sent to the card by means
of RSTIN. Beyond this window, RSTIN does not respond
on a clock pulse, and only monitors the cards RST contact.

In automatic mode (ATREN set HIGH), RST is monitored
by the TDA8006, RSTIN has no action and CLK is sent by
the TDA8006 at t3. RST is LOW until 45000 CLK pulses, if
the card has not started to answer before, and is then set
HIGH for again a maximum of 45000 CLK pulses.

It is also possible to make customized activation sequence
by keeping CLK STOP LOW with RSTIN LOW beyond t5,
and then apply CLK by means of CLK configuration.

The sequencer is clocked by1⁄64f

which leads to a time

INT

interval T of 25 µs typical. Thus t1=0to1⁄64T, t2=t1+T,
t3=t1+ 4T, t4=t3to t5 and t5=t1+ 7T.

Output Ports Extension Register (PER, address 7,
write-only; all bits cleared after reset)

Within this register, the four low order bits are used for
controlling the activation of the card. The four high order
bits D4, D5, D6 and D7 control auxiliary ±2 mA push-pull
output ports, which can be used for any purpose (LEDs,
control signals, etc.). The electrical state of the ports is
HIGH if the bit is LOW, and LOW if the bit is HIGH. The bits
are cleared after reset, so the ports are HIGH.

1998 Jul 31 23

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

handbook, full pagewidth

CMDVCC

VUP

V

CC

I/O

RSTIN

CLK

RST

handbook, full pagewidth

CMDVCC

ATREN

VUP

V

CC

I/O

CLK

RST

t0t

t

1

2

t

t

3

4

t5 (= t

act

)

ATR

MGR235

Fig.11 Manual activation sequence using t3/t5.

t0t

t

1

2

t

3

t5 (= t

Fig.12 Automatic activation sequence.

1998 Jul 31 24

act

)

ATR45000CLK

MGR236

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

Deactivation sequence

When the session is completed, the microcontroller sets
CMDVCC LOW (t10). The circuit then executes an
automatic deactivation sequence:

• Card reset (RST goes LOW) (t11)

• Clock is stopped (t12)

• I/O becomes high impedance to the ISO 7816

UART (t13)

• VCC falls to 0 V with typical 0.16 V/µs slew rate (t14)

• The step-up converter is stopped and CLK, RST, V

CC

and I/O become low impedance to GND (t15).

handbook, full pagewidth

CMDVCC

RST

CLK

t

11=t10

+1⁄64T, t12=t11+1⁄2T, t13=t11+T,

t14=t11+3⁄2T, t15=t11+ 5T.
tde is the time that VCC needs for going down to less than

0.3 V.

I/O

V

CC

VUP

t

t

10

t

11

12

t

13

t

de

Fig.13 Deactivation sequence.

Protections

Main hardware fault conditions are monitored by the
circuit:

• Overcurrent on V

CC

• Short-circuits between VCC and other contacts

• Card take-off during transaction.

When one of these problems is detected, the security logic
block sets the OFF bit LOW, which generates an interrupt
in order to warn the microcontroller, and initiates an
automatic deactivation of the contacts.

t

14

t

15

MGR237

When the deactivation has been completed and CMDVCC
has been set LOW, the OFF bit returns HIGH, except if the
problem was due to a card extraction in which case it
remains LOW until a card is inserted.

1998 Jul 31 25

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

handbook, full pagewidth

CMDVCC

OFF

RST

CLK

I/O

V

CC

MGR238

Fig.14 Emergency deactivation sequence after VCC short-circuited to ground.

Auxiliary contacts C4 and C8

The auxiliary contacts C4 and C8 are controlled with
P34 and P35 through two identical pseudo-bidirectional
I/O lines.

In the Idle state P34 is pulled HIGH to VDD through an
integrated resistor of 20 kΩ and C4 is pulled HIGH to V

CC

through an integrated resistor of 10 kΩ. This allows
operation with a VCC value of 3 V and a VDD value of 5 V.
The first side on which a falling edge occurs becomes the
master. An anti-latch circuitry disables the detection of
falling edge on the other side, which becomes the slave.

After a delay of approximately 200 ns (t

), the N transistor

d

on the slave side is turned on, thus transmitting the ‘0’
present on the master side. When the master side goes
back to logic 1, the P transistor on the slave side is turned
on during td, and then both sides return to their idle states.

The maximum frequency on the I/O lines is 1 MHz.

1998 Jul 31 26

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

V

DDD

V

n1

V

n2

I

n1

I

n3

I

n6

I

n7

P

tot

T

stg

T

j

V

esd

analog supply voltage −0.5 +6.5 V
digital supply voltage −0.5 +6.5 V
all input voltages except S1, S2 and VUP −0.5 VDD+ 0.5 V
voltage on pins S1, S2 and VUP −0.5 +7.5 V
DC current into XT AL1, XTAL2, P30/RXD,

−5+5mA
P31/TXD, RESET, P33/INT1, P36/WR,
P37/RD, P00 to P07, P20 to P27, P10/T2,
P1 1/T2EX, EA, ALE, PSEN, CDELAY,
PRES, INHIB, CLKOUT and TEST

DC current from or to pins S1,

−200 +200 mA
S2 and VUP

DC current from or to K0 to K3 −5+5mA
DC current from or into pin ALARM

see Table 12 −5+5mA

(according to option choice)
total power dissipation T

= −20 to +85 °C

amb

QFP44 − 400 mW

QFP64 − 500 mW
storage temperature −55 +150 °C
junction temperature − 140 °C
electrostatic discharge on pins I/O, V

CC

−6+6kV
RST, CLK, C4, C8
and PRES

on other pins −2+2kV

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air

QFP64 51 K/W
QFP44 64 K/W

1998 Jul 31 27

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

CHARACTERISTICS

V

=5V; VSS=0V; T

DD

specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA

V

DDD

I

DD(pd)

analog supply voltage 4.2 − 6.0 V
digital supply voltage 4.2 − 6.0 V
supply current in

power-down mode

I

DD(sm)

supply current in sleep
mode

I

DD(om)

supply current operating
mode

V

th(VDD)

threshold voltage on V
(falling)

V

hys(VthVDD)

V

th(CDELAY)

hysteresis on V
threshold voltage on

pin CDELAY

V

CDELAY

I

CDELAY

voltage on pin CDELAY −−VDDV
output current at

pin CDELAY

t

W

ALARM pulse width C

ALARM (open drain active HIGH or LOW output)

I

OH

V

OL

I

OL

V

OH

HIGH-level output current active LOW option; VOH=5V −−10 µA
LOW-level output voltage active LOW option; IOL=2mA −0.3 − +0.4 V
LOW-level output current active HIGH option; VOL=0V −−−10 µA
HIGH-level output voltage active HIGH option; IOH= −2mA VDD− 0.8 − VDD+ 0.3 V

=25°C; for general purpose I/O ports refer to 80CE560 data sheet; unless otherwise

amb

VDD= 5 V; card inactive; note 1 −−250 µA

card powered, microcontroller in

−−1500 µA
power-down mode but with clock
stopped; note 1

ICC= 65 mA; f
f

= 10 MHz; f

clk

f

CLKOUT

= 20 MHz; 5 V card;

= 20 MHz;

xtal

= 20 MHz;

osc

130 − 180 mA

notes 1 and 2
I

= 65 mA; f

CC

f

= 10 MHz; f

clk

f

CLKOUT

= 20 MHz; 3 V card;

= 20 MHz;

xtal

= 20 MHz;

osc

65 − 90 mA

notes 1 and 2
unloaded; f

f

= 5 MHz; f

clk

f

CLKOUT

= 20 MHz;

xtal

= 10 MHz;

osc

= 5 MHz; 5 V card;

1 − 6mA

notes 1 and 2
unloaded; f

f

= 5 MHz; f

clk

f

CLKOUT

= 5 MHz; 3 V card;

= 20 MHz;

xtal

osc

= 10 MHz;

0.5 − 4mA

notes 1 and 2

DD

th(VDD)

3.6 − 3.95 V

50 − 250 mV

− 1.38 − V

pin grounded (charge) −−1−µA
V

CDELAY=VDD
CDELAY

(discharge) − 2 − mA

=10nF − 10 − ms

1998 Jul 31 28

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Crystal oscillator

f

xtal

f

ext

CLKOUT

f

CLKOUT

V

OL

V

OH

t

o(r)

t

o(f)

δ duty factor C

Step-up converter

f

INT

V

VUP

Reset output to the card (pin RST)

V

o(RST)

I

o(RST)

V

OL

V

OH

t

r

t

f

Clock output to the card (pin CLK)

V

o(CLK)

I

o(CLK)

V

OL

V

OH

t

r

t

f

f

CLK

δ duty factor C
SR slew rate (rise and fall) C

crystal frequency 4 − 25 MHz
frequency of external

0 − 25 MHz
signal applied on
pin XTAL1

frequency on pin CLKOUT 0 − 25 MHz
LOW-level output voltage IOL=5mA −−0.8 V
HIGH-level output voltage IOH= −5mA VDD− 1 −− V
output rise time CL=60pF −−10 ns
output fall time CL=60pF −−10 ns

=60pF 40 − 60 %

L

internal oscillation

2 2.5 3 MHz
frequency

voltage on pin VUP − 6.5 − V

output voltage inactive mode; no load 0 − 0.1 V

inactive mode; I

= 1 mA 0 − 0.3 V

o(RST)

output current when inactive and pin grounded 0 −−1mA
LOW-level output voltage IOL= 200 µA0−0.3 V
HIGH-level output voltage IOH= −200 µAV

− 0.7 − V

CC

CC

V
rise time CL=30pF −−0.1 µs
fall time CL=30pF −−0.1 µs

output voltage inactive mode; no load 0 − 0.1 V

inactive mode; I

=1mA 0 − 0.3 V

o(CLK)

output current when inactive and pin grounded 0 −−1mA
LOW-level output voltage IOL= 200 µA0−0.3 V
HIGH-level output voltage IOH= −200 µAV

− 0.5 − V

CC

CC

V
rise time CL=30pF −−8ns
fall time CL=30pF −−8ns
clock frequency 1.25 MHz idle configuration 1 1.25 1.5 MHz

operational 0 − 10 MHz

=30pF 45 − 55 %

L

= 30 pF 0.2 −− V/ns

L

1998 Jul 31 29

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Card supply voltage (pin VCC); note 3

V

O(VCC)

card supply output voltage inactive

no load 0 − 0.1 V
I

O(VCC)

pin grounded 0 −−1mA

active

I

< 65 mA; 5 V card 4.75 5 5.25 V

CC

I

< 65 mA; 3 V card 2.8 3 3.2 V

CC

current pulses of 40 nAs with

< 200 mA; t < 400 ns;

I

CC

f < 20 MHz; 5 V card
current pulses of 24 nAs with

I

< 200 mA; t < 400 ns;

CC

f < 20 MHz; 3 V card

I

O(VCC)

I

CC(sd)

card supply output current from 0 to 3 or 5 V −−65 mA

V

short-circuited to GND −−250 mA

CC

shutdown current at
pin V

CC

SR slew rate up or down

(capacitor = 100 to 300 nF)
Data line (pin I/O); note 4
V

o(I/O)

output voltage inactive

no load 0 − 0.1 V
I

=1mA −−0.3 V

o(I/O)

I

o(I/O)

V

OL

output current inactive and pin grounded 0 −−1mA
LOW-level output voltage I/O configured as output;

IOL=1mA
V

OH

HIGH-level output voltage I/O configured as output;

IOH< −50 µA
V
V
I
I

IL

IH
IL
LIH

LOW-level input voltage I/O configured as input −0.3 − +0.8 V
HIGH-level input voltage I/O configured as input 1.5 − V
LOW-level input current VIL=0 V −−−600 µA
HIGH-level input leakage

VIH=V

CC

current

t

i(r)

t

i(f)

t

o(r)

t

o(f)

R

pu(int)

input rise time CL=30pF −−1 µs
input fall time CL=30pF −−1 µs
output rise time CL=30pF −−0.1 µs
output fall time CL=30pF −−0.1 µs
internal pull-up resistance

between I/O and V

CC

=1mA 0 − 0.3 V

4.6 − 5.4 V

2.75 − 3.25 V

−−80 − mA

0.10 0.16 0.22 V/µs

0 − 0.3 V

0.8V

CC

− VCC+ 0.25 V

CC

−−20 µA

81013kΩ

V

1998 Jul 31 30

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Auxiliary cards contacts (C4 and C8); note 5

V

o(C4,C8)

I

o(C4,C8)

V

OL

V

OH

V

IL

V

IH

I

IL

I

LIH

t

i(r)

t

i(f)

t

o(r)

t

o(f)

t

d

R

pu(int)

f

(max)

output voltage inactive

no load 0 − 0.1 V
I

o(C4,C8)

=1mA −−0.3 V
output current inactive and pin grounded −−−1mA
LOW-level output voltage C4 or C8 configured as output;

0 − 0.3 V

IOL=1mA

HIGH-level output voltage C4 or C8 and I/O configured as

output; I

< −50 µA

OH

0.8V

CC

− VCC+ 0.25 V

LOW-level input voltage C4 or C8 configured as input −0.3 − +0.8 V
HIGH-level input voltage C4 or C8 configured as input 1.5 − V

CC

V
LOW-level input current VIL=0V −−−600 µA
HIGH-level input leakage

VIH=V

CC

−−±20 µA

current
input rise time CL=30pF −−1 µs
input fall time CL=30pF −−1 µs
output rise time CL=30pF −−0.1 µs
output fall time CL=30pF −−0.1 µs
delay between falling edge

−−200 ns
on P34 and C4 (or
C4 and P34)

internal pull-up resistance

81013kΩ
between C4 and VCC and
C8 and V

maximum frequency on

CC

−−1 MHz

C4 or C8

Timing

t

act

activation sequence
duration

t

de

deactivation sequence
duration

t

3(start)

start of the window for
sending clock to the card

t

5(end)

end of the window for
sending clock to the card

Output ports from extension (

V

OL

V

OH

LOW-level output voltage IOL=2mA −−0.4 V
HIGH-level output voltage IOH= −2mA VDD− 1 −− V

K0 to K3)

1998 Jul 31 31

−−225 µs

−−100 µs

−−130 µs

145 −− µs

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Card presence input (pin PRES)

V

IL

V

IH

I

LIL

LOW-level input voltage −−0.3V
HIGH-level input voltage 0.7V
LOW-level input leakage

Vi=0V −−20 µA

DD

−− V

DD

current

I

LIH

HIGH-level input leakage

Vi=V

DD

−−20 µA

current

Notes

in all configurations include the current at pins VDD, V

1. I

DD

DDA

and V

DDRAM

.

2. Values given for program execution out of internal ROM. If execution out of external ROM or charges connected to
I/O ports, current consumption may be higher.

3. A ceramic multilayer capacitance with low ESR of minimum 100 nF should be used in order to meet these
specifications.

4. The I/O line has an integrated pull-up resistor of 10 kΩ at pin VCC.

5. Pins C4 and C8 have integrated pull-up resistors of 10 kΩ at pin VCC; P34 and P35 have integrated pull-up resistors
of 20 kΩ at pin VDD.

V

OPTIONS
Table 12 Options table

FEATURES OPTIONS

Alarm active HIGH active LOW
Presence active HIGH active LOW
MOVEC protection on off

1998 Jul 31 32

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1998 Jul 31 33

k, full pagewidth

APPLICATION INFORMATION

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

+5 V

GND

reset

RX

TX

V

DD

2

J1

J1

1

C20
100 nF

RESET

P10/T2

P11/T2EX

n.c.

P30/RXD

P31/TXD

P33/INT1

P36/WR

P37/RD

P20
P21

C21
33 µF

33 32 31 30 29 28 27 26 25 24 23

34
35
36
37
38
39
40
41
42
43
44

1

TEST

ALARM

P222P23

C7

4.7
nF

3

C21

33 pF

CDELAY

CLKOUT

TDA8006AH

4

5

ALE

PSEN

Y2

V

DD

PRES

6

XTAL2

C9

100 nF

VDDGNDC8C4

7EA8

XTAL1

P039P02

14.745 MHz

C20
33 pF

V

DD

C4
100
nF

R2
100 kΩ

R1

0 Ω

C8

C4

C7

C3

C6

C2

C5

C1

C1I

C5I

C2I

C6I

C3I

C7I

C4I

C8I

CARD READ UNIT

K1
K2

MGR239

C14
100 nF

CC

I/O

V

22
21
20
19
18
17
16
15
14
13
12

10

11

P01

P00

VUP

100 nF

S2
V

DDA
S1
AGND
CLK
RST
GNDRAM
V

DDRAM
n.c.
n.c.

C5
100 nF

C1

V

DD

C2

100

nF

C6
100 nF

V

DD

C3
10 µF

C10
47 pF

Fig.15 Application diagram.

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

PACKAGE OUTLINES

QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

51 33

52

pin 1 index

64

1

32

Z

e

w M

b

p

20

19

A

E

A

H

E

E

2

A

A

1

detail X

SOT319-2

L

p

L

(A )

3

θ

w M

b

e

p

Z

D

D

H

D

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.20

0.25

0.05

2.90

2.65

0.25

0.50

0.35

0.25

0.14

UNIT A1A2A3bpcE

(1)

(1) (1)(1)

D

20.1

19.9

eH

14.1

13.9

24.2

1

23.6

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT319-2

1998 Jul 31 34

H

B

D

E

18.2

17.6

v M

A

v M

B

LL

p

1.0

0.6

0.2 0.10.21.95

EUROPEAN

PROJECTION

Z

D

1.2

0.8

Zywv θ

E

o

1.2

7

o

0.8

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

pin 1 index

44

1

22

Z

E

e

H

E

E

w M

b

p

12

11

A

2

A

A

1

detail X

SOT307-2

(A )

3

θ

L

p

L

w M

b

e

p

D

H

D

Z

D

B

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

0.25

UNIT A1A2A3b

cE

p

0.40

0.25

0.20

0.14

(1)

(1) (1)(1)

D

10.1

9.9

eH

10.1

9.9

12.9

0.8 1.3

12.3

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

IEC JEDEC EIAJ

REFERENCES

SOT307-2

1998 Jul 31 35

v M

H

v M

D

A

B

E

12.9

12.3

LL

p

0.95

0.55

0.15 0.10.15

EUROPEAN

PROJECTION

Z

D

1.2

0.8

Zywv θ

E

1.2

0.8

o

10

o

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details,
refer to the Drypack information in the

“Data Handbook
IC26; Integrated Circuit Packages; Section: Packing
Methods”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Jul 31 36

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Jul 31 37

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

NOTES

1998 Jul 31 38

Philips Semiconductors Product specification

Multiprotocol IC Card coupler TDA8006

NOTES

1998 Jul 31 39

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone]

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545104/1200/01/pp40 Date of release: 1998 Jul 31 Document order number: 9397 750 03256