Datasheet TDA8005AG, TDA8005AH Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8005A

Low-power (3 V/5 V) smart card
coupler

Preliminary specification
File under Integrated Circuits, IC17

1998 Mar 20

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

FEATURES

• Smart card supply (5 and 3 V ±5%, 20 mA maximum
with controlled rise and fall times)

• Smart card clock generation (up to 8 MHz), with two
times synchronous frequency doubling

• Clock STOP HIGH, clock STOP LOW or 1.25 MHz (from
internal oscillator) for cards power-down mode

• Specific UART on I/O for automatic direct/inverse
convention settings and error management at
character level

• Automatic activation and deactivation sequences
through an independent sequencer

• Supports the protocol T = 0 in accordance with
ISO 7816 GSM11.11 requirements (Global System for
Mobile communication); approved for Final GSM11.11
Test Approval (FTA)

• Several analog options are available for different
applications: doubler or tripler DC-to-DC converter, card
presence, active HIGH or LOW, threshold voltage
supervisor, etc.

• Overloads and take-off protections

• Current limitations in the event of short-circuit

• Special circuitry for killing spikes during power-on or off

• Supply supervisor

• Step-up converter (supply voltage from 2.5 to 6 V)

• Power-down and sleep mode for low power

consumption

• Enhanced ElectroStatic Discharge (ESD) protections on
card side (6 kV minimum)

• Control and communication through a standard RS232
full-duplex interface

• Optional additional I/O ports for:
– keyboard
– LEDs
– display
– etc.

• P80CL51 microcontroller core with 4-kbyte ROM and
256-byte RAM.

APPLICATIONS

• Portable smart card readers for protocol T = 0

• GSM mobile phones.

GENERAL DESCRIPTION

The TDA8005A is a low-cost card interface for portable
smart card readers. Controlled through a standard serial
interface, it takes care of all ISO 7816 and GSM11.11
requirements for both 5 and 3 V cards. It gives the card
and the set a very high level of security, due to its special
hardware against ESD, short-circuiting, power failure, etc.
Its integrated step-up converter allows operation within a
supply voltage range of 2.5 to 6 V.

The very low power consumption in power-down and sleep
modes saves battery power.

Development tools, application report and support
(hardware and software) are available.

ORDERING INFORMATION

TYPE

NUMBER

TDA8005AG LQFP64 plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2
TDA8005AH QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);

1998 Mar 20 2

NAME DESCRIPTION VERSION

body 10 × 10 × 1.75 mm

PACKAGE

SOT307-2

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

I

DD(pd)

I

DD(sm)

I

DD(om)

V

CC

I

CC

SR slew rate on V

t

de

t

act

f

XTAL

T

amb

supply voltage doubler and tripler option 2.5 − 6.0 V
supply current in power-down mode VDD= 5 V; card inactive − 100 −µA
supply current in sleep mode card powered but clock

stopped; no load

doubler option − 500 −µA
tripler option − 700 −µA

supply current in operating mode unloaded; f

= 6.5 MHz; f

f

µC

XTAL

= 13 MHz;

= 3.25 MHz

card

− 5.5 − mA

card supply voltage 5 V card

no load 4.85 5.05 5.25 V
static load 4.75 5.0 5.25 V
dynamic load on 200 nF

4.5 − 5.4 V

capacitor

3 V card

no load 2.9 3.03 3.15 V
static load 2.79 3 3.21 V
dynamic load on 200 nF

2.75 − 3.25 V

capacitor

card supply current operating −−20 mA

limitation −−note 1 mA

(rise and fall) maximum load capacitor

CC

0.04 0.1 0.16 V/µs
250 nF (including typical
200 nF decoupling)

deactivation sequence duration −−225 µs
activation sequence duration −−150 µs
crystal frequency 2 − 16 MHz
operating ambient temperature −25 − +85 °C

Note

1. See Table 3 for mask options.

1998 Mar 20 3

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

BLOCK DIAGRAM

handbook, full pagewidth

V

DDA

2.5 to 6 V
100 nF

ALARM

DELAY

RESET

RxD

TxD
AUX1
AUX2

INT1

P00

to

P37

V

63 (43)

44

46 (31)

22 (17)

DDD

100 nF

10 (7)

SUPPLY

INTERNAL

REFERENCE

VOLTAGE SENSE

2.3 to 2.7 V

alarm

ref

TDA8005AG

47 nF

S1 S2

64 (44) 61 (41) 3 (2) 62 (42)

STEP-UP CONVERTER

INTERNAL OSCILLATOR

2.5 MHz

V

DDD

47 nF

S3 S4

osc ref

60 (40)

V

UP

S5

47 nF

(TDA8005AH)

V

DDD

28 (18)
29 (19)
32 (22)
33 (23)
30 (20)

(1)

CONTROLLER

CL51

4 kbytes ROM

256-byte RAM

OPTIONAL

PORTS

data clk EN S0 S1 R/W

skill

start

RST

off

SEQUENCER

INT

SECURITY

EN1

EN2

EN3

V

CC

GENERATOR

RST

BUFFER

I/O

BUFFER

59 (39)

58 (38)

56 (36)

55 (35)

V

LIS

CC

100 nF

RST

I/O

PERIPHERAL

INTERFACE

micro-

controller

clock

XTAL1 XTAL2

Pin numbers in parenthesis represent the TDA8005AH.
(1) For details see Chapter “Pinning” and Table 3.

ISO 7816 UART

CLOCK CIRCUITRY

osc

36 (26) 35 (25) 37 (27) 2 (1) 53

DGND AGND

Fig.1 Block diagram.

1998 Mar 20 4

I/O

EN4

CLOCK

BUFFER

OUTPUT PORT

EXTENSION

52 51 50 49

K0 K1 K2 K3 K4 K5

57 (37)

47 (32)

4

MGL330

CLK

PRES

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

PINNING

SYMBOL

n.c. 1 − not connected
AGND 2 1 analog ground
S3 3 2 contact 3 for the step-up converter
K5 4 − output port from port extension
P03 5 3 general purpose I/O port (connected to port P03)
P02 6 4 general purpose I/O port (connected to port P02)
P01 7 5 general purpose I/O port (connected to port P01)
n.c. 8 − not connected
P00 9 6 general purpose I/O port (connected to port P00)
V

DDD

n.c. 11 − not connected
TEST1 12 8 test pin 1 (connected to port P10; must be left open-circuit in the application)
P11 13 9 general purpose I/O port or interrupt (connected to port P11)
P12 14 10 general purpose I/O port or interrupt (connected to port P12)
P13 15 11 general purpose I/O port or interrupt (connected to port P13)
P14 16 12 general purpose I/O port or interrupt (connected to port P14)
n.c. 17 − not connected
P15 18 13 general purpose I/O port or interrupt (connected to port P15)
P16 19 14 general purpose I/O port or interrupt (connected to port P16)
TEST2 20 15 test pin 2 (connected to PSEN; must be left open-circuit in the application)
P17 21 16 general purpose I/O port or interrupt (connected to port P17)
RESET 22 17 input for resetting the microcontroller (active HIGH)
n.c. 23 − not connected
n.c. 24 − not connected
n.c. 25 − not connected
n.c. 26 − not connected
n.c. 27 − not connected
RxD 28 18 serial interface receive line
TxD 29 19 serial interface transmit line
INT1 30 20 general purpose I/O port or interrupt (connected to port P33)
T0 31 21 general purpose I/O port (connected to port P34)
AUX1 32 22 push-pull auxiliary output (±5 mA; connected to timer T1 e.g. port P35)
AUX2 33 23 push-pull auxiliary output (±5 mA; connected to timer; port P36)
P37 34 24 general purpose I/O port (connected to port P37)
XTAL2 35 25 crystal connection
XTAL1 36 26 crystal connection or external clock input
DGND 37 27 digital ground
n.c. 38 − not connected

LQFP64 QFP44

PIN

DESCRIPTION

10 7 digital supply voltage

1998 Mar 20 5

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

SYMBOL

n.c. 39 − not connected
P20 40 28 general purpose I/O port (connected to port P20)
P21 41 − general purpose I/O port (connected to port P21)
P22 42 29 general purpose I/O port (connected to port P22)
P23 43 30 general purpose I/O port (connected to port P23)
ALARM 44 − open-drain output for power-on reset (active HIGH or LOW by mask option)
n.c. 45 − not connected
DELAY 46 31 external capacitor connection for delayed reset signal
PRES 47 32 card presence contact input (active HIGH or LOW by mask option)
TEST3 48 33 test pin 3 (must be left open-circuit in the application)
K4 49 − output port from port extension
K3 50 − output port from port extension
K2 51 − output port from port extension
K1 52 − output port from port extension
K0 53 − output port from port extension
TEST4 54 34 test pin 4 (must be left open-circuit in the application)
I/O 55 35 data line to/from the card (ISO C7 contact)
RST 56 36 card reset output (ISO C2 contact)
CLK 57 37 clock output to the card (ISO C3 contact)
V

CC

LIS 59 39 supply for low-impedance on cards contacts
S5 60 40 contact 5 for the step-up converter
S2 61 41 contact 2 for the step-up converter
S4 62 42 contact 4 for the step-up converter
V

DDA

S1 64 44 contact 1 for the step-up converter

LQFP64 QFP44

PIN

DESCRIPTION

58 38 card supply output voltage (ISO C1 contact)

63 43 analog supply voltage

1998 Mar 20 6

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

handbook, full pagewidth

V

n.c.

AGND

S3

K5
P03
P02
P01

n.c.

P00

DDD

n.c.

TEST1

P11
P12
P13
P14

DDA

VS1S4

64

63
1
2
3
4
5
6
7
8

S2

S5.

62

61

60

LIS
59

CC

V

CLK

RST

I/O

TEST4K0K1
54

58

57

56

55

53

K2

K3

K4

50

52

51

49

TEST3

48
47

PRES

46

DELAY

45

n.c.
ALARM

44
43

P23

42

P22

41

P21

TDA8005AG

P20

9

10
11
12
13
14
15
16

40
39

n.c.

38

n.c.

37

DGND

36

XTAL1

35

XTAL2

34

P37

33

AUX2

17
n.c.

18

P15

19

P16

20

TEST2

21

P17

22

RESET

23
n.c.

Fig.2 Pin configuration (LQFP64).

1998 Mar 20 7

24
n.c.

25
n.c.

26

n.c.

27
n.c.

28

RxD

29

TxD

30

INT1

31
T0

32

AUX1

MGL331

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

handbook, full pagewidth

AGND

S3
P03
P02
P01
P00

V

DDD

TEST1

P11
P12
P13

DDA

S1

V

S4

S2

S5

44

43

42

41

40

1
2
3
4
5

14

P16

TDA8005AH

15

16

P17

TEST2

6
7
8

9
10
11

12

13

P14

P15

LIS

39

17

RESET

CC

V

38

18

RxD

CLK

37

19

TxD

RST

36

20

INT1

I/O

35

21
T0

TEST4

34

22

AUX1

33
32
31
30
29
28
27
26
25
24
23

MGL332

TEST3
PRES
DELAY
P23
P22
P20
DGND
XTAL1
XTAL2
P37
AUX2

Fig.3 Pin configuration (QFP44).

1998 Mar 20 8

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

FUNCTIONAL DESCRIPTION
Microcontroller

The microcontroller is a P80CL51 with 256 bytes of RAM
instead of 128. The baud rate of the UART has been
multiplied by four in modes 1, 2 and 3. This means that the
division factor of 32 in the formula is replaced by 8 in both
reception and transmission mode and that in the reception
modes only four samples per bit are taken with decision on
the majority of samples 2, 3 and 4; the delay counter has
been reduced from 1536 to 24 as well.

Remark: this has an impact when getting out of
power-down mode. It is recommended to switch to
internal clock before entering power-down mode.

All the other functions remain unchanged. Refer to the
P80CL51 data sheet for any further information. Internal
ports INT0 (P32), P10, P04 to P07 and P24 to P27 are
used for controlling the smart card interface.

Mode 0 is unchanged. The baud rate for modes 1 and 3 is:

SMOD

2

---------------- ­8

×

---------------------------------------------- ­12 256 TH1–()×

f

clk

The baud rate for mode 2 is:

SMOD

2

---------------- ­16

f

×

clk

For mode 3 timing see Table 1.

Supply

The circuit operates within a supply voltage range of

2.5 to 6 V. The supply pins are V
AGND. Pins V

and AGND supply the analog drivers to

DDA

DDD

, V

DDA

, DGND and

the card and have to be externally decoupled because of
the large current spikes that the card and the step-up
converter can create. An integrated spike killer ensures
the contacts to the card remain inactive during power-up or
power-down. An internal voltage reference is generated
which is used within the step-up converter, the voltage
supervisor and the V

generator.

CC

The voltage supervisor generates an internal alarm pulse,
whose length is defined by an external capacitor tied to the
DELAY pin, when V

is too low to ensure proper

DDD

operation (1 ms per 1 nF typical). This pulse is used as a
reset pulse by the controller, in parallel with an external
reset input, which can be tied to the system controller.

It is also used in order to either block any spurious card
contacts during controllers reset, or to force an automatic
deactivation of the contacts in the event of supply dropout;
see Sections “Activation sequence” and “Deactivation
sequence”.

In the 64 pin version, this reset pulse is output to the open
drain ALARM pin, which may be selected active HIGH or
active LOW by mask option and may be used as a reset
pulse for other devices within the application.

Table 1 Mode 3 timing

BAUD

= 6.5 MHz;

f

clk

VDD=5V

f

= 3.25 MHz;

clk

VDD=5or3V

RATE

SMOD TH1 SMOD TH1

135416 1 255 −−
67708 0 255 1 255
45139 1 253 −−
33854 0 254 0 255
27083 1 251 −−
22569 0 253 1 253
16927 −−0 254
13542 −−1 251
11285 0 250 0 253

1998 Mar 20 9

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

handbook, full pagewidth

V

th(VDD)

+ V

hys(VthVDD)

V

th(DELAY)

V

th(VDD)

V

DELAY

ALARM

V

DD

Fig.4 Supply supervisor.

Low impedance supply (pin LIS)

For some applications, it is mandatory that the contacts to
the card (VCC, RST, CLK and I/O) are low impedance while
the card is inactive and also when the coupler is not
powered. An auxiliary supply voltage on pin LIS ensures
this condition where I

≤ 5 µA for V

LIS

= 5 V. This low

LIS

impedance situation is disabled when VCC starts rising
during activation, and re-enabled when the step-up
converter is stopped during deactivation. If this feature is
not required, the LIS pin must be tied to V

DDD

.

Step-up converter

Except for the V
buffers, the whole circuit is powered by V

generator and the other cards contacts

CC

and V

DDD

DDA

.
If the supply voltage is 3 or 5 V, then a higher voltage is
needed for the ISO contacts supply. When a card session
is requested by the controller, the sequencer first starts the
step-up converter, which is a switched capacitors type,
clocked by an internal oscillator at a frequency of
approximately 2.5 MHz. The output voltage V
regulated at approximately 6.5 V and then fed to the V

step-up

is

CC

generator. VCC and DGND are used as a reference for all
other cards contacts.

MGL333

The step-up converter may be chosen as a doubler or a
tripler by mask option, depending on the voltage and the
current needed on the card.

ISO 7816 security

The correct sequence during activation and deactivation of
the card is ensured through a specific sequencer, clocked
by a division ratio of the internal oscillator.

Activation (START signal P05; see Table 3) is only
possible if the card is present (PRES HIGH or LOW
according to mask option), and if the supply voltage is
correct (ALARM signal inactive); CLK and RST are
controlled by RSTIN (internal signal; port P04), allowing
the correct count of CLK pulses during answer-to-reset
from the card.

The presence of the card is signalled to the controller by
the OFF signal (port P10; see Table 3).

During a session, the sequencer performs an automatic
emergency deactivation in the event of card take-off,
supply voltage drop, or hardware problems. The OFF
signal falls thereby warning the controller.

1998 Mar 20 10

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

Clock circuitry

The clock to the microcontroller and the clock to the card
are derived from the main clock signal (XTAL from
2 to 16 MHz, or an external clock signal).

Directly after reset and during power reduction modes the
microcontroller clock frequency f

equals1⁄8f

clk

INT

; f

is

INT

always present because it is derived from the internal
oscillator and gives the lowest power consumption.
When required (for card session, serial communication or
anything else) the microcontroller may choose to clock
itself with

XTAL

,1⁄4f

XTAL

or1⁄2f

. All frequency changes

INT

1

⁄2f

are synchronous, thereby ensuring no hang-up due to
short spikes etc.

Cards clock: the microcontroller may select to send the
card a card clock frequency of1⁄2f

1

⁄2f

(≈1.25 MHz), or to stop the clock HIGH or LOW.

INT

XTAL

,1⁄4f

XTAL

,1⁄8f

XTAL

or

All transitions are synchronous, ensuring correct pulse
length during start or change in accordance with
ISO 7816.

After power on, CLK is set at STOP LOW and f

1

⁄8f

.

INT

is set at

clk

Power-down and sleep modes

The TDA8005A offers a large flexibility for defining power
reduction modes by software. Some configurations are
described below.

In the power-down mode, the microcontroller is in
power-down and the supply and the internal oscillator are

active. The card is not active; this is the smallest power
consumption mode. Any change on P1 ports or on PRES
will wake-up the circuit (for example, a key pressed on the
keyboard, the card inserted or taken off).

In the sleep mode, the card is powered but configured in
the idle or sleep mode. The step-up converter will only be
active when it is necessary to reactivate V

step-up

. When the
microcontroller is in power-down mode any change on P1
ports or on PRES will wake up the circuit.

In both power reduction modes the sequencer is active,
allowing automatic emergency deactivation in the event of
card take-off, hardware problems, or supply dropout.

The TDA8005A is set into power-down or sleep mode by
software. There are several ways to return to normal
mode: insertion or extraction of the card, detection of a
change on P1 (which can be a key pressed) or a command
from the system microcontroller. For example, if the
system monitors the clock signal on XTAL1, it may stop
this clock after setting the device into power-down mode
and then wake it up when sending the clock signal again.
In this situation, the internal clock should have been used
before the f

clk

.

Peripheral interface

This block allows synchronous serial communication with
the three peripherals (ISO 7816 UART, clock circuitry and
output port extension); see Figs 1 and 5.

handbook, full pagewidth

RESET

CC0 CC1 CC2 CC3 CC4 CC5 CC6 CC7

UC0

UT0

PE0

P24

DATA

clock configuration

UART configuration

UC1 UC2 UC3 UC4 UC5 UC6 UC7

UART transmit

UT1 UT2 UT3 UT4 UT5 UT6 UT7

ports extension

PE1 PE2 PE3 PE4 PE5 PE6 PE7

P06

STROBE

P07

ENABLE

PERIPHERAL CONTROL

P27

REG0

Fig.5 Peripheral interface diagram.

1998 Mar 20 11

P26

REG1

P25

R/W

UR1 UR2 UR3 UR4 UR5 UR6 UR7

UR0

US1 US2 US3 US4 US5 US6 US7

US0

P32
INT

UART receive

UART status register

MGL334

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

Table 2 Explanation of Fig.5; note 1

BIT NAME DESCRIPTION

REG0 = 0, REG1 = 0 and R/
(configuration after reset is cards clock STOP LOW, f

CC0 cards clock =
CC1 cards clock =1⁄4f
CC2 cards clock =1⁄8f
CC3 cards clock =1⁄2f

W = 0; CLOCK configuration register

=1⁄8f

clk

1

⁄2f

XTAL
XTAL
XTAL
INT

INT

)

CC4 cards clock = STOP HIGH
CC5 f
CC6 f
CC7 f

clk
clk
clk

=1⁄2f
=1⁄4f
=1⁄2f

XTAL
XTAL
INT

REG0 = 1, REG1 = 0 and R/W = 0; UART configuration register (after reset all bits are cleared)

UC0 ISO UART RESET
UC1 START SESSION
UC2 LCT (Last Character to Transmit)
UC3 TRANSMIT/RECEIVE
UC4 3 V/5 V
UC5 to UC7 not used

REG0 = 0, REG1 = 1 and R/

W = 0; UART transmit register

UT0 to UT7 LSB to MSB of the character to be transmitted to the card

REG0 = 1, REG1 = 1 and R/W = 0; PORTS EXTENSION (after reset all bits are cleared)

PE0 to PE5 PE0 to PE5 is the inverse of the value to be written on K0 to K5
PE6 and PE7 not used

REG0 = 0, REG1 = 0 and R/

W = 1; UART receive register

UR0 to UR7 LSB to MSB of the character received from the card

REG0 = 1, REG1 = 0 and R/

W = 1; UART status register (after reset all bits are cleared)

US0 UART transmit buffer empty
US1 UART receive buffer full
US2 first start bit detected
US3 parity error detected during reception of a character (the UART has asked the card to repeat the

character)

US4 parity error detected during transmission of a character; the controller must write the previous

character in the UART transmit register, or abort the session

US5 to US7 not used

Note

1. All registers are active HIGH.

1998 Mar 20 12

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

USE OF PERIPHERAL INTERFACE

Write operation

1. Select the correct register with R/W, REG0 and REG1

2. Write the word in the Peripheral Shift Register (PSR)
with DATA and STROBE; DATA is shifted on the rising
edge of STROBE; 8 shifts are necessary

3. Give a negative pulse on ENABLE; the data is parallel
loaded in the register on the falling edge of ENABLE.

Read operation

1. Select the correct register with R/W, REG0 and REG1

2. Give a first negative pulse on ENABLE; the word is
parallel loaded in the peripheral shift register on the
rising edge of ENABLE

3. Give a second negative pulse on ENABLE for
configuring the PSR in shift right mode

4. Read the word from PSR with DATA and STROBE;
DATA is shifted on the rising edge of STROBE; 7 shifts
are necessary.

E

XAMPLE OF PERIPHERAL INTERFACE

;****************************************
;*CHANGE OF CLOCK CONFIGURATION REGISTER*
;****************************************
;
;**THE NEW CONFIGURATION IS SUPPOSED**
;**TO BE IN THE ACCUMULATOR**

CLR REG0
CLR REG1
CLR R/W
MOV R2,#8

LOOP RRC A

MOV DATA C
CLR STROBE
SET STROBE
DJNZ R2,LOOP
CLR ENABLE
SET ENABLE
SET DATA
RET

;****************************************
;*READ CHARACTER ARRIVED IN UART RECEIVE*
;*****************REGISTER***************
;****************************************
;
;**THE CHARACTER WILL BE IN THE**
;**ACCUMULATOR**

CLR REG0
CLR REG1
SET R/

W
CLR ENABLE
SET ENABLE
CLR ENABLE
SET ENABLE
MOV R2,#8

LOOP MOV C,DATA

RRC A
CLR STROBE
SET STROBE
DJNZ R2,LOOP
SET DATA
RET

ISO UART

The ISO UART handles all the specific requirements
defined in ISO T = 0 protocol type. It is clocked with the
cards clock, which gives the f

/31 sampling rate for start

clk

bit detection (the start bit is detected at the first LOW level
on I/O) and the f

/372 frequency for Elementary Time Unit

clk

(ETU) timing (in the reception mode the bit is sampled at

1

⁄2ETU). It also allows the cards clock frequency changes

without interfering with the baud rate.
This hardware UART allows operating of the

microcontroller at low frequency, thus lowering EM
radiations and power consumption. It also frees the
microcontroller of fastidious conversions and real time jobs
thereby allowing the control of higher level tasks.

The following occurs in the reception mode (see Fig.6):

• Detection of the inverse or direct convention at the
beginning of Answer To Reset (ATR)

• Automatic convention setting, so the microcontroller
only receives characters in direct convention

• Parity checking and automatic request for character
repetition in case of error (reception is possible at
12 ETU).

1998 Mar 20 13

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

The following occurs in the transmission mode (see Fig.7):

• Transmission according to the convention detected
during ATR, consequently the microcontroller only has
to send characters in direct convention; transmission of
the next character may start at 12 ETU in the event of no
error or 13 ETU in case of error

• Parity calculation and detection of repetition request
from the card in the event of error

• The bit LCT (Last Character to Transmit) allows fast
reconfiguration for receiving the answer 12 ETU after
the start bit of the last transmitted character.

The ISO UART status register can inform which event has
caused an interrupt (buffer full, buffer empty, parity error
detected etc.) in accordance with peripheral interface.

The register is reset when its status is read by the
microcontroller.

The ISO UART configuration register enables the
microcontroller to configure the ISO UART and to choose
between 5 or 3 V cards. Bit UC4 (3 V/5 V) LOW means
5 V card, bit UC4 (3 V/5 V) HIGH means 3 V card; conform
peripheral interface. The selection of 3 or 5 V card has to
be done before activation.

The convention is recognized on the first character of the
ATR and the UART configures itself in order to exchange
direct data without parity processing with the
microcontroller whatever the convention of the card is.
Bit UC1 (START SESSION) must be reset by software.
At the end of every character, the UART tests the parity
and resets what is necessary for receiving another
character.

If no parity error is detected, the UART sets bit US1 (UART
receive buffer full) in the status register which warns the
microcontroller it has to read the character before the
reception of the next one has been completed. The status
register is reset when read from the controller.

If a parity error has been detected, the UART pulls the I/O
line LOW between 10.5 and 12 ETU. It also sets the
bits US1 (UART receive buffer full) and US3 (parity error
detected during reception of a character) in the status
register which warns the microcontroller that an error has
occurred. The card is supposed to repeat the previous
character.

After power-on, all ISO UART registers are reset.
The ISO UART is configured in the reception mode. When

the microcontroller wants to start a session, it sets the bits
UC1 (START SESSION) and UC0 (ISO UART RESET) in
the UART configuration register and then sets bit START
SESSION LOW. When the first start bit on I/O is detected
(sampling rate f
start bit detected) in the status register which gives an
interrupt on internal port INT0 one clock pulse later.

/31), the UART sets the bit US2 (first

clk

1998 Mar 20 14

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

handbook, full pagewidth

START; and T/R = 0START; T/R = 0 or LCT = 1

SET ENABLE FSD

INHIBIT I/O DURING 200 CLK

SAMPLE I/O EVERY 31 CLK

I/O = 0

SAMPLE I/O AT 186

AND EVERY 372 CLK

CONVERT AND LOAD CHARACTER
IN RECEPTION BUFFER AT 10 ETU

CHECK PARITY

DISABLE I/O BUFFER BETWEEN

10 AND 12 ETU

(1)

clock starts

y

n

10th bit

5th bit

parity error

SET FSD STATUS REGISTER

IF FSD IS ENABLED

RESET EN FSD

SET CONVENTION

IF START SESSION = 1

SET BIT RECEPTION PARITY

ERROR AT 10 ETU

PULL I/O LINE LOW FROM

10.5 TO 11.75 ETU

(2)

SET BIT BUFFER FULL AT 10 ETU

RESET RECEPTION PART AT 12 ETU

STOP; T/R = 1

(1) FSD = First Start Detect.
(2) The start session is reset by software.
(3) The software may load the received character in the peripheral control at any time without any action on the ISO UART.

(3)

Fig.6 ISO UART reception flow chart.

1998 Mar 20 15

MGL335

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

When the controller needs to transmit data to the card, it
first sets bit UC3 in the UART configuration register which
configures the UART in the transmission mode. As soon
as a character has been written in the UART transmit
register, the UART makes the conversion, calculates the
parity and starts the transmission on the rising edge of
ENABLE. When the character has been transmitted, it
surveys the I/O line at 11 ETU in order to know if an error
has been detected by the card.

If no error has occurred, the UART sets bit US0 (UART
transmit buffer empty) in the status register and waits for
the next character. If the next character has been written
before 12 ETU, the transmission will start at 12 ETU. If it
was written after 12 ETU it will start on the rising edge of
ENABLE.

If an error has occurred, it sets bits US0 and US4 (parity
error detected during transmission of a character) which
warns the microcontroller to rewrite the previous character
in the UART transmit register.

If the character has been rewritten before 13 ETU, the
transmission will start at 13 ETU. If it has been written after
13 ETU it will start on the rising edge of ENABLE.

When the transmission is completed, the microcontroller
may set bit LCT (Last Character to Transmit) so that the
UART will force the reception mode into ready to get the
reply from the card at 12 ETU. This bit must be reset
before the end of the first reception. Bit UC3
(TRANSMIT/RECEIVE) must be reset to enable the
reception of the characters to follow.

When the session is completed, the microcontroller
re-initializes the whole UART by resetting bit UC0 (ISO
UART RESET).

1998 Mar 20 16

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

handbook, full pagewidth

START; T/R

SET TRANSMIT ENABLE

transmit register selected

CONVERT, CALCULATE PARITY

AND LOAD IN TRANSMIT

SHIFT REGISTER

SHIFT EVERY ETU IF TRANSMIT

ENABLE IS SET

SET I/O BUFFER IN

RECEPTION AT 10 ETU

SAMPLE I/O AT 11 ETU

SET BIT BUFFER EMPTY

AT 11 ETU

10th bit shifted

parity
error

n

(1)

y

SET BIT TRANSMISSION PARITY

ERROR AND BUFFER EMPTY

AT 11 ETU

(2)

y

LCT = 1

n

RESET TRANSMIT PART AT 11 ETU

FORCE RECEPTION MODE

STOP

(1) The transmit register may be loaded just after reading from the status register.
(2) The software must reset the last character but before completion of the first received character.

RESET TRANSMIT PAR T AND

ENABLE TRANSMIT AT 12 ETU

T/R = 0

STOP

n

y

Fig.7 ISO UART transmission flow chart.

RESET TRANSMIT PAR T AND

ENABLE TRANSMIT AT 13 ETU

MGL336

1998 Mar 20 17

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

I/O buffer modes (see Fig.8) The I/O buffer modes are:

• I/O buffer disabled

• I/O buffer in input, 20 kΩ pull-up resistor connected

between I/O and VCC, I/O masked till 200 clock pulses

• I/O buffer in input, 20 kΩ pull-up resistor connected
between I/O and VCC, I/O is sampled every 31 clock
pulses

• I/O buffer in output, 20 kΩ pull-up resistor connected
between I/O and V

CC

• I/O buffer in output, I/O is pulled LOW by the N transistor
of the buffer

• I/O buffer in output, I/O is pulled HIGH or LOW by the
P or N transistor.

Output ports extension

In the LQFP64 version, 6 auxiliary output ports may be
used for low frequency tasks (for example, keyboard
scanning). These ports are push-pull output types
(in accordance with use in software document).

Activation sequence

In order to allow a precise count of clock pulses during
ATR, a defined time window (t

; t5) is opened where the

3

clock may be sent to the card by means of RSTIN
(port P04). Beyond this window, RSTIN has no more
action on clock, and only monitors the cards RST contact
(RST is the inverse of RSTIN).

The sequencer is clocked by f

/64 which leads to a time

INT

interval T of 25 µs typical. Thus t1=0to1⁄64T,
t2=t1+3⁄2T, t3=t1+ 4T, t4=t3to t5 and t5=t1+ 7T.

Deactivation sequence

When the session is completed, the microcontroller sets
START HIGH. The circuit then executes an automatic
deactivation sequence (see Fig.10):

1. Card reset (RST falls LOW) at t

2. Clock is stopped at t

11

10

3. I/O becomes high impedance to the ISO UART (t12)

4. VCC falls to 0 V with typical 0.1 V/µs slew rate (t13)

5. The step-up converter is stopped and CLK; RST, V

CC

and I/O become low impedance to GND (t14)

6. t10<1⁄64T; t11=t10+1⁄2T; t12=t10+ T; t13=t10+3⁄2T;
t14=t10+ 5T.

When the card is inactive, V

, CLK, RST and I/O are

CC

LOW, with low impedance with respect to GND.
The step-up converter is stopped. The I/O is configured in
the reception mode with a high impedance path to the ISO
UART, subsequently no spurious pulse from the card
during power-up will be taken into account until I/O is
enabled. When conditions are fulfilled (supply voltage
present, card present, no hardware problems), the
microcontroller may initiate an activation sequence by
setting START LOW (t0; see Fig.9):

1. The step-up converter is started (t1)

2. LIS signal is disabled by internal signal ENLI, and V

CC

starts rising from 0 to 5 or 3 V (according to bit 4 of
UART configuration register) with a controlled rise time
of 0.1 V/µs typically (t2)

3. I/O buffer is enabled (t3)

4. Clock is sent to the card (t4)

5. RST buffer is enabled (t5).

Protections

Main hardware fault conditions are monitored by the
circuit:

• Overcurrent on V

(in accordance with options as

CC

specified in Table 3)

• Short circuits between VCC and other contacts

• Card take-off during transaction.

When one of these problems is detected, the security logic
block pulls the interrupt line (port P10) OFF LOW, in order
to warn the microcontroller and initiates an automatic
deactivation of the contacts. When the deactivation has
been completed, the OFF line returns HIGH, except if the
problem was due to a card extraction in which case it
remains LOW until a card is inserted.

1998 Mar 20 18

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

handbook, full pagewidth

I/O

MODE

OUT

IN

T

R

PRES

I/O BUFFER

ISO UART

handbook, full pagewidth

activation character

12 34543416363343 1

character
reception
with error

character
reception

without

error

character

transmission

with error

character

transmission

without

error

reception

without

error

forced

deactivation

MBH638

Fig.8 I/O buffer modes.

START

f

INT

V

step-up

ENRST

RSTIN

OFF

/64

V

CC

I/O

CLK

RST

ENLI

internal

internal

t

3

t

act

Fig.9 Activation sequence.

MGL337

1998 Mar 20 19

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

handbook, full pagewidth

PRES

OFF

START

f

/64

INT

RST

CLK

I/O

V

CC

V

step-up

ENLI

internal

t10t11t12t

13

t

de

t

14

Fig.10 Emergency deactivation sequence after a card take-off.

MGL338

1998 Mar 20 20

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

V

DDD

V

n

I

n1

I

n2

I

n3

I

n4

I

n5

I

n6

I

n7

P

tot

T

stg

V

esd

T

j

analog supply voltage −0.3 +6.5 V
digital supply voltage −0.3 +6.5 V
all input voltages −0.3 VDD+ 0.5 V
DC current into pins XTAL1, XTAL2, RxD,

− 5mA
TxD, RESET, INT1, T0 (port P34), P37,
P00 to P03, P11 to P17, P20 to P23 and
TEST1 to TEST4

DC current from or to pins AUX1 and AUX2 −10 +10 mA
DC current from or to pins S1 to S5 −30 +30 mA
DC current into pin DELAY −5 +10 mA
DC current from or to pin PRES −5+5mA
DC current from and to pins K0 to K5 −5+5mA
DC current from or into pin ALARM

−5+5mA
(according to option choice)

total power dissipation T

= −25 to +85°C − 500 mW

amb

storage temperature −55 +150 °C
electrostatic discharge on pins I/O, VCC, RST,

−6+6kV

CLK and PRES
on other pins −2+2kV

junction temperature −−125 °C

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air

LQFP64 70 K/W
QFP44 60 K/W

1998 Mar 20 21

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

CHARACTERISTICS

V

=5V; VSS=0V; T

DD

specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DD

I

DD(pd)

supply voltage voltage superior, option

supply current in power-down
mode

I

DD(sm)

I

DD(om)

supply current in sleep mode card powered but clock

supply current operating
mode

V

th(VDD)

threshold voltage on V
(falling)

V

hys(VthVDD)

V

th(DELAY)

hysteresis on V
threshold voltage on

pin DELAY

V

DELAY

I

DELAY

t

W

voltage on pin DELAY VDD− 0.5 − V
output current at pin DELAY pin grounded (charge) −1.5 −1 −0.4 µA

ALARM pulse width C

ALARM (open drain active HIGH or LOW output)

I

V

I

V

OH

OL

OL

OH

HIGH-level output current active LOW option;

LOW-level output voltage active LOW option;

LOW-level output current active HIGH option;

HIGH-level output voltage active HIGH option;

=25°C; for general purpose I/O ports refer to P80CL51 data sheet; unless otherwise

amb

2.5 − 6.0 V

dependant; note 1
VDD= 5 or 3 V; card inactive − 100 −µA

stopped; no load

doubler option − 500 −µA
tripler option − 700 −µA

DD

unloaded; f
f

= 6.5 MHz;

clk

f

= 3.25 MHz

card

V

=3V; f

DD

f

= 3.25 MHz;

clk

f

= 3.25 MHz

card

supervisor option 2 − 2.3 V

XTAL

XTAL

= 13 MHz;

= 13 MHz;

− 5.5 − mA

− 3 − mA

2.45 − 3V

3.8 − 4.5 V

th(VDD)

40 − 350 mV

− 1.38 − V

DD

V

DELAY=VDD
DELAY

(discharge) 4 6.8 10 mA

=10nF − 10 − ms

−− 10 µA

VOH=5V

−− 0.4 V

IOL=2mA

−− −10 µA

VOL=0V

VDD− 1 −−V

IOH= −2mA

V

Crystal oscillator; note 2
f

XTAL

f

ext

crystal frequency 2 − 16 MHz
frequency of external signal

applied on pin XTAL1

1998 Mar 20 22

0 − 16 MHz

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Step-up converter

f

INT

V

step-up

Low impedance supply (pin LIS)

V

LIS

I

LIS

Reset output to the card (pin RST)

V

o(RST)

I

o(RST)

V

OL

V

OH

t

r

t

f

Clock output to the card (pin CLK)

V

o(CLK)

I

o(CLK)

V

OL

V

OH

t

r

t

f

f

clk

δ duty cycle C

internal oscillation frequency 2 − 3 MHz
voltage on pin S5 5 V card − 6.5 − V

3 V card − 4.5 − V

voltage on pin LIS 0 − V

DD

V

current at pin LIS −− 7 µA

output voltage when inactive or when LIS

is used; I

o(RST)

=1mA

output current when inactive and pin

−0.3 − +0.4 V

−− −1mA

grounded
LOW-level output voltage IOL= 200 µA −0.25 − +0.4 V
HIGH-level output voltage IOH≤−200 µA

5 V card 4 − V
3 V card 2.4 − V

+ 0.3 V

CC

+ 0.3 V

CC

rise time CL=30pF −− 1 µs
fall time CL=30pF −− 1 µs

output voltage when inactive or when LIS

is used; I

o(CLK)

=1mA

output current when inactive and pin

−0.3 − +0.4 V

−− −1mA

grounded
LOW-level output voltage IOL= 200 µA −0.25 − +0.4 V
HIGH-level output voltage IOH≤−200 µAV

− 0.5 − VCC+ 0.25 V

CC

rise time CL=30pF −− 15 ns
fall time CL=30pF −− 15 ns
clock frequency 1 MHz idle configuration 1 − 1.5 MHz

low operating speed −− 2 MHz

middle operating speed −− 4 MHz

high operating speed −− 8 MHz

=30pF 45 − 55 %

L

1998 Mar 20 23

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Card supply voltage (pin VCC)

V

o(VCC)

I

o(VCC)

card supply output voltage when inactive and when LIS

card supply output current when inactive and pin

SR slew rate on V

(rise and fall)

Data line (pin I/O)

V

o(I/O)

I

o(I/O)

V

OL

V

OH

V

IL

V

IH

t

r

t

f

output voltage when inactive or when LIS

output current when inactive and pin

LOW-level output voltage I/O configured as output;

HIGH-level output voltage I/O configured as output;

LOW-level input voltage I/O configured as input;

HIGH-level input voltage I/O configured as input;

rise time CL=30pF −− 1 µs
fall time CL=30pF −− 1 µs

Protections

I

CC(sd)

shutdown current at pin V

CC

−0.3 − +0.4 V

is used; I

o(VCC)

=1mA

when active; 5 V card

no load 4.85 5.05 5.25 V
static load 4.75 5.0 5.25 V
dynamic loads on 200 nF

4.5 − 5.4 V

capacitor

when active; 3 V card

no load 2.9 3.03 3.15 V
static load 2.79 3 3.21 V
dynamic loads on 200 nF

2.75 − 3.25 V

capacitor

−− −1mA

grounded

when active −− 20 mA

limited −− note1 mA

maximum load capacitor

0.04 0.1 0.16 V/µs
250 nF (including typical
200 nF decoupling)

−0.3 − +0.4 V
is used; I

o(I/O)

=1mA

−− −1mA
grounded

−0.25 − +0.3 V
IOL=1mA

0.8V

− VCC+ 0.25 V

CC

IOH≤ 100 µA

0 − 0.5 V

IIL=1mA

0.6V

CC

− V

CC

IIL= 100 µA

CC

− 00/30/60;

− mA

note 1

V

1998 Mar 20 24

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing

t

act

t

de

t

3(start)

t

5(end)

Auxiliary outputs (AUX1 and AUX2)

V

OL

V

OH

Output ports from extension (K0 to K5)

V

OL

V

OH

Card presence input (pin PRES)

V

IL

V

IH

I

IH

Notes

1. See Table 3 for mask options.

2. The crystal oscillator is the same as option 3 of the P80CL51.

activation sequence duration −− 225 µs
deactivation sequence

−− 150 µs

duration
start of the window for

−− 130 µs

sending clock to the card
end of the window for sending

140 −−µs

clock to the card

LOW-level output voltage IOL=5mA −− 0.4 V
HIGH-level output voltage IOH= −5mA VDD− 1 −−V

LOW-level output voltage IOL=2mA −− 0.4 V
HIGH-level output voltage IOH= −2mA VDD− 1 −−V

LOW-level input voltage IIL= −1mA −− 0.6 V
HIGH-level input voltage IIH= 100 µA 0.7V

−−V

DD

HIGH-level input current VIH= 5 V 0.2 − 3 µA

1998 Mar 20 25

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1998 Mar 20 26

KEYBOARD

5 V

(analog)

100 nF

+5 V (analog)

1615141312111098765432

1

100 nF

APPLICATION INFORMATION

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

controller

MMI-EN

+5 V (logic)

MMI-CLK

MMI-REQ

from

system

RESET

RX

TX

LIS

LED2

LED1

R7

1.5 Ω

1.5 Ω
R8

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

32

333435363738394041424344454647

TDA8005AG

Fig.11 Possible GSM application.

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

48

4.7
nF

handbook, full pagewidth

47 nF

4.7
nF

100

nF

+5 V (logic)

100

kΩ

NC8
NC7
NC6
NC5
C1
C2
C3
C4

K1
K2

NC1
NC2
NC3
NC4

C5
C6
C7
C8

CARD READ UNIT

C702

MGL339

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1998 Mar 20 27

KEYBOARD

ndbook, full pagewidth

V

DD

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

4.7
nF

47 nF

1

48

100 nF

64
63
62
61
60

47 nF

59
58
57
56
55
54
53
52
51
50
49

47
nF

3 V

100
nF

C8
C7
C6
C5
NC1
NC2
NC3
NC4

CARD READ UNIT

K1
K2

C4
C3
C2

C1
NC5
NC6
NC7
NC8

LM01

MGL340

100 nF

1615141312111098765432

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

32

333435363738394041424344454647

33
pF

7.15
MHz

DD

LED1

LED2

R6

R7

V

TDA8005AG

33
pF

R/W

AS E D7 D6 D5 D4 D3 D2 D1 D8

DISPLAY DRIVER

AND DISPLAY

Fig.12 Possible stand-alone application.

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

Mask options

Table 3 TDA8005A option choice form

FUNCTION DESCRIPTION OPTION

P00
P01
P02
P03
P04 RSTIN 3 S
P05 START 3 S
P06 STROBE 3 S
P07 ENABLE 3 S
P10 OFF 2 S
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24 DATA 1 S
P25 R/
P26 REG1 3 S
P27 REG0 3 S
P30
P31
P32 INT 1 S
P33
P34
P35 AUX1 3 S
P36 AUX2 3 S
P37

W3S

Table 4 Description of used options; note 1

OPTION DESCRIPTION

1 standard I/O
2 open-drain I/O
3 push-pull output
S set to HIGH state
R set to LOW state

Note

1. Example: option 1 S indicates standard I/O, set to
HIGH state at power-on.

1998 Mar 20 28

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

Table 5 Analog options

FEATURES OPTIONS

Step-up doubler tripler
Supervisor 2.3 V 3 V 4.5 V
I/O low high impedance
I/O pull-up 10 kΩ 20 kΩ 30 kΩ
R-CLK 0 100 Ω 150 Ω 200 Ω
R-RST 0 80 Ω 130 Ω 180 Ω
ALARM active HIGH active LOW
PRES active HIGH active LOW
IC protection no limitation 30 mA limitation 60 mA limitation

1998 Mar 20 29

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

PACKAGE OUTLINES

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

c

y

X

A

48 33

49

64

1

pin 1 index

16

Z

32

E

e

H

E

E

w M

b

p

17

A

2

A

A

1

detail X

SOT314-2

(A )

3

θ

L

p

L

Z

e

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE
VERSION

SOT314-2

A

A1A2A3bpcE

max.

0.20

0.05

1.45

0.25

1.35

IEC JEDEC EIAJ

1.60

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

w M

b

p

D

H

D

0.27

0.18

0.17

0.12

D

(1)

(1) (1)(1)

D

10.1

10.1

9.9

9.9

REFERENCES

v M

B

v M

0 2.5 5 mm

scale

eH

12.15

0.5

11.85

1998 Mar 20 30

A

B

E

12.15

11.85

LL

p

0.75

0.45

0.12 0.11.0 0.2

EUROPEAN

PROJECTION

H

D

Z

D

1.45

1.05

Zywv θ

E

1.45

1.05

o

7

o

0

ISSUE DATE

95-12-19
97-08-01

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

pin 1 index

44

1

22

Z

E

e

H

E

E

w M

b

p

12

11

A

2

A

A

1

detail X

SOT307-2

(A )

3

θ

L

p

L

w M

b

e

p

D

H

D

Z

D

B

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

0.25

0.40

0.20

0.25

0.14

UNIT A1A2A3bpcE

(1)

(1) (1)(1)

D

10.1

9.9

eH

10.1

9.9

12.9

0.8 1.3

12.3

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT307-2

1998 Mar 20 31

v M

H

v M

D

A

B

E

12.9

12.3

LL

p

0.95

0.55

0.15 0.10.15

EUROPEAN

PROJECTION

Z

D

1.2

0.8

Zywv θ

E

1.2

0.8

o

10

o

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all LQFP and
QFP packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

If wave soldering cannot be avoided, for LQFP and
QFP packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Wave soldering

Wave soldering is not recommended for LQFP and QFP
packages. This is because of the likelihood of solder
bridging due to closely-spaced leads and the possibility of
incomplete solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all LQFP and
QFP packages with a pitch (e) equal or less than

0.5 mm.

1998 Mar 20 32

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Mar 20 33

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

NOTES

1998 Mar 20 34

Philips Semiconductors Preliminary specification

Low-power (3 V/5 V) smart card coupler TDA8005A

NOTES

1998 Mar 20 35

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 435102/1200/01/pp36 Date of release: 1998 Mar 20 Document order number: 9397 750 02512