Datasheet TDA8004T-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1997 Nov 21
File under Integrated Circuits, IC02

1999 Dec 30

INTEGRATED CIRCUITS

TDA8004T

IC card interface

1999 Dec 30 2

Philips Semiconductors Product specification

IC card interface TDA8004T

FEATURES

• 3 or 5 V supply for the IC (GND and VDD)

• Step-up converter for VCC generation (separately

powered with a 5 V ±10% supply, V

DDP

and PGND)

• 3 specific protected half duplex bidirectional buffered
I/O lines (C4, C7 and C8)

• VCC regulation 5 V ±5% on 2 × 100 nF or 1 × 100 nF
and 1 × 220 nF multilayer ceramic capacitors with low
ESR, ICC< 65 mA at 4.5 V < V

DDP

< 6.5 V, current
spikes of 40 nAs up to 20 MHz, withcontrolled rise and
fall times, filtered overload detection approximately
90 mA)

• Thermal and short-circuit protections on all card
contacts

• Automatic activation and deactivation sequences
(initiated by software or by hardware in the event of a
short-circuit, card take-off, overheating or supply
drop-out)

• Enhanced ESD protection on card side (>6 kV)

• 26 MHz integrated crystal oscillator

• Clock generation for the card up to 20 MHz (divided by

1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals)

• Non-inverted control of RST via pin RSTIN

• ISO 7816, GSM11.11 and EMV (payment systems)

compatibility

• Supply supervisor for spikes killing during power-on and
power-off

• One multiplexed status signal OFF.

APPLICATIONS

• IC card readers for banking

• Electronic payment

• Identification

• Pay TV.

GENERAL DESCRIPTION

The TDA8004T is a complete low cost analog interface for
asynchronous smart cards. It can be placed betw the card
andthe microcontroller with very few external components
to perform all supply protection and control functions.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8004T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

1999 Dec 30 3

Philips Semiconductors Product specification

IC card interface TDA8004T

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

supply voltage 2.7 − 6.5 V

V

DDP

step-up supply voltage 4.5 5 6.5 V

I

DD

supply current inactive mode; VDD= 3.3 V;

f

XTAL

=10MHz

−−1.2 mA

active mode; V

DD

= 3.3 V;

f

XTAL

= 10 MHz; no load

−−1.5 mA

I

DDP

step-up supply current inactive mode; V

DDP

=5V;

f

XTAL

=10MHz

−−0.1 mA

active mode; V

DDP

=5V;

f

XTAL

= 10 MHz; no load

−−18 mA

Card supply

V

CC

card supply voltage including
ripple

DC ICC < 65 mA 4.75 − 5.25 V
AC current spikes of 40 nAs 4.65 − 5.25 V

V

i(ripple)(p-p)

ripple voltage on V

CC

(peak-to-peak value)

20 kHz ≤f 200 MHz −−350 mV

I

CC

 card supply current VCC from 0 to 5 V −−65 mA

General

f

CLK

card clock frequency 0 − 20 MHz

t

de

deactivation cycle duration 60 80 100 µs

P

tot

continuous total power dissipation T

amb

= −25 to +85 °C −−0.56 W

T

amb

ambient temperature −25 − +85 °C

1999 Dec 30 4

Philips Semiconductors Product specification

IC card interface TDA8004T

BLOCK DIAGRAM

handbook, full pagewidth

MGM175

100 nF

100 nF

100 nF

100 nF

100

nF

100

nF

I/O

TRANSCEIVER

I/O

TRANSCEIVER

I/O

TRANSCEIVER

THERMAL

PROTECTION

V

CC

GENERATOR

RST

BUFFER

CLOCK

BUFFER

SEQUENCER

CLOCK

CIRCUITRY

OSCILLATOR

HORSEQ

INTERNAL OSCILLATOR

2.5 MHz

STEP-UP CONVERTER

INTERNAL

REFERENCE

VOLTAGE SENSE

SUPPLY

EN2

PV

CC

EN5

EN4

EN3

CLK

EN1 CLKUP

ALARM

V

ref

21

V

DD

6

V

DDP

75

S1 S2

8

VUP

4

PGND

17

V

CC

16

14

RST

CGND

PRES

10

9

PRES

15

CLK

13

12

11

AUX1

AUX2

I/O

22

18
n.c.

GND

26

28

27

I/OUC

AUX2UC

AUX1UC

25

24

2

1

3

19

20

23

XTAL2

XTAL1

CLKDIV2

CLKDIV1

RFU1

CMDVCC

RSTIN

OFF

TDA8004T

Fig.1 Block diagram.

All capacitors are mandatory.

1999 Dec 30 5

Philips Semiconductors Product specification

IC card interface TDA8004T

PINNING

SYMBOL PIN I/O DESCRIPTION

CLKDIV1 1 I control with CLKDIV2 for choosing CLK frequency
CLKDIV2 2 I control with CLKDIV1 for choosing CLK frequency
RFU1 3 I reserved for future use (to be connected to V

DD

or microcontroller I/O; active HIGH)
PGND 4 supply power ground for step-up converter
S2 5 I/O capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ

must be connected between pins S1 and S2)

V

DDP

6 supply power supply voltage for step-up converter

S1 7 I/O capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ

must be connected between pins S1 and S2)

VUP 8 I/O output of step-up converter (a 100 nF capacitor with ESR < 100 mΩ must be

connected to PGND)

PRES 9 I card presence contact input (active LOW); if PRES orPRES is true, then the card is

considered as present

PRES 10 I card presence contact input (active HIGH); if PRES or

PRES is true, then the card is

considered as present

I/O 11 I/O data line to and from card (C7) (internal 10 kΩ pull-up resistor connected to V

CC

)

AUX2 12 I/O auxiliary line to and from card (C8) (internal 10 kΩ pull-up resistor connected to V

CC

)

AUX1 13 I/O auxiliary line to and from card (C4) (internal 10 kΩ pull-up resistor connected to V

CC

)
CGND 14 supply ground for card signals
CLK 15 O clock to card (C3)
RST 16 O card reset (C2)
V

CC

17 O Supply for card (C1); decouple to CGND with 2 × 100 nF or 1 × 100 nF and 1 × 220 nF

capacitors with ESR < 100 mΩ (with 220 nF, the noise margin on VCC will be higher).
n.c. 18 − not connected
CMDVCC 19 I start activation sequence input from microcontroller (active LOW)
RSTIN 20 I card reset input from microcontroller (active HIGH)
V

DD

21 supply supply voltage
GND 22 supply ground
OFF 23 O NMOS interrupt to microcontroller (active LOW) with 20 kΩ internal pull-up resistor

connected to VDD (refer section “Fault detection”)
XTAL1 24 I crystal connection or input for external clock
XTAL2 25 O crystal connection (leave open if an external clock source is used)
I/OUC 26 I/O microcontroller data I/O line (internal 10 kΩ pull-up resistor connected to V

DD

)

AUX1UC 27 I/O auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to

V

DD

)

AUX2UC 28 I/O auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to

V

DD

)

1999 Dec 30 6

Philips Semiconductors Product specification

IC card interface TDA8004T

FUNCTIONAL DESCRIPTION

Throughout this document, it is assumed that the reader is
familiar with ISO 7816 norm terminology.

Power supply

The supply pins for the IC are VDD and GND. VDD should
be in the range from 2.7 to 6.5 V. All interface signals with
the system controller are referenced to VDD; so, be sure
the supply voltage of the system controller is also VDD. All
card contacts remain inactive during powering up or
powering down. The sequencer is not activated until V

DD

reaches V

th2+Vhys(th2)

(see Fig.3). When VDDfalls below

V

th2

, an automatic deactivation of the contacts is

performed.
For generating a 5 V ±5% VCC supply to the card, an

integrated voltage doubler is incorporated. This step-up
converter should be separately supplied by V

DDP

and
PGND (from 4.5 to 6.5 V). Due to large transient currents,
the 2 × 100 nF capacitors of the step-up converter should
have an ESR less than 100 mΩ and be located as near as
possible to the IC.

The supply voltages VDD and V

DDP

may be applied to

the IC in any time sequence.
If a voltage between 7 and 9 V is available within the

application, this voltage may be tied to pin VUP, thus
blocking the step-up converter. In this case, V

DDP

must be
tiedtoVDDandthecapacitorbetweenpinsS1 and S2may
be omitted.

Voltage supervisor

This block surveys the VDD supply. A defined reset pulse
of approximately 10 ms (tW) is used internally for
maintainingthe IC in the inactive modeduringpoweringup
or powering down of VDD (see Fig.3).

As long as VDD is less than V

th2+Vhys(th2)

, the IC will
remaininactivewhateverthelevelsonthecommandlines.
This also lasts for the duration of tWafter VDDhas reached
a level higher than V

th2+Vhys(th2)

.

The system controller should not try to start an activation
during this time.

When VDDfalls below V

th2

, a deactivation sequence of the

contacts is performed.

handbook, halfpage

CLKDIV1
CLKDIV2

RFU1

PGND

S2

V

DDP

S1

VUP

PRES
PRES

I/O
AUX2
AUX1

CGND

AUX2UC
AUX1UC
I/OUC
XTAL2

OFF
GND

XTAL1

V

DD

RSTIN

CMDVCC
n.c.
V

CC

RST
CLK

1
2
3
4
5
6
7
8

9
10
11
12
13

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

TDA8004T

MGM174

Fig.2 Pin configuration.

1999 Dec 30 7

Philips Semiconductors Product specification

IC card interface TDA8004T

handbook, full pagewidth

MGM176

V

DD

t

W

t

W

V

th2

+ V

hys(th2)

V

th2

ALARM

(internal signal)

Fig.3 ALARM as a function of VDD (tW= 10 ms).

Clock circuitry

The clock signal (CLK) to the card is either derived from a
clock signal input on pin XTAL1 or from a crystal up to
26 MHz connected between pins XTAL1 and XTAL2.

The frequency may be chosen at
f

XTAL

,1⁄2f

XTAL

,1⁄4f

XTAL

or1⁄8f

XTAL

via pins CLKDIV1 and

CLKDIV2.
The frequency change is synchronous, which means that

during transition, no pulse is shorter than 45% of the
smallest period and that the first and last clock pulse
around the change has the correct width.

In the case of f

XTAL

, the duty factors are dependent on the

signal at XTAL1.
In order to reach a 45% to 55% duty factor on pin CLK the

input signal on XTAL1 should have a duty factor of
48% to 52% and transition times of less than 5% of the
input signal period.

If a crystal is used with f

XTAL

, the duty factor on pin CLK
may be 45% to 55% depending on the layout and on the
crystal characteristics and frequency.

Intheothercases,itisguaranteedbetween45% and 55%
of the period.

Thecrystaloscillatorrunsassoon as the IC is powered up.
If the crystal oscillator is used, or if the clock pulse on
XTAL1 is permanent, then the clock pulse will be applied
to the card according to the timing diagram of the
activation sequence (see Fig.5).

If the signal applied to XTAL1 is controlled by the system
controller, then the clock pulse will be applied to the card
when the system controller will send it (after completion of
the activation sequence).

Table 1 Clock circuitry definition

CLKDIV1 CLKDIV2 CLK

00

1

⁄

8

f

XTAL

01

1

⁄

4

f

XTAL

11

1

⁄

2

f

XTAL

10f

XTAL

1999 Dec 30 8

Philips Semiconductors Product specification

IC card interface TDA8004T

I/O circuitry

The three data lines I/O, AUX1 and AUX2 are identical.
The Idle state is realized by both lines (I/O and I/OUC)

being pulled HIGH via a 10 kΩ resistor (I/O to VCC and
I/OUC to VDD).

I/O is referenced to VCC and I/OUC to VDD, thus allowing
operation with VCC≠ VDD.

The first side on which a falling edge occurs becomes the
master.Ananti-latchcircuitdisablesthe detection of falling
edges on the other line, which becomes a slave.

After a time delay t

d(edge)

(approximately 200 ns), the
N transistor on the slave side is turned on, thus
transmitting the logic 0 present on the master side.

Whenthemastersidereturnstologic 1, the P transistor on
theslavesideisturnedon during the time delayt

d(edge)

and

then both sides return to their Idle states.
This active pull-up feature ensures fast LOW-to-HIGH

transitions; it is able to deliver more than 1 mA up to an
output voltage of 0.9VCCon a 80 pF load. At the end of the
active pull-up pulse, the output voltage only depends on
the internal pull-up resistor and on the load current (see
Fig.4).

The maximum frequency on these lines is 1 MHz.

Inactive state

Afterpower-onreset,the circuit enters the inactive state. A
minimumnumber of circuits are active while waiting forthe
microcontroller to start a session.

• All card contacts are inactive (approximately 200 Ω to
GND)

• I/OUC, AUX1UC and AUX2UC are high impedance
(10 kΩ pull-up resistor connected to VDD)

• Voltage generators are stopped

• XTAL oscillator is running

• Voltage supervisor is active.

Activation sequence

Afterpower-on and after the internal pulse width delay, the
system controller may check the presence of the card with
the signal OFF (OFF = HIGH while CMDVCC is HIGH
means that the card is present; OFF = LOW while
CMDVCC is HIGH means that no card is present).

If the card is in the reader (which is the case if PRES or
PRES is true), the system controller may start a card
session by pulling CMDVCC LOW.

The following sequence then occurs (see Fig.5):

• CMDVCC is pulled LOW (t0)

• The voltage doubler is started (t1~t0)

• VCC rises from 0 to 5 V with a controlled slope

(t2=t1+1⁄23T) (I/O, AUX1 and AUX2 follow VCC with a
slight delay)

• I/O, AUX1 and AUX2 are enabled (t3=t1+ 4T)

• CLK is applied to the C3 contact (t4)

• RST is enabled (t5=t1+ 7T).

In the timing informations above and below, T is 64 times
the period of the internal oscillator, about 25 µs.

The clock may be applied to the card in the following way:

• Set RSTIN HIGH before setting CMDVCC LOW and
reset it LOW between t3and t5; CLK will start at this
moment. RST will remain LOW until t5, where RST is
enabledto be the copy of RSTIN. After t5,RSTIN has no
further action on CLK. This is to allow a precise count of
CLK pulses before toggling RST.

If this feature is not needed, then CMDVCC may be set
LOWwithRSTINLOW.Inthiscase,CLKwillstart at t3and
after t5,RSTINmaybesetHIGHinordertoget the Answer
To Request (ATR) from the card.

handbook, halfpage

0

(2)

(1)

6

4

2

0

20 40

t (ns)

V

o

(V)

12

8

4

0

I

o

(mA)

60

FCE270

Fig.4 I/O, AUX1, and AUX2 output voltage and

current as a function of time during a
LOW-to-HIGH transition.

(1) Current.
(2) Voltage.

1999 Dec 30 9

Philips Semiconductors Product specification

IC card interface TDA8004T

handbook, full pagewidth

MGM177

CMDVCC

VUP

V

CC

I/O

CLK

RSTIN

RST

high - Z

t

act

t

0

t

1

t

2

t

3

t

4

t

5

ATR

OSC_INT/64

(T

≈

25 µs)

Fig.5 Activation sequence.

Active state

When the activation sequence is completed, the
TDA8004T will be in the active state. Data is exchanged
between the card and the microcontroller via the I/O lines.
The TDA8004T is designed for cards without VPP (this is
the voltage required to program or erase the internal
non-volatile memory).

Depending on the layout and on the application test
conditions (for example with an additional 1 pF cross
capacitance between C2/C3 and C2/C7) it is possible
that C2 is polluted with high frequency noise from C3. In
this case, it will be necessary to connect a 220 pF
capacitance between C2 and CGND.

It is recommended to:

1. Keep track C3 as far as possible from other tracks

2. Have straight connection between CGND and C5 (the
2 capacitorson C1 should be connected tothisground
track)

3. Avoid ground loops between CGND, PGND and GND

4. Decouple V

DDP

and VDD separately; if the 2 supplies
are the same in the application, then they should be
connected in star on the main track.

With all these layout precautions, noise should be at an
acceptable level and jitter on C3 should be less than
100 ps. Refer to

Application Note AN97036

for specimen

layouts

Deactivation sequence

When a session is completed, the microcontroller sets the
CMDVCCline to the HIGH state. The circuit then executes
an automatic deactivation sequence by counting the
sequencer back and ends in the inactive state (see Fig.6):

• RST goes LOW → (t11=t10)

• CLK is stopped LOW → (t12=t11+1⁄2T)

• I/O, AUX1 and AUX2 are output into high-impedance

state → (t13=t11+ T); 10 kΩ pull-up resistor connected
to V

CC

• VCC falls to zero → (t14=t11+1⁄23T); the deactivation
sequence is completed when VCC reaches its inactive
state

• VUPfalls to zero → (t15=t11+ 5T)and all card contacts
become low-impedance to GND; I/OUC, AUX1UC and
AUX2UC remain pulled up to VDD via a 10 kΩ resistor.

1999 Dec 30 10

Philips Semiconductors Product specification

IC card interface TDA8004T

handbook, full pagewidth

MGE739

CMDVCC

VUP

OSC_INT/64

(T

≈ 25 µs)

V

CC

I/O

CLK

RST

high - Z

t

de

t

10

t

11

t

12

t

13

t

14

t

15

Fig.6 Deactivation sequence.

Fault detection

The following fault conditions are monitored by the circuit:

• Short-circuit or high current on V

CC

• Removing card during transaction

• VDD dropping

• Overheating.

There are two different cases (see Fig.7):

1. CMDVCCHIGH:(outside a card session) then, OFF is
LOW if the card is not in the reader and HIGH if the
card is in the reader. A supply voltage drop on VDD is
detected by the supply supervisor, generates an
internal power-on reset pulse, but don’t act upon OFF.
The card is not powered-up, so no short-circuit or
overheating is detected.

2. CMDVCCLOW:(withinacard session) then, OFFfalls
LOW if the card is extracted, or if a short-circuit has
occurred on VCC, or if the temperature on the IC has
become too high. As soon as the fault is detected, an
emergency deactivation is automatically performed
(see Fig.8).

When the system controller sets CMDVCC back to
HIGH, it may sense OFF again in order to distinguish
between a hardware problem or a card extraction. If a
supply voltage drop on VDDis detected whilst the card
is activated, then an emergency deactivation will be
performed, but OFF remains HIGH.

Depending on the type of card presence switch within the
connector (normally closed or normally open) and on the
mechanical characteristics of the switch, a bouncing may
occur on presence signals at card insertion or withdrawal.

There is no debounce feature in the device, so the
softwarehastotakeitintoaccount;however,thedetection
of card take off during active phase, which initiates an
automatic deactivation sequence is done on the first
true/false transition on PRES or PRES and is memorized
until the system controller sets CMDVCC HIGH.

So, the software may take some time waiting for presence
switches to be stabilized without causing any delay on the
necessary fast and normalized deactivation sequence.

1999 Dec 30 11

Philips Semiconductors Product specification

IC card interface TDA8004T

handbook, full pagewidth

FCE271

OFF

CMDVCC

PRES

V

CC

Deactivation caused by
cards withdrawal

Deactivation caused by
short circuit

Fig.7 Behaviour of OFF, CMDVCC, PRES and VCC.

handbook, full pagewidth

MGE740

I/O

CLK

RST

high - Z

t

de

OFF

PRES

V

CC

t

10

t

11

t

12

t

13

t

14

OSC_INT/64

(T

≈

25 µs)

Fig.8 Emergency deactivation sequence.

VCC regulator

V

CC

buffer is able to deliver up to 65 mA continuously. It has an internal overload detection at approximately 90 mA.

Thisdetectionisinternally filtered, allowing spurious current pulses up to 200 mA to be drawn by the card without causing
a deactivation (the average current value must stay below 65 mA).

For VCC accuracy reasons, a 100 nF capacitor with ESR < 100 mΩ should be tied to CGND near pin 17 and a 100 nF
(or better 220 nF) with same ESR should be tied to CGND near C1 contact.

1999 Dec 30 12

Philips Semiconductors Product specification

IC card interface TDA8004T

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); notes 1 and 2.

Notes

1. All card contacts are protected against any short with any other card contact.

2. Stress beyond these levels may cause permanent damage to the device. This is a stress rating only and functional
operation of the device under this condition is not implied.

HANDLING

Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.
Method 3015 (HBM; 1500 Ω; 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD, V

DDP

supply voltage −0.3 +7 V

V

n1

voltage on pins: XTAL1, XTAL2, RFU1, RSTIN,
AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2,
CMDVCC and OFF

−0.3 +7 V

V

n2

voltage on card contact pins PRES, PRES, I/O, RST,
AUX1, AUX2 and CLK

−0.3 +7 V

V

n3

voltage on pin VUP, S1 and S2 − 9V

T

stg

IC storage temperature −55 +125 °C

P

tot

continuous total power dissipation T

amb

= −25 to +85 °C − 0.56 W

T

j

junction temperature − 150 °C

V

es1

electrostatic voltage on pins: I/O, RST, VCC, AUX1,
CLK, AUX2, PRES and PRES

−6+6kV

V

es2

electrostatic voltage on all other pins −2+2kV

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 70 K/W

1999 Dec 30 13

Philips Semiconductors Product specification

IC card interface TDA8004T

CHARACTERISTICS

VDD= 3.3 V; V

DDP

=5V; T

amb

=25°C; all parameters remain within limits but are only statistically tested for the

temperature range; f

XTAL

= 10 MHz; unless otherwise specified; all currents flowing into the IC are positive. When a

parameter is specified as a function of V

DD

or VCC, it means their actual value at the moment of measurement.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Temperature

T

amb

ambient temperature −25 − +85 °C

Supplies

V

DD

supply voltage 2.7 − 6.5 V

V

DDP

supply voltage for the voltage
doubler

4.5 5 6.5 V

V

o(VUP)

output voltage on pin VUP from
step-up converter

− 5.5 − V

V

i(VUP)

input voltage to be applied on VUP
in order to block the step-up
converter

7 − 9V

I

DD

supply current inactive mode −−1.2 mA

active mode; f

CLK=fXTAL

;

CL=30pF

−−1.5 mA

I

P

supply current for the step-up
converter

inactive mode −−0.1 mA
active mode; f

CLK=fXTAL

;

CL=30pF

I

CC

=0 −−18 mA

I

CC

=65mA −−150 mA

V

th2

threshold voltage on VDD (falling) 2.2 − 2.4 V

V

hys(th2)

hysteresis on V

th2

50 − 150 mV

t

W

width of the internal ALARM pulse 6 − 20 ms

Card supply voltage (VCC); note 1
V

CC

output voltage including ripple inactive mode −0.1 − +0.1 V

inactive mode; I

CC

=1mA −0.1 − +0.4 V

active mode;
I

CC

 <65mADC

4.75 − 5.25 V

active mode; single current
pulse of −100 mA; 2 µs

4.65 − 5.25 V

active mode; current pulses
of 40 nAs with
I

CC

 < 200 mA; t < 400 ns;

4.65 − 5.25 V

V

i(ripple)(p-p)

peak-to-peak ripple voltage on V

CC

20 kHz ≤f 200 MHz −−350 mV

I

CC

 output current from 0 to 5 V; −−65 mA

V

CC

short-circuit to ground −−120 mA

SR slew rate up and down 0.11 0.17 0.22 V/µs

1999 Dec 30 14

Philips Semiconductors Product specification

IC card interface TDA8004T

Crystal connections (XTAL1 and XTAL2)

C

ext

external capacitance on
XTAL1 and XTAL2

depending on specification
of crystal or resonator used

−−15 pF

f

i(XTAL)

crystal input frequency 2 − 26 MHz

V

IH(XTAL)

HIGH-level input voltage on XTAL1 0.8V

DD

− VDD+ 0.2 V

V

IL(XTAL)

LOW-level input voltage on XTAL1 −0.3 − 0.2V

DD

V

Data lines (I/O, I/OUC, AUX1, AUX2, AUXUC1 and AUXUC2)

GENERAL
t

d(edge)

delay between falling edge on pins
I/OUC and I/O (or I/O and I/OUC)
and width of active pull-up pulse

− 200 − ns

f

I/O(max)

maximum frequency on data lines −−1 MHz

C

i

input capacitance on data lines −−10 pF
DATA LINES; I/O, AUX1 AND AUX2 (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VCC)
V

OH

HIGH-level output voltage on data

lines

no DC load 0.9V

CC

− VCC+ 0.1 V

I

OH

= −40 µA 0.75V

CC

− VCC+ 0.1 V

V

OL

LOW-level output voltage on data

lines

I=1mA −−300 mV

V

IH

HIGH-level input voltage on data

lines

1.8 − VCC+ 0.3 V

V

IL

LOW-level input voltage on data

lines

−0.3 − +0.8 V

V

inactive

voltage on data lines outside a

session

no load −−0.1 V
I

I/O

=1mA −−0.3 V

I

edge

current from data lines when active

pull-up active

VOH= 0.9VCC; Co=80pF −1 −− mA

I

LIH

 input leakage current HIGH on data

lines

VIH=V

CC

−−10 µA

I

IL

LOW-level input current on data

lines

VIL=0V −−600 µA

R

pu(int)

internal pull-up resistance between

data lines and V

CC

91113kΩ

t

r

, t

f

input transition times on data lines from V

IL(max)

to V

IH(min)

−−1µs

output transition times on data lines C

o

= 80 pF, no DC load;
10% to 90% of VCC (see
Fig.9)

−−0.1 µs

DATA LINES; I/OUC, AUX1UC AND AUX2UC (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VDD)
V

OH

HIGH-level output voltage on data
lines

no DC load 0.9V

DD

− VDD+ 0.2 V

I

OH

= −40 µA 0.75V

DD

− VDD+ 0.2

V

OL

LOW-level output voltage on data
lines

IOL=1mA −−300 mV

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Dec 30 15

Philips Semiconductors Product specification

IC card interface TDA8004T

V

IH

HIGH-level input voltage on data
lines

0.7V

DD

− VDD+ 0.3 V

V

IL

LOW-level input voltage on data
lines

0 − 0.3V

DD

V

I

LIH

 input leakage current HIGH on data

lines

VIH=V

DD

−−10 µA

I

IL

LOW-level input on data lines VIL=0V −−600 µA

R

pu(int)

internal pull-up resistance between
data lines and V

DD

91113kΩ

t

r

,t

f

input transition times on data lines from V

IL(max)

to V

IH(min)

−−1µs

output transition times on data lines C

o

= 30 pF; 10% to 90%
of VDD (see Fig.9)

−−0.1 µs

Internal oscillator

f

osc(int)

frequency of internal oscillator 2.2 − 3.2 MHz

Reset output to the card (RST)

V

o(inactive)

output voltage in inactive mode no load 0 − 0.1 V

I

o

=1mA 0 − 0.3 V

t

d(RSTIN-RST)

delay between pins RSTIN and RST RST enabled −−2µs

V

OL

LOW-level output voltage IOL= 200 µA0−0.3 V

V

OH

HIGH-level output voltage IOH= −200 µA 0.9V

CC

− V

CC

V

t

r,tf

rise and fall times Co= 250 pF −−0.1 µs

Clock output to the card (CLK)

V

o(inactive)

output voltage in inactive mode no load 0 − 0.1 V

I

o

=1mA 0 − 0.3 V

V

OL

LOW-level output voltage IOL= 200 µA0−0.3 V

V

OH

HIGH-level output voltage IOH= −200 µA 0.9V

CC

− V

CC

V

t

r,tf

rise and fall times CL= 35 pF; note 2 −−8ns

δ duty factor (except for f

XTAL

)C

L

= 35 pF; note 2 45 − 55 %

SR slew rate (rise and fall) C

L

= 35 pF 0.2 −− V/ns

Logic inputs (CLKDIV1, CLKDIV2, PRES, PRES, CMDVCC, RSTIN and RFU1); note 3
V

IL

LOW-level input voltage −−0.3V

DD

V

V

IH

HIGH-level input voltage 0.7V

DD

−− V

I

LIL

 input leakage current LOW 0 < VIL<V

DD

−−5µA

I

LIH

 input leakage current HIGH 0 < VIH<V

DD

−−5µA

OFF output (OFF is an open drain with an internal 20 kΩ pull-up resistor to VDD)

V

OL

LOW-level output voltage IOL=2mA −−0.4 V

V

OH

HIGH-level output voltage IOH= −15 µA 0.75V

DD

−− V

Protections

T

sd

shut-down temperature − 135 −°C

I

CC(sd)

shut-down current at V

CC

−−110 mA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Dec 30 16

Philips Semiconductors Product specification

IC card interface TDA8004T

Notes

1. To meet these specifications VCCshould be decoupled to CGND using two ceramic multilayer capacitors of low ESR
with values of either 100 nF or one 100 nF and one 220 nF.

2. The transition times and duty factor definitions are shown in Fig.9;

3. PRES and CMDVCC are active LOW; RSTIN and PRES are active HIGH; for CLKDIV1 and CLKDIV2 see Table 1;
RFU1 must be tied HIGH.

APPLICATION INFORMATION

VDD for the TDA8004T must be the same as for the microcontroller and CLKDIV1, CLKDIV2, RSTIN, PRES, PRES,
AUX1UC, AUX2UC, I/OUC, RFU1, CMDVCC and OFF should be referenced to VDDand XTAL1 also when driven by an
external clock.

For optimum layout be sure that there is enough ground area around the TDA8004T and the connector. Place the
TDA8004T very near to the connector, ideally under the connector, and decouple VDD and V

DDP

properly.

Refer to

AN97036

for further application information for proper implementation of the TDA8004T.

Timing

t

act

activation sequence duration see Fig.5 − 180 220 µs

t

de

deactivation sequence duration see Fig.6 60 80 100 µs

t

3

start of the window for sending CLK
to the card

see Fig.5 −−130 µs

t

5

end of the window for sending CLK
to the card

see Fig.5 140 −− µs

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

δ

t

1

t1t2+()

------------------- -

=

handbook, full pagewidth

MGM178

10%

90% 90%

10%

t

r

t

f

t

1

t

2

V

CC

or V

DD

(V

OH

+ VOL)/2

0

Fig.9 Definition of output transition times.

1999 Dec 30 17

Philips Semiconductors Product specification

IC card interface TDA8004T

100 nF

100 nF

100 nF

AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
GND

V

DD
RSTIN
CMDVCC
n.c.

V

CC
RST
CLK

CLKDIV1
CLKDIV2

RFU1

GNDP

V

DDP

S1

S2

VUP
PRES
PRES

I/O
AUX2
AUX1

CGND

28
27
26
25
24
23
22
21
20
19
18
17
16

1
2
3
4
5
6
7
8
9
10
11
12
13
14 15

TDA8004T

C5
C6
C7
C8

C1
C2
C3
C4

CARD READ

(Normally closed type)

K1
K2

+3.3 V

+3.3 V

+3.3 V

+3.3 V

3.3 V POWERED
MICROCONTROLLER

33 pF

100 nF

100 nF

220 nF

+5 V

10 µF

100 k

These capacitors
must be placed
near the IC and
have LOW ESR
(Less than 1 cm)

Straight and short
connextions between
CGND, C5 and capacitors
GND. (No loop)

One 100nF
with LOW ESR
near pin 17,

One 100nF or 220nF
with LOW ESR
near C1 contact
(less than 1cm)

C3 should be routed
far from C2, C7, C4 and C8
and, better, surrounded
with ground tracks.

MGM179

More application information on
application report AN97036

VDD for the TDA8004 must be the same as controller
supply voltage, CLKDIV1, CLKDIV2, RSTIN, PRES,
PRES, AUXUC, I/OUC, AUX2UC, RFU1, CMDVCC,
OFF should be referenced to VDD, and also XTAL1
if driven by external clock.

Fig.10 Application diagram.

1999 Dec 30 18

Philips Semiconductors Product specification

IC card interface TDA8004T

PACKAGE OUTLINE

UNIT

A

max.

A

1

A

2

A3b

p

cD

(1)E(1) (1)

eHELLpQ

Z

ywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

2.65

0.30

0.10

2.45

2.25

0.49

0.36

0.32

0.23

18.1

17.7

7.6

7.4

1.27

10.65

10.00

1.1

1.0

0.9

0.4

8
0

o
o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT136-1

X

14

28

w

M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

c

L

v

M

A

e

15

1

(A )

3

A

y

0.25

075E06 MS-013

pin 1 index

0.10

0.012

0.004

0.096

0.089

0.019

0.014

0.013

0.009

0.71

0.69

0.30

0.29

0.050

1.4

0.055

0.419

0.394

0.043

0.039

0.035

0.016

0.01

0.25

0.01

0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO28: plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

97-05-22

99-12-27

1999 Dec 30 19

Philips Semiconductors Product specification

IC card interface TDA8004T

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesaverybriefinsighttoacomplex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboardbyscreenprinting,stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Dec 30 20

Philips Semiconductors Product specification

IC card interface TDA8004T

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1999 Dec 30 21

Philips Semiconductors Product specification

IC card interface TDA8004T

NOTES

1999 Dec 30 22

Philips Semiconductors Product specification

IC card interface TDA8004T

NOTES

1999 Dec 30 23

Philips Semiconductors Product specification

IC card interface TDA8004T

NOTES

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

68

Philips Semiconductors – a w orldwide compan y

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Printed in The Netherlands 545004/25/02/pp24 Date of release: 1999 Dec 30 Document order number: 9397 750 06034