Datasheet TDA8004AT Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8004AT

IC card interface

Preliminary specification
File under Integrated Circuits, IC02

2000 Feb 29

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

FEATURES

• 3 or 5 V supply for the IC (GND and VDD)

• Step-up converter for VCC generation (separately

powered with a 5 V ±10% supply, V

and PGND)

DDP

• 3 specificprotectedhalfduplexbidirectionalbufferedI/O
lines (C4, C7 and C8)

• VCC regulation (5 or 3 V ±5% on 2 × 100 nF or
1 × 100 nF and 1 × 220 nF multilayer ceramic
capacitors with low ESR, ICC< 65 mA at

4.5V<V

< 6.5 V, current spikes of 40 nAs up to

DDP

20 MHz, with controlled rise and fall times, filtered
overload detection approximately 90 mA)

• Thermal and short-circuit protections on all card
contacts

• Automatic activation and deactivation sequences
(initiated by software or by hardware in the event of a
short-circuit, card take-off, overheating or supply
drop-out)

• Enhanced ESD protection on card side (>6 kV)

• 26 MHz integrated crystal oscillator

• Clock generation for the card up to 20 MHz (divided by

1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals)
with synchronous frequency changes

• Non-inverted control of RST via pin RSTIN

• ISO 7816, GSM11.11 and EMV (payment systems)

compatibility

• Supply supervisor for spikes killing during power-on
and power-off

• One multiplexed status signal OFF.

APPLICATIONS

• IC card readers for banking

• Electronic payment

• Identification

• Pay TV.

GENERAL DESCRIPTION

The TDA8004AT is a complete low cost analog interface
for asynchronous 3 or 5 V smart cards. It can be placed
between the card and the microcontroller with very few
external components to perform all supply protection and
control functions.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8004AT SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

2000 Feb 29 2

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

V

DDP

I

DD

I

DDP

Card supply

V

CC

V

i(ripple)(p-p)

 card supply current VCC from 0 to 5 or to 3 V −−65 mA

I

CC

General

f

CLK

t

de

P

tot

T

amb

supply voltage 2.7 − 6.5 V
step-up supply voltage 4.5 5 6.5 V
supply current inactive mode; VDD= 3.3 V;

f

=10MHz

XTAL

active mode; V
f

= 10 MHz; no load

XTAL

step-up supply current inactive mode; V

f

=10MHz

XTAL

active mode; V
f

= 10 MHz; no load

XTAL

card supply voltage including
ripple

5 V card

DC I

 < 65 mA 4.75 − 5.25 V

CC

DD

DDP

DDP

= 3.3 V;

=5V;

=5V;

−−1.2 mA

−−1.5 mA

−−0.1 mA

−−18 mA

AC current spikes of 40 nAs 4.65 − 5.25 V

3 V card

DC I

 < 65 mA 2.85 − 3.15 V

CC

AC current spikes of 40 nAs 2.76 − 3.20 V

ripple voltage on V

CC

from 20 kHz to 200 MHz −−350 mV

(peak-to-peak value)

card clock frequency 0 − 20 MHz
deactivation cycle duration 60 80 100 µs
continuous total power dissipation T

= −25 to +85 °C −−0.56 W

amb

ambient temperature −25 − +85 °C

2000 Feb 29 3

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

BLOCK DIAGRAM

handbook, full pagewidth

OFF

RSTIN

CMDVCC

5V/3V

CLKDIV1
CLKDIV2

V

DD

23
20
19

3

1

2

100 nF

21

CIRCUITRY

SUPPLY

INTERNAL

REFERENCE

VOLTAGE SENSE

HORSEQ

CLOCK

CLK

V

ALARM

V

DDP

ref

SEQUENCER

100 nF

6

STEP-UP CONVERTER

INTERNAL OSCILLATOR

EN1 CLKUP

100 nF

S1 S2
75

2.5 MHz

EN2

PV

CC

GENERATOR

EN5

EN4

V

CC

RST

BUFFER

CLOCK

BUFFER

PGND

4

VUP

8

100 nF

V

17

CC

100

100

nF

14

CGND

16

15

10

9

nF

RST

CLK

PRES
PRES

XTAL1

XTAL2

AUX1UC

24

OSCILLATOR

25

27

EN3

PROTECTION

TDA8004AT

AUX2UC

I/OUC

All capacitors are mandatory.

28

26

22

GND

18
n.c.

Fig.1 Block diagram.

2000 Feb 29 4

THERMAL

TRANSCEIVER

TRANSCEIVER

TRANSCEIVER

I/O

I/O

I/O

13

12

11

FCE658

AUX1

AUX2

I/O

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

PINNING

SYMBOL PIN I/O DESCRIPTION

CLKDIV1 1 I control with CLKDIV2 for choosing CLK frequency
CLKDIV2 2 I control with CLKDIV1 for choosing CLK frequency
5V/

3V 3 I control signal for selecting VCC= 5 V (HIGH) or VCC= 3 V (LOW)
PGND 4 supply power ground for step-up converter
S2 5 I/O capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ

must be connected between pins S1 and S2)

V

DDP

S1 7 I/O capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ

VUP 8 O output of step-up converter (a 100 nF capacitor with ESR < 100 mΩ must be connected

PRES 9 I card presence contact input (active LOW); if PRES or PRES is true, then the card is

PRES 10 I card presence contact input (active HIGH); if PRES or

I/O 11 I/O data line to and from card (C7) (internal 10 kΩ pull-up resistor connected to V
AUX2 12 I/O auxiliary line to and from card (C8) (internal 10 kΩ pull-up resistor connected to V
AUX1 13 I/O auxiliary line to and from card (C4) (internal 10 kΩ pull-up resistor connected to V
CGND 14 supply ground for card signals
CLK 15 O clock to card (C3)
RST 16 O card reset (C2)
V

CC

n.c. 18 − not connected
CMDVCC 19 I start activation sequence input from microcontroller (active LOW)
RSTIN 20 I card reset input from microcontroller (active HIGH)
V

DD

GND 22 supply ground
OFF 23 O NMOS interrupt to microcontroller (active LOW) with 20 kΩ internal pull-up resistor

XTAL1 24 I crystal connection or input for external clock
XTAL2 25 O crystal connection (leave open circuit if an external clock source is used)
I/OUC 26 I/O microcontroller data I/O line (internal 10 kΩ pull-up resistor connected to V
AUX1UC 27 I/O auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to

AUX2UC 28 I/O auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to

6 supply power supply voltage for step-up converter

must be connected between pins S1 and S2)

to PGND)

considered as present

PRES is true, then the card is

considered as present

)

CC

CC
CC

17 O supply for card (C1); decouple to CGND with 2 × 100 nF or 1 × 100nF and 1 × 220 nF

capacitors with ESR < 100 mΩ (with 220 nF, the noise margin on VCC will be higher)

21 supply supply voltage

connected to VDD(refer section “Fault detection”)

)

DD

V

)

DD

V

)

DD

)
)

2000 Feb 29 5

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

FUNCTIONAL DESCRIPTION

Throughout this document,it is assumed that thereader is
familiar with ISO7816 norm terminology.

Power supply

The supply pins for the IC are VDDand GND. VDD should
be in the range from 2.7 to 6.5 V. All interface signals with
the microcontroller are referenced to VDD; therefore be
sure the supply voltage of the microcontroller is also at
VDD. All card contacts remain inactive during powering up

handbook, halfpage

CLKDIV1
CLKDIV2

5V/3V

PGND

S2

V

DDP

S1

VUP

PRES
PRES

I/O
AUX2
AUX1

CGND

1
2
3
4
5
6
7

TDA8004AT

8

9
10
11
12
13

FCE659

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1

OFF
GND
V

DD

RSTIN

CMDVCC
n.c.
V

CC

RST
CLK

or powering down. The sequencer is not activated until
VDD reaches V
below V

, an automatic deactivation of the contacts is

th2

th2+Vhys(th2)

(see Fig.3). When VDD falls

performed.
For generating a 5 V ±5% VCC supply to the card, an

integrated voltage doubler is incorporated. This step-up
converter should be separately supplied by V

DDP

and
PGND (from 4.5 to 6.5 V). Due to large transient currents,
the 2 × 100 nF capacitors of the step-up converter should
have an ESR of less than 100 mΩ,and belocated as near
as possible to the IC.

The supply voltages VDDand V

may be applied to the

DDP

IC in any time sequence.
If a voltage between 7 and 9 V is available within the

application, this voltage may be tied to pin VUP, thus
blocking the step-up converter. In this case, V

DDP

must be
tiedto VDDandthe capacitor between pinsS1 and S2may
be omitted.

Voltage supervisor

This block surveys the VDD supply. A defined reset pulse
of approximately 10 ms (tW) is used internally for
maintainingthe IC in the inactivemodeduring powering up
or powering down of VDD (see Fig.3)).

Fig.2 Pin configuration.

2000 Feb 29 6

As long as VDD is less than V

th2+Vhys(th2)

, the IC will
remaininactive whatever the levelson the command lines.
This also lasts for the duration of tWafter VDDhas reached
a level higher than V

th2+Vhys(th2)

.

The system controller should not attempt to start an
activation sequence during this time.

When VDDfalls below V

, a deactivation sequence of the

th2

contacts is performed.

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

handbook, full pagewidth

V

+ V

th2

V

DD

hys(th2)

V

th2

t

W

ALARM

(internal signal)

Fig.3 Alarm as a function of VDD (tW= 10 ms).

Clock circuitry

The clock signal (CLK) to the card is either derived from a
clock signal input on pin XTAL1 or from a crystal up to
26 MHz connected between pins XTAL1 and XTAL2.

The frequency may be chosen at f
or1⁄8f

via pins CLKDIV1 and CLKDIV2.

XTAL

XTAL

,1⁄2f

XTAL

,1⁄4f

XTAL

The frequency change is synchronous, which means that
during transition, no pulse is shorter than 45% of the
smallest period and that the first and last clock pulse
around the change has the correct width.

In the case of f

, the duty factors are dependent on the

XTAL

signal at XTAL1.

t

W

FCE660

Inthe other cases, itisguaranteed between 45% and 55%
of the period.

The crystal oscillator runs as soon as the IC is
powered-up. If the crystal oscillator is used, or if the clock
pulse on XTAL1 is permanent, then the clock pulse will be
applied to the card according to the timing diagram of the
activation sequence (see Fig.5).

If the signal applied to XTAL1 is controlled by the
microcontroller, then the clock pulse will be applied to the
card by the microcontroller after completion of the
activation sequence.

Table 1 Clock circuitry definition

In order to reach a 45% to 55% duty factor on pin CLK the
input signal on XTAL1 should have a duty factor of
48% to 52% and transition times of less than 5% of the
input signal period.

If a crystal is used with f

, the duty factor on pin CLK

XTAL

may be 45% to 55% depending on the layout and on the
crystal characteristics and frequency.

2000 Feb 29 7

CLKDIV1 CLKDIV2 CLK

00
01
11
10f

1

⁄

f

8

XTAL

1

⁄

f

4

XTAL

1

⁄

f

2

XTAL

XTAL

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

I/O circuitry

The three data lines I/O, AUX1 and AUX2 are identical.
TheIdle state isrealized by data linesI/O and I/OUC being

pulled HIGH via a 10 kΩ resistor (I/O to VCCand I/OUC to
VDD).

I/O is referenced to VCC, and I/OUC to VDD, thus allowing
operation with VCC≠ VDD.

The first line on which a falling edge occurs becomes the
master.Ananti-latchcircuit disables the detection of falling
edges on the other line, which then becomes the slave.

After a time delay t

(approximately 200 ns), the

d(edge)

N transistoron the slave line isturnedon, thus transmitting
the logic 0 present on the master line.

When the masterline returns to logic 1, the P transistor on
the slave line is turned on during the time delay t

d(edge)

and

then both lines return to their Idle states.
This active pull-up feature ensures fast LOW-to-HIGH

transitions; it is able to deliver more than 1 mA up to an
output voltage of 0.9VCCon a 80 pF load. Atthe end of the
active pull-up pulse, the output voltage only depends on
the internal pull-up resistor, and on the load current
(see Fig.4).

The maximum frequency on these lines is 1 MHz.

FCE661

12

(mA)

8

I

o

V
(V)

6

o

4

handbook, halfpage

(1)

(2)

Inactive state

After power-on reset, the circuit enters the inactive state.
A minimum number of circuits are active while waiting for
the microcontroller to start a session.

• All card contacts are inactive (approximately 200 Ω

to GND)

• I/OUC, AUX1UC and AUX2UC are high impedance

(10 kΩ pull-up resistor connected to VDD)

• Voltage generators are stopped

• XTAL oscillator is running

• Voltage supervisor is active.

Activation sequence

After power-on and, after the internal pulse width delay,
the microcontroller may check the presence of the card
withthe signal OFF(OFF = HIGHwhile CMDVCC isHIGH
means that the card is present; OFF = LOW while
CMDVCC is HIGH means that no card is present).

If the card is in the reader (which is the case if PRES or
PRESis true), the microcontrollermay start a cardsession
by pulling CMDVCC LOW.

The following sequence then occurs (see Fig.5):

• CMDVCC is pulled LOW (t0)

• The voltage doubler is started (t1~t0)

• VCC rises from 0 to 5 or 3V with a controlled slope

(t2=t1+1⁄23T) (I/O, AUX1 and AUX2 follow VCC with a
slight delay); T is 64 times the period of the internal
oscillator, approximately 25µs

• I/O, AUX1 and AUX2 are enabled (t3=t1+ 4T)

• CLK is applied to the C3 contact (t4)

• RST is enabled (t5=t1+ 7T).

2

0

0

(1) Current.
(2) Voltage.

20 40

t (ns)

4

0

60

Fig.4 I/O, AUX1 and AUX2 output voltage and

current as a function of time during a
LOW-to-HIGH transition.

2000 Feb 29 8

The clock may be applied to the card in the following way:

Set RSTIN HIGH before setting CMDVCC LOW, and
reset it LOW between t3and t5; CLK will start at this
moment. RST will remain LOW until t5, where RST is
enabledto be thecopy of RSTIN. After t5,RSTIN has no
further action on CLK. This is to allow a precise count of
CLK pulses before toggling RST.

If this feature is not needed, then CMDVCC may be set
LOW with RSTIN LOW. In this case, CLK will start at t3,
and after t5, RSTIN may be set HIGH in order to get the
Answer To Request (ATR) from the card.

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

t

handbook, full pagewidth

OSC_INT/64

CMDVCC

act

VUP

V

CC

I/O

CLK

RSTIN

RST

t

1

t

2

t

0

Fig.5 Activation sequence.

Active state

When the activation sequence is completed, the
TDA8004AT will be in the active state. Data is exchanged
between the card and the microcontroller via the I/O lines.
The TDA8004AT is designed for cards without VPP(this is
the voltage required to program or erase the internal
non-volatile memory).

Depending on the layout and on the application test
conditions (for example with an additional 1 pF cross
capacitance between C2/C3 and C2/C7) it is possible that
C2 is polluted with high frequency noise from C3. In this
case, it will be necessary to connect a 220 pF capacitor
between C2 and CGND

.

It is recommended to:

1. Keep track C3 as far as possible from other tracks

2. Have straight connection between CGND and C5(the
2 capacitorson C1 should beconnectedtothis ground
track)

3. Avoid ground loops between CGND, PGND and GND

4. Decouple V

and VDD separately; if the 2 supplies

DDP

are the same in the application, then they should be
connected in star on the main track.

ATR

high - Z

t

t

3

4

t

5

FCE662

With all these layout precautions, noise should be at an
acceptable level, and jitter on C3 should be less than
100 ps. Refer to

Application Note AN97036

for specimen

layouts.

Deactivation sequence

When a session is completed, the microcontroller sets the
CMDVCCline to theHIGH state. Thecircuit then executes
an automatic deactivation sequence by counting the
sequencer back and ends in the inactive state (see Fig.6):

• RST goes LOW → (t11=t10)

• CLK is stopped LOW → (t12=t11+1⁄2T); where T is
approximately 25 µs

• I/O, AUX1 and AUX2 are output into high-impedance

state → (t13=t11+ T) (10 kΩ pull-up resistor connected
to VCC)

• VCC falls to zero → (t14=t11+1⁄23T); the deactivation
sequence is completed when VCC reaches its inactive
state

• VUPfalls to zero → (t15=t11+ 5T)and all cardcontacts
become low-impedance to GND; I/OUC, AUX1UC and
AUX2UC remain pulled up to VDD via a 10 kΩ resistor.

2000 Feb 29 9

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

t

t

14

high - Z

de

t

15

handbook, full pagewidth

OSC_INT/64

CMDVCC

VUP

V

CC

I/O

CLK

t

10

t

13

t

12

RST

t

11

Fig.6 Deactivation sequence.

Fault detection

The following fault conditions are monitored by the circuit:

• Short-circuit or high current on V

CC

• Removing card during transaction

• VDD dropping

• Overheating.

There are two different cases ((see Fig.7))

1. CMDVCCHIGH: (outside acardsession) then, OFFis
LOW if the card is not in the reader, and HIGH if the
card is in the reader. A supply voltage drop on VDD is
detected by the supply supervisor which generates an
internal power-on reset pulse, but does not act upon
OFF.Thecardis not powered-up, so no short-circuitor
overheating is detected.

2. CMDVCCLOW:(withinacard session) then, OFF falls
LOW if the card is extracted, or if a short-circuit has
occurred on VCC, or if the temperature on the IC has
become too high. As soon as the fault is detected, an
emergency deactivation is automatically performed
(see Fig.8).

FCE663

When the system controller sets CMDVCC back to
HIGH, it may sense OFF again in order to distinguish
between a hardware problem or a card extraction. If a
supply voltage drop on VDDis detected whilst the card
is activated, then an emergency deactivation will be
performed, but OFF remains HIGH.

Depending on the type of card presence switch within the
connector (normally closed or normally open), and on the
mechanical characteristics of the switch, a bouncing may
occur on presence signals at card insertion or withdrawal.

There is no debounce feature in the device, so the
softwarehas to take it intoaccount;however, the detection
of card take off during active phase, which initiates an
automatic deactivation sequence is done on the first True/
Falsetransition on PRESor PRES, andis memorized until
the system controller sets CMDVCC HIGH.

So, the software may take some time waiting for presence
switches to be stabilized without causing any delay on the
necessary fast and normalized deactivation sequence.

2000 Feb 29 10

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

handbook, full pagewidth

PRES

OFF

CMDVCC

V

CC

Deactivation caused by
cards withdrawal

Deactivation caused by
short circuit

FCE665

Fig.7 Behaviour of OFF, CMDVCC, PRES and VCC (see also application note AN97036 for software decision

algorithm on OFF signal).

t

handbook, full pagewidth

OSC_INT/64

OFF

PRES

t

10

de

t

14

V

CC

I/O

CLK

RST

t

t

13

t

12

11

high - Z

FCE664

Fig.8 Emergency deactivation sequence.

VCC regulator

The V

buffer is able to deliver up to 65 mA continuously (at 5V if 5V/3V is HIGH or 3 V if 5V/3V is LOW). It has an

CC

internal overload detection at approximately 90 mA.
Thisdetection is internally filtered,allowing spurious current pulsesup to 200 mA tobe drawn by thecard without causing

a deactivation (the average current value must stay below 65 mA).
For VCCaccuracy reasons, a 100 nF capacitor with an ESR < 100 mΩ should be tied to CGND near pin 17, and a 100 nF

(or better 220 nF) with same ESR should be tied to CGND near to the C1 contact.

2000 Feb 29 11

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); notes 1 and 2.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD, V
V

n1

V

n2

V

n3

T

stg

P

tot

T

j

V

es1

V

es2

supply voltage −0.3 +7 V

DDP

voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN,

−0.3 +7 V
AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2,
CMDVCC and OFF

voltage on card contact pins PRES, PRES, I/O, RST,

−0.3 +7 V
AUX1, AUX2 and CLK

voltage on pins VUP, S1 and S2 − +9 V
IC storage temperature −55 +125 °C
continuous total power dissipation T

= −25 to +85 °C − 0.56 W

amb

junction temperature − 150 °C
electrostatic voltage on pins I/O, RST, VCC, AUX1,

−6+6kV
CLK, AUX2, PRES and PRES

electrostatic voltage on all other pins −2+2kV

Notes

1. All card contacts are protected against any short with any other card contact.

2. Stress beyond these levels may cause permanent damage to the device. This is a stress rating only and functional
operation of the device under this condition is not implied.

HANDLING

Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.
Method 3015 (HBM; 1500 Ω; 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground.

THERMAL RESISTANCE

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 70 K/W

2000 Feb 29 12

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

CHARACTERISTICS

VDD= 3.3 V; V
temperature range; f
parameter is specified as a function of V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Temperature

T

amb

Supplies

V

DD

V

DDP

V

o(VUP)

V

i(VUP)

I

DD

I

P

V

th2

V

hys(th2)

t

W

Card supply voltage; note 1
V

CC

V

i(ripple)(p-p)

DDP

=5V; T

XTAL

=25°C; all parameters remain within limits but are only statistically tested for the

amb

= 10 MHz; unless otherwise specified; all currents flowing into the IC are positive. When a

or VCC it means their actual value at the moment of measurement.

DD

ambient temperature −25 − +85 °C

supply voltage 2.7 − 6.5 V
supply voltage for the voltage

4.5 5 6.5 V

doubler
output voltage on pin VUP from

− 5.5 − V

step-up converter
input voltage to be applied on VUP

7 − 9V
in order to block the step-up
converter

supply current inactive mode −−1.2 mA

active mode; f

CLK

= f

XTAL

;

−−1.5 mA

CL=30pF

supply current for the step-up
converter

inactive mode −−0.1 mA
active mode; I

f

CLK=fXTAL

I

=0 −−18 mA

CC

=65mA −−150 mA

I

CC

=0;

CC

; CL=30pF

threshold voltage on VDD (falling) 2.2 − 2.4 V
hysteresis on V

th2

50 − 150 mV
width of the internal ALARM pulse 6 − 20 ms

output voltage including ripple inactive mode − 0.1 − +0.1 V

inactive mode; I

=1mA −0.1 − +0.4 V

CC

active mode;

I

 <65mADC

CC

5 V card 4.65 − 5.25 V
3 V card 2.85 − 3.15 V

active mode; single current
pulse of −100 mA; 2 µs

5 V card 4.65 − 5.25 V
3 V card 2.76 − 3.15 V

active mode; current pulses
of 40 nAs with

I

 < 200 mA; t < 400 ns

CC

5 V card 4.65 − 5.25 V
3 V card 2.76 − 3.20 V

peak-to-peak ripple voltage on V

from 20 kHz to 200 MHz −−350 mV

CC

2000 Feb 29 13

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ICC output current from 0 to 5 or 3 V −−65 mA

V

short-circuit to ground −−120 mA

CC

SR slew rate up and down 0.11 0.17 0.22 V/µs

Crystal connections (pins XTAL1 and XTAL2)

C

ext

f

i(XTAL)

V

IH(XTAL)

V

IL(XTAL)

Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC)

GENERAL
t

d(edge)

f

I/O(max)

C

i

DATA LINES; PINS I/O, AUX1 AND AUX2 (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VCC)
V

OH

V

OL

V

IH

V

IL

V

inactive

I

edge

 input leakage current HIGH on data

I

LIH

I

IL

t

t(DI)

t

t(DO)

DATA LINES; PINS I/OUC, AUX1UC AND AUX2UC (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VDD)
V

OH

V

OL

external capacitors on pins
XTAL1 and XTAL2

depending on specification
of crystal or resonator used

−−15 pF

crystal input frequency 2 − 26 MHz
HIGH-level input voltage on XTAL1 0.8V
LOW-level input voltage on XTAL1 −0.3 − +0.2V

delay between falling edge on pins

− 200 − ns

− VDD+ 0.2 V

DD

DD

V

I/OUC and I/O (or I/O and I/OUC)
and width of active pull-up pulse

maximum frequency on data lines −−1 MHz
input capacitance on data lines −−10 pF

HIGH-level output voltage on data
lines

LOW-level output voltage on data

no DC load 0.9V
I

= −40 µA 0.75V

OH

− VCC+ 0.1 V

CC

− VCC+ 0.1 V

CC

I=1mA −−300 mV

lines
HIGH-level input voltage on data

1.8 − VCC+ 0.3 V

lines
LOW-level input voltage on data

−0.3 − +0.8 V

lines
voltage on data lines outside a

session
current from data lines when active

no load −−0.1 V
I

=1mA −−0.3 V

I/O

VOH= 0.9VCC; Co=80pF −1 −− mA

pull-up active

VIH=V

CC

−−10 µA

lines
LOW-level input current on data

VIL=0V −−600 µA

lines
input transition times on data lines from VIL max to VIHmin −−1µs
output transition times on data lines Co= 80 pF, no DC load;

10% to 90% from 0 to V

−−0.1 µs

CC

(see Fig.9)

HIGH-level output voltage on data
lines

LOW-level output voltage on data

no DC load 0.9V
I

= −40 µA 0.75V

OH

− VDD+ 0.2 V

DD

− VDD+ 0.2 V

DD

I=1 mA −−300 mV

lines

2000 Feb 29 14

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

IH

V

IL

 input leakage current HIGH on data

I

LIH

I

IL

R

pu(int)

t

t(DI)

t

t(DO)

Internal oscillator

f

osc(int)

Reset output to the card (pin RST)

V

o(inactive)

t

d(RSTIN-RST)

V

OL

V

OH

t

r,tf

Clock output to the card (pin CLK)

V

o(inactive)

V

OL

V

OH

t

, t

r

f

δ duty factor (except for f
SR slew rate (rise and fall) C

Logic inputs (pins CLKDIV, CLKDIV2,PRES, PRES, CMDVCC, RSTIN and 5V/3V); note 3
V

IL

V

IH

I

 input leakage current LOW 0 < VIL<V

LIL

I

 input leakage current HIGH 0 < VIH<V

LIH

OFF output (pin OFF is an open-drain with an internal 20 kΩ pull-up resistor to VDD)

HIGH-level input voltage on data

0.7V

− VDD+ 0.3 V

DD

lines
LOW-level input voltage on data

0 − 0.3V

DD

V

lines

VIH=V

DD

−−10 µA

lines
LOW-level input on data lines VIL=0V −−600 µA
internal pull-up resistance between

data lines and V

DD

91113kΩ

input transition times on data lines from VIL max to VIH min −−1µs
output transition times on data lines Co= 30 pF; 10% to 90%

−−0.1 µs

from 0 to VDD (see Fig.9)

frequency of internal oscillator 2.2 − 3.2 MHz

output voltage in inactive mode no load 0 − 0.1 V

I

=1mA 0 − 0.3 V

o

delay between pins RSTIN and RST RST enabled −−2µs
LOW-level output voltage IOL= 200 µA0−0.3 V
HIGH-level output voltage IOH= −200 µA 0.9V

CC

− V

CC

V

rise and fall times Co= 250 pF −−0.1 µs

output voltage in inactive mode no load 0 − 0.1 V

I

=1mA 0 − 0.3 V

o

LOW-level output voltage IOL= 200 µA0−0.3 V
HIGH-level output voltage IOH= −200 µA 0.9V

CC

− V

CC

V

rise and fall times CL= 35 pF; note 2 −−8ns

)C

XTAL

LOW-level input voltage −−0.3V
HIGH-level input voltage 0.7V

= 35 pF; note 2 45 − 55 %

L

= 35 pF 0.2 −− V/ns

L

DD

−− V

DD

DD

DD

−−5µA

−−5µA

V

V

OL

V

OH

LOW-level output voltage IOL=2mA −−0.4 V
HIGH-level output voltage IOH= −15 µA 0.75V

Protections

T

sd

I

CC(sd)

shut-down temperature − 135 −°C
shut-down current at V

CC

2000 Feb 29 15

−− V

DD

−−110 mA

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing

t

act

t

de

t

3

t

5

Notes

1. To meet these specifications VCCshould be decoupled to CGNDusing two ceramic multilayer capacitors of low ESR
with values of either 100 nF or one 100 nF and one 220 nF.

2. The transition times and duty factor definitions are shown in Fig.9;

3. PRES and CMDCC are active LOW; RSTIN and PRES are active HIGH; for CLKDIV1 and CLKDIV2 see Table 1.

activation sequence duration see Fig.5 − 180 220 µs
deactivation sequence duration see Fig.6 60 80 100 µs
start of the window for sending CLK

see Fig.5 −−130 µs

to the card
end of the window for sending CLK

see Fig.5 140 −− µs

to the card

t

=

1

-------------- ­t1t2+

δ

handbook, full pagewidth

10%

t

f

t

2

t

r

90% 90%

10%

t

1

Fig.9 Definition of output transition times.

V

OH

(V

+ VOL)/2

OH

V

OL

FCE666

2000 Feb 29 16

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

APPLICATION DIAGRAM

handbook, full pagewidth

More application information on
application report AN97036

100 nF

10 µF

+5 V

100 nF

100 nF

These capacitors
must be placed
near the IC and
have LOW ESR
(Less than 1 cm)

+3.3 V

Straight and short
connextions between
CGND, C5 and capacitors
GND. (No loop)

100 k

VDD for the TDA8004 must be the same as controller
supply voltage, CLKDIV1, CLKDIV2, RSTIN, PRES,
PRES, AUXUC, I/OUC, AUX2UC, RFU1, CMDVCC,
OFF should be referenced to VDD, and also XTAL1
if driven by external clock.

100 nF

220 nF

C1
C2
C3
C4

28
27
26

25

24

23
22
21
20
19
18
17
16

AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
GND

V

DD
RSTIN
CMDVCC
n.c.

V

CC
RST
CLK

K1

K2

33 pF

100 nF

One 100nF
with LOW ESR
near pin 17,

One 100nF or 220nF
with LOW ESR
near C1 contact
(less than 1cm)

C3 should be routed
far from C2, C7, C4 and C8
and, better, surrounded
with ground tracks.

CLKDIV1

1

CLKDIV2

2

5V/3V

3

GNDP

4

S2

5

V

DDP

6

S1

7

VUP

8

PRES

9

PRES

10

I/O

11

AUX2

12

AUX1

13

CGND

14 15

(Normally closed type)

TDA8004AT

CARD READ

C5
C6
C7
C8

+3.3 V

+3.3 V

3.3 V POWERED
MICROCONTROLLER

Fig.10 Application diagram.

2000 Feb 29 17

FCE667

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

PACKAGE OUTLINE

SO28: plastic small outline package; 28 leads; body width 7.5 mm

D

c

y

Z

28

pin 1 index

1

e

15

14

w M

b

p

SOT136-1

E

H

E

Q

A

2

A

1

L

p

L

detail X

(A )

A

X

v M

A

A

3

θ

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE
VERSION

SOT136-1

A

max.

2.65

0.10

A

1

0.30

0.10

0.012

0.004

A2A

2.45

2.25

0.096

0.089

IEC JEDEC EIAJ

075E06 MS-013

0.25

0.01

b

3

p

0.49

0.32

0.36

0.23

0.019

0.013

0.014

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

18.1

7.6

7.4

0.30

0.29

1.27

0.050

17.7

0.71

0.69

REFERENCES

2000 Feb 29 18

eHELLpQ

10.65

10.00

0.419

0.394

1.4

0.055

1.1

0.4

0.043

0.016

1.1

1.0

0.043

0.039

PROJECTION

0.25

0.25 0.1

0.01

0.01

EUROPEAN

ywv θ

Z

0.9

0.4

0.035

0.004

0.016

ISSUE DATE

97-05-22

99-12-27

o

8

o

0

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

SOLDERING
Introduction to soldering surface mount packages

Thistextgives a very brief insighttoa complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board byscreen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on four sides, thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) or printed-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2000 Feb 29 19

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm;it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Short-form specification The data in this specification is extracted from a full data sheet with the same type

number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2000 Feb 29 20

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

NOTES

2000 Feb 29 21

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

NOTES

2000 Feb 29 22

Philips Semiconductors Preliminary specification

IC card interface TDA8004AT

NOTES

2000 Feb 29 23

Philips Semiconductors – a w orldwide compan y

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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

69

Printed in The Netherlands 753504/01/pp24 Date of release: 2000 Feb 29 Document order number: 9397 750 06685