Page 1
2 x 75W multifunction dual-bridge power amplifier
Features
■ Multipower bcd technology
■ MOSFET output power stage
■ DMOS power output
■ New high-efficiency (class AB)
■ Single-channel 1Ω driving capability
■ High output power capability 2x28 W/4 Ω @
14.4 V, 1 kHz, 10 % THD
■ Max. output power 2x75 W/2 Ω, 1x150 W/1 Ω
■ Single-channel 1 Ω driving capability
■ 84 W undistorted power
■ Full I
■ Possibility to disable the I
■ Differential inputs
■ Full fault protection
■ DC offset detection
■ Two independent short circuit protections
■ Diagnostic on clipping detector with selectable
■ Clipping detector as diagnostic pin when I
■ Standby/mute pins
■ ESD protection
Table 1. Device summary
2
C bus driving with 4 address possibilities:
– Standby
–Play/mute
– Gain 12/26 dB
– Full digital diagnostic (AC and DC loads)
2
C bus
threshold (2 % / 10 %)
2
bus is disabled
C
TDA7575B
with integrated digital diagnostics
PowerSO36
(slug up)
Description
The TDA7575B is a new MOSFET dual bridge
amplifier specially intended for car radio
applications. Thanks to the DMOS output stage
the TDA7575B has a very low distortion allowing
a clear powerful sound.
Among the features, its superior efficiency
performance coming from the internal exclusive
structure, makes it the most suitable device to
simplify the thermal management in high power
sets.The dissipated output power under average
listening condition is in fact reduced up to 50%
when compared to the level provided by
conventional class AB solutions.
This device is equipped with a full diagnostic array
that communicates the status of each speaker
through the I
possibility of driving loads down to 1Ω paralleling
the outputs into a single channel. It is also
possible to disable the I
TDA7575B by means of the usual standby and
mute pins.
2
C bus. The TDA7575B has also the
Flexiwatt27
2
C and control the
Order code Package Packing
TDA7575B Flexiwatt27 Tube
TDA7575BPD PowerSO36 (slug up) Tube
TDA7575BPDTR PowerSO36 (slug up) Tape and reel
December 2009 Doc ID 14103 Rev 2 1/32
www.st.com
1
Page 2
Contents TDA7575B
Contents
1 Block and pins diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 1 W capability setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6 I2C abilitation setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Diagnostics functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 Turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Permanent diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 Output DC offset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.4 AC diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 Multiple faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6 Faults availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.7 I2C programming/reading sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32 Doc ID 14103 Rev 2
Page 3
TDA7575B List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. DB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Double fault table for turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 14103 Rev 2 3/32
Page 4
List of figures TDA7575B
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Quiescent drain current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Output power vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Output power vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Output power vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. Distortion vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. Distortion vs. output voltage (LD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14. Cross talk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15. Cross talk vs. frequency (LD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16. CMRRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17. Output attenuation vs. supply voltage (vs. dependent muting) . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18. Output attenuation vs. mute pin voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 19. Power dissipation vs. output power (4Ω - SINE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 20. Power dissipation vs. output power (2Ω - SINE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 21. Power dissipation vs. average output power (Audio program simulation, 4Ω) . . . . . . . . . . 14
Figure 22. Power dissipation vs. average output power (Audio program simulation, 2Ω) . . . . . . . . . . 14
Figure 23. ITU R-ARM frequency response, weighting filter for transient pop. . . . . . . . . . . . . . . . . . . 14
Figure 24. Application circuit (TDA7575B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 25. Application circuit (TDA7575BPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 26. Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 27. Timing diagram on the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 28. Timing acknowledge clock pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 29. Turn-on diagnostic: working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. SVR and output behavior - case 1: without turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. SVR and output pin behavior - case 2: with turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. Short circuit detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 33. Load detection thresholds - high gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 34. Load detection thresholds - high gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 35. Restart timing without diagnostic enable (permanent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 36. Restart timing with diagnostic enable (permanent). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 37. Current detection high: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . 27
Figure 38. Current detection low: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . . 27
Figure 39. PowerSO36 (slug up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 29
Figure 40. Flexiwatt27 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 30
4/32 Doc ID 14103 Rev 2
Page 5
TDA7575B Block and pins diagrams
2
1 Block and pins diagrams
Figure 1. Block diagram
V
ADDRESS
A B CLK
DATA VCC CD_OUT
S
I2CBUS
IN1+
IN1-
SHORT CIRCUIT
PROTECTION
IN2+
IN2-
SHORT CIRCUIT
PROTECTION
SVR S_GND
ST-BY/HE 1Ω MUTE
PW_GND TAB
Figure 2. Pins connection diagram (top view)
OUT1+
OUT1+
VCC
VCC
PWGND
PWGND
OUT1-
OUT1-
OUT2-
OUT2-
PWGND
PWGND
VCC
VCC
OUT2+
OUT2+
36
35
34
33
B
32
31
30
29
28
26
25
A
23
22
21
20
19
D01AU1270
PowerSO36 (slug up)
1
2
3
4
5
6
7
8
9
1027
11
12
1324
14
15
16
17
18
TAB
IN1+
IN1-
MUTE
ST_BY
SGND
DATA
CK
N.C.
N.C.
N.C.
N.C.
SVR
CD-OUT
1-OHM
I2C-EN
IN2-
IN2+
CLIP
DETECTOR
D01AU1269
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Flexiwatt27
OUT1+
OUT1-
OUT2+
OUT2-
2
I
C EN
TAB
PWGND
A
OUT2+
N.C.
OUT2-
V
CC
IN2+
IN2-
I2CEN
1Ω
CD_OUT
SVR
CK
DATA
SGND
STT-BY
MUTE
IN1-
IN1+
V
CC
OUT1-
N.C.
OUT1+
B
PWGND
TAB
D03IN151
Doc ID 14103 Rev 2 5/32
Page 6
Electrical specifications TDA7575B
2 Electrical specifications
2.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
T
V
V
V
V
peak
V
CK
DATA
I
O
I
O
P
stg
op
tot
Operating supply voltage 18 V
DC supply voltage 28 V
S
Peak supply voltage (for t = 50 ms) 50 V
CK pin voltage 6 V
Data pin voltage 6 V
Output peak current (not repetitive t = 100 ms) 8 A
Output peak current (repetitive f > 10 Hz) 6 A
Power dissipation T
= 70 °C 86 W
case
, TjStorage and junction temperature -55 to 150 °C
2.2 Thermal data
Table 3. Thermal data
Symbol Parameter PowerSO36 Flexiwatt 27 Unit
R
th j-case
Thermal resistance junction-to-case Max 1 1 °C/W
2.3 Electrical characteristics
VS = 14.4 V; f = 1 kHz; RL = 4 Ω; T
Table 4. Electrical characteristics
= 25 °C unless otherwise specified.
amb
Symbol Parameter Test condition Min. Typ. Max. Unit
Power amplifier
V
Supply voltage range - 8 - 18 V
S
I
Total quiescent drain current - 50 130 200 mA
d
P
o
Output power
Max. power
(1)
THD = 10 %
THD = 1 %; BTL mode
= 2 Ω; THD 10 %
R
L
= 2 Ω; THD 1 %
R
L
= 2 Ω; Max. power
R
L
(1)
35 40 - W
25 28
22
45
50
37
70
75
-W
-W
6/32 Doc ID 14103 Rev 2
Page 7
TDA7575B Electrical specifications
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Single channel configuration
P
o
Output power
(1 Ω pin > 2.5 V); RL = 1 Ω;
THD 3 %
Max. power
(1)
80
14084150
-W
THD Total harmonic distortion
P
= 1-12 W; STD mode
o
HE mode; Po = 1-2 W
HE mode; P
P
= 1-12 W, f = 10 kHz - 0.15 0.5 %
o
R
= 2; HE mode; Po = 3 W - 0.03 0.5 %
L
= 4-8 W
o
0.03
-
0.03
0.1
0.1 %
0.5
Single channel configuration
-0.020.1%
-4060μV
-1525μV
50 60 - dB
C
Cross talk Rg = 600 Ω; Po = 1 W 60 75 - dB
T
R
G
ΔG
G
ΔG
E
E
Input impedance - 60 100 130 kΩ
IN
Voltage gain 1 (default) - 25 26 27 dB
V1
Voltage gain match 1 - -1 0 1 dB
V1
Voltage gain 2 - 11 12 13 dB
V2
Voltage gain match 2 - -1 0 1 dB
V2
Output noise voltage gain 1
IN1
Output noise voltage gain 2
IN2
SVR Supply voltage rejection
(1 Ω pin > 2.5 V); R
= 4-30 W
P
o
R
= 600 Ω; Gv = 26 dB
g
= 1;
L
filter 20 to 22 kHz
R
= 600 Ω; Gv = 12d B
g
filter 20 to 22 kHz
f = 100 Hz to 10 kHz; V
= 600 Ω
R
g
= 1 Vpk;
r
BW Power bandwidth (-3 dB) 100 - - KHz
A
I
A
V
V
CMRR Input CMRR V
V
Standby attenuation - 90 100 - dB
SB
Standby current consumption V
SB
Mute attenuation - 80 90 dB
M
Offset voltage Mute and play -45 0 45 mV
OS
Min. supply mute threshold - 7 7.5 8 V
AM
Maximum common mode input
MC
level
= 0 V - 2 10 μA
st-by
= 1 Vpk-pk; Rg = 0 Ω 56 60 dB
CM
f = 1 kHz - - 1 Vrms
SR Slew rate - 1.5 4 - V/μs
ΔV
During mute on/off output offset
voltage
OS
During standby on/off output
offset voltage
ITU R-ARM weighted
see Figure 23
-10 - +10 mV
-10 - +10 mV
Doc ID 14103 Rev 2 7/32
Page 8
Electrical specifications TDA7575B
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
T
T
V
V
V
V
V
V
V
I
I
V
V
I
I
Turn on delay D2 (IB1) 0 to 1 - 15 40 ms
ON
Turn off delay D2 (IB1) 1 to 0 - 15 40 ms
OFF
Standby pin for standby - 0 - 1.5 V
OFF
Standby pin for standard bridge - 3.5 - 5 V
SB
Standby pin for high-efficiency - 7 - 18 V
HE
Standby pin current 1.5 < V
I
O
Standby pin current V
Mute pin voltage for mute mode - 0 - 1.5 V
m
Mute pin voltage for play mode - 3.5 - 18 V
m
Mute pin current (standby) V
I
m
I
Mute pin current (operative) 0 V < V
m
I2C pin voltage for I2C disabled - 0 - 1.5 V
I2C
I2C pin voltage for I2C enabled - 2.5 - 18 V
I2C
2
CI2C pin current (standby) 0V < I2C EN < 18V, V
2
CI2C pin current (operative) I2C EN <18V, V
1 Ω pin voltage for 2ch mode - 0 - 1.5 V
1Ω
1 Ω pin voltage for 1 Ω mode - 2.5 - 18 V
1Ω
1 Ω pin current (standby) 0 V < 1 Ω <18 V, V
1Ω
1 Ω pin current (operative) 1 Ω < 18 V, V
1Ω
La
< 1.5 V -10 0 10 μA
st-by
= 0 V, V
mute
Low logic level 0 - 1.5 V
< 18 V 7 160 200 μA
st-by/HE
< 1.5V -5 0 5 μA
st-by
mute
< 18 V, V
st-by
> 3.5 V 7 11 15 μA
st-by
> 3.5 V - 65 100 μA
st-by
< 1.5V -5 0 5 μA
stby
>3.5V 7 11 15 μA
< 1.5 V -5 0 5 μA
s-tby
A pin voltage
Ha High logic level 2.5 - 18 V
Ia A pin current (standby) 0V < A < 18V , V
Ia A pin current (operative) A<18V, V
Lb
Low logic level 0 - 1.5 V
st-by
< 1.5 V -5 0 5 μA
stby
> 3.5V 7 11 15 μA
B pin voltage
Hb High logic level 2.5 - 18 V
Ib B pin current (standby) 0 V < B < 18 V, V
Ib B pin current (operative) B < 18 V, V
T
T
I
CDH
I
CDL
Thermal warning - - 150 - °C
W
Thermal protection intervention - - 170 - °C
PI
Clip pin high leakage current CD off, 0 V < VCD < 5.5 V -15 0 15 μA
Clip pin low sink current CD on; VCD < 300 mV 1 mA
st-by
< 1.5 V -5 0 5 μA
s-tby
> 3.5 V 7 11 15 μA
D0 (IB1) = 0 0.8 1.3 2.5 %
CD Clip detect THD level
D0 (IB1) = 1 5 10 15 %
(*) Standby pin high enables I2C bus; Standby pin low puts the device in standby condition. (see “prog” for more details)
8/32 Doc ID 14103 Rev 2
Page 9
TDA7575B Electrical specifications
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Turn-on diagnostics (Power amplifier mode)
Pgnd
Short to GND det. (below this
limit, the output is considered in
short circuit to GND)
Power amplifier in standby
condition
--1.2V
Short to Vs det. (above this
Pvs
limit, the output is considered in
-V
-0.9 - - V
s
short circuit to VS)
Normal operation
Pnop
thresholds.(within these limits,
the output is considered
-1.8-V
-1.5 V
s
without faults).
Lsc Shorted load det. - - - 0.5 Ω
Lop Open load det. - 130 - - Ω
Lnop Normal load det. - 1.5 - 70 Ω
Turn-on diagnostics (Line driver mode)
Short to GND det. (below this
Pgnd
limit, the output is considered in
--1.2V
short circuit to GND)
Short to Vs det. (above this
Pvs
limit, the Output is considered
V
-0.9 - - V
s
in Short Circuit to VS)
Pnop
Normal operation
thresholds.(within these limits,
the output is considered
Power amplifier in standby
1.8 - V
-1.5 V
s
without faults).
Lsc Shorted load det. - - 1.5 Ω
Lop Open load det. 400 - - Ω
Lnop Normal load det. 4.5 - 200 Ω
Permanent diagnostics (Power amplifier mode or line driver mode)
Pgnd
Pvs
Short to GND det. (below this
limit, the output is considered in
short circuit to GND)
Short to Vs det. (above this
limit, the Output is considered
in Short Circuit to VS)
Power amplifier in Mute or Play
condition, one or more short
circuits protection activated
-
--1.2V
Vs -
0.9
--V
Normal operation
Pnop
thresholds.(Within these limits,
the Output is considered
-1.8-V
-1.5 V
s
without faults).
Pow. amp. mode - - 0.5 Ω
Lsc Shorted load det.
Line driver mode - - 1.5 Ω
Doc ID 14103 Rev 2 9/32
Page 10
Electrical specifications TDA7575B
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
V
I
I
I
OLH
I
2
C bus interface
I
f
SCL
V
V
1. Saturated sqare wave output.
Offset detection
O
Normal load current detection VO < (VS - 5)pk IB2 (D0) = 0 500 - - mA
NLH
Normal load current detection VO < (VS - 5)pk IB2 (D0) = 1 250 - - mA
NLL
Open load current detection VO < (VS - 5)pk IB2 (D0) = 0 - - 250 mA
Open load current detection VO < (VS - 5)pk IB2 (D0) =1 - - 125 mA
OLL
Clock frequency - - - 400 kHz
Input low voltage - - - 1.5 V
IL
Input high voltage - 2.3 - - V
IH
Power amplifier in play condition
AC input signals = 0
±1.5 ±2 ±2.5 V
10/32 Doc ID 14103 Rev 2
Page 11
TDA7575B Electrical characteristics curves
3 Electrical characteristics curves
Figure 3. Quiescent drain current vs. supply
Figure 4. Output power vs. supply voltage
voltage
Id (mA)
Id (mA)
160
160
150
150
Vi=0
140
140
130
130
120
120
110
110
100
100
90
90
80
80
70
70
Vi=0
NO LOADS
NO LOADS
8 1012141618
8 1012141618
Vs ( V)
Vs ( V)
Po (W)
Po (W)
80
80
75
75
70
70
65
65
60
60
55
55
50
50
45
45
40
40
35
35
30
30
25
25
20
20
15
15
10
10
RL=4 Ohm
RL=4 Ohm
f=1 KHz
f=1 KHz
5
5
8 9 10 11 12 13 14 15 16 17 18
8 9 10 11 12 13 14 15 16 17 18
Vs ( V)
Vs ( V)
Po-max
Po-max
THD=10%
THD=10%
THD=1%
THD=1%
Figure 5. Output power vs. supply voltage Figure 6. Output power vs. supply voltage
Po (W)
Po (W)
130
130
120
120
110
110
100
100
90
90
80
80
70
70
60
60
50
50
40
40
30
30
20
20
10
10
RL=2 Ohm
RL=2 Ohm
f=1 KHz
f=1 KHz
0
0
8 9 10 11 12 13 14 15 16 17 18
8 9 10 11 12 13 14 15 16 17 18
Vs ( V)
Vs ( V)
Po-max
Po-max
THD=10%
THD=10%
THD=1%
THD=1%
Po (W)
Po (W)
130
130
120
120
110
110
100
100
90
90
80
80
70
70
60
60
50
50
40
40
30
30
20
20
10
10
RL=2 Ohm
RL=2 Ohm
f=1 KHz
f=1 KHz
0
0
8 9 10 11 12 13 14 15 16 17 18
8 9 10 11 12 13 14 15 16 17 18
Vs ( V)
Vs ( V)
Po-max
Po-max
THD=10%
THD=10%
THD=1%
THD=1%
Figure 7. Distortion vs. output power Figure 8. Distortion vs. output power
THD (%)
THD (%)
THD (%)
10
10
HI-EFF mode
HI-EFF mode
Vs=14.4V
Vs=14.4V
RL=4 Ohm
RL=4 Ohm
1
1
f=10 KHz
f=10 KHz
0.1
0.1
f=1 KHz
f=1 KHz
0.01
0.01
0.1 1 10 100
0.1 1 10 100
Po (W)
Po (W)
Doc ID 14103 Rev 2 11/32
THD (%)
10
10
HI-EFF mode
HI-EFF mode
Vs=14.4V
Vs=14.4V
RL=2 Ohm
RL=2 Ohm
1
1
f=10 KHz
f=10 KHz
0.1
0.1
f=1 KHz
f=1 KHz
0.01
0.01
0.1 1 10 100
0.1 1 10 100
Po (W)
Po (W)
Page 12
Electrical characteristics curves TDA7575B
Figure 9. Distortion vs. output power Figure 10. Distortion vs. output power
THD (%)
THD (%)
THD (%)
10
10
STD mode
STD mode
Vs=14.4V
Vs=14.4V
RL=4 Ohm
RL=4 Ohm
1
1
f=10 KHz
f=10 KHz
0.1
0.1
f=1 KHz
0.01
0.01
0.001
0.001
0.1 1 10 100
0.1 1 10 100
f=1 KHz
Po (W)
Po (W)
0.001
0.001
THD (%)
10
10
STD mode
STD mode
Vs=14.4V
Vs=14.4V
RL=2 Ohm
RL=2 Ohm
1
1
f=10 KHz
f=10 KHz
0.1
0.1
f=1 KHz
f=1 KHz
0.01
0.01
0.1 1 10 100
0.1 1 10 100
Po (W)
Po (W)
Figure 11. Distortion vs. output power Figure 12. Distortion vs. frequency
THD (%)
10
10
1
1
THD (%)
THD (%)
STD mode
STD mode
Vs=14.4V
Vs=14.4V
RL=1 Ohm
RL=1 Ohm
f=10 KHz
f=10 KHz
10
10
0.1
0.1
1
1
THD (%)
Vs=14.4V
Vs=14.4V
STD mode
STD mode
1Ω -40W
1Ω -40W
2Ω -24W
2Ω -24W
4Ω -12W
4Ω -12W
0.1
0.1
f=1 KHz
f=1 KHz
0.01
0.01
0.1 1 10 100
0.1 1 10 100
Po (W)
Po (W)
Figure 13. Distortion vs. output voltage
(LD mode)
THD (%)
THD (%)
10
10
LD mode
LD mode
Vs=14.4V
Vs=14.4V
RL=100 Ohm
RL=100 Ohm
1
1
0.1
0.1
f=10 KHz
f=10 KHz
0.01
0.01
f=1 KHz
f=1 KHz
0.001
0.001
0123456789101112
0123456789101112
Vout
Vout
0.01
0.01
0.001
0.001
10 100 1000 10000 100000
10 100 1000 10000 100000
f (Hz)
f (Hz)
Figure 14. Cross talk vs. frequency
CROSSTALK (dB)
CROSSTALK (dB)
-20
-20
STD mode
STD mode
-30
-30
RL=2 Ohm
RL=2 Ohm
Rg=600 Ohm
Rg=600 Ohm
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
10 100 1000 10000 100000
10 100 1000 10000 100000
f (Hz)
f (Hz)
12/32 Doc ID 14103 Rev 2
Page 13
TDA7575B Electrical characteristics curves
Figure 15. Cross talk vs. frequency
(LD mode)
CROSSTALK (dB)
CROSSTALK (dB)
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
LD mode
LD mode
Vo=1 Vrms
Vo=1 Vrms
RL=100 Ohm
RL=100 Ohm
10 100 1000 10000 100000
10 100 1000 10000 100000
f (Hz)
f (Hz)
Figure 17. Output attenuation vs. supply
voltage (vs. dependent muting)
OUT ATTN (dB)
OUT ATTN (dB)
20
20
0 dB=1 Vrms
0 dB=1 Vrms
0
0
RL=2 Ohm
RL=2 Ohm
-20
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
5678910
5678910
Vs (V)
Vs (V)
Figure 19. Power dissipation vs. output power
(4Ω - SINE)
Ptot (W)
Ptot (W)
35
35
Vs=14.4V
Vs=14.4V
30
30
RL=2 x 4 Ohm
RL=2 x 4 Ohm
f=1 KHz
f=1 KHz
25
25
20
20
15
15
10
10
5
5
0
0
0.1 1 10 100
0.1 1 10 100
HI-EFF
HI-EFF
Po (W)
Po (W)
STD
STD
Figure 16. CMRRR vs. frequency
CMRR (dB)
CMRR (dB)
-40
-40
Vcm=1 Vpp
Vcm=1 Vpp
-50
-50
-60
-60
-70
-70
10 100 1000 10000 100000
10 100 1000 10000 100000
f (Hz)
f (Hz)
Figure 18. Output attenuation vs. mute pin
voltage
OUT ATTN (dB)
OUT ATTN (dB)
20
20
0 dB=2 Vrms
0 dB=2 Vrms
RL=2 Ohm
RL=2 Ohm
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-100
1 1.5 2 2.5 3 3.5 4
1 1.5 2 2.5 3 3.5 4
MUTE PIN V (V)
MUTE PIN V (V)
Figure 20. Power dissipation vs. output power
(2Ω - SINE)
Ptot (W)
Ptot (W)
60
60
Vs=14.4V
Vs=14.4V
RL:=2 x 2 Ohm
RL:=2 x 2 Ohm
50
50
f=1 KHz
f=1 KHz
STD
40
40
30
30
20
20
HI-EFF
10
10
0
0
0.1 1 10 100
0.1 1 10 100
HI-EFF
Po (W)
Po (W)
STD
Doc ID 14103 Rev 2 13/32
Page 14
Electrical characteristics curves TDA7575B
Figure 21. Power dissipation vs. average
output power (Audio program
simulation, 4Ω)
Ptot (W)
30
Vs=14 V
25
RL=2 x 4Ω
GAUSSIAN NOISE
20
CLIP
START
15
STD
10
5
HI-EFF
0
012345
Po (W)
Figure 23. ITU R-ARM frequency response,
weighting filter for transient pop
Output attenuation (dB)
10
0
-10
Figure 22.
Power dissipation vs. average output
power (Audio program simulation,
2Ω)
Ptot (W)
Ptot (W)
35
35
Vs=14V
Vs=14V
RL=2 x 2 Ohm
RL=2 x 2 Ohm
30
30
GAUSSIAN NOISE
GAUSSIAN NOISE
25
25
20
20
15
15
10
10
5
5
0
0
01234567 8910
01234567 8910
CLIP
CLIP
START
START
Po (W)
Po (W)
STD
STD
HI-EFF
HI-EFF
-20
-30
-40
-50
10 100 1000 10000 100000
Hz
AC00343
14/32 Doc ID 14103 Rev 2
Page 15
TDA7575B Application circuits
4 Application circuits
Figure 24. Application circuit (TDA7575B)
V
DATA
VCC
12 2-26
S_GND
S
PW_GND TAB
IN1+
IN1-
IN2+
IN2-
C1 0.22μF
C2 0.22μF
C3 0.22μF
C4 0.22μF
D05AU1615
2
I
C BUS
A
B
CLK
25 3 14 13 7-21 16
8
9
20
19
11
15
C5
10μF
ST-BY/HE
Figure 25. Application circuit (TDA7575BPD)
C7
0.1μF
1
CD_OUT
C8
2200μF
17
1Ω SETTING
1μF
C6
R1 47KΩ
4
6
24
22
18
10
R2 47KΩ
OUT1+
OUT1-
OUT2+
OUT2-
V
2
C BUS
I
ENABLE
MUTE
IN1+
IN1-
IN2+
IN2-
C1 0.22μF
C2 0.22μF
C3 0.22μF
C4 0.22μF
D05AU1616
2
C BUS
I
A
B
CLK
32 8 7 21-2-33-34 14
23
2
3
18
17
5
13
C5
10μF
ST-BY/HE
V
S
DATA
VCC
6 24-25-30-31
S_GND
PW_GND TAB
C7
0.1μF
1
CD_OUT
C8
2200μF
15
1Ω SETTING
1μF
C6
R1 47KΩ
35-36
28-29
19-20
26-29
4
16
OUT1+
OUT1-
OUT2+
OUT2-
R2 47KΩ
V
2
I
C BUS
ENABLE
MUTE
Doc ID 14103 Rev 2 15/32
Page 16
I2C bus interface TDA7575B
5 I2C bus interface
Data transmission from microprocessor to the TDA7575B and vice versa takes place
through the 2 wires I
2
C BUS interface, consisting of the two lines SDA and SCL (pull-up
resistors to positive supply voltage must be connected).
5.1 Data validity
As shown by Figure 26, the data on the SDA line must be stable during the high period of
the clock.
The high and low state of the data line can only change when the clock signal on the SCL
line is low.
5.2 Start and stop conditions
As shown by Figure 27 a start condition is a high to low transition of the SDA line while SCL
is high.
The stop condItion Is A Low To High Transition of the SDA line while SCL is high.
5.3 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
5.4 Acknowledge
The transmitter
pulse (see Figure 28). The receiver
line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock
pulse.
(*) Transmitter
=master (μP) when it writes an address to the TDA7575B
= slave (TDA7575B) when the µP reads a data byte from TDA7575B
(**) Receiver
= slave (TDA7575B) when the µP writes an address to the TDA7575B
=master (μP) when it reads a data byte from TDA7575B
Figure 26. Data validity on the I
(*)
puts a resistive HIGH level on the SDA line during the acknowledge clock
SDA
SCL
(**)
2
C bus
DATA LINE
STABLE, DATA
VALID
the acknowledges has to pull-down (LOW) the SDA
CHANGE
DATA
ALLOWED
D99AU1031
16/32 Doc ID 14103 Rev 2
Page 17
TDA7575B I2C bus interface
Figure 27. Timing diagram on the I2C bus
SCL
2
I
CBUS
SDA
START
Figure 28. Timing acknowledge clock pulse
SCL
SDA
START
MSB
5.5 1 Ω capability setting
It is possible to drive 1Ω load paralleling the outputs into a single channel.
In order to implement this feature, outputs are to be connected on the board as follows:
● OUT1+ (pin 35 and pin 36) shorted to OUT2+ (pin 19 and pin 20)
● OUT1- (pin 28 and pin 29) shorted to OUT2- (pin 26 and pin 27).
It is recommended to minimize the impedance on the board between OUT2 and the load in
order to minimize THD distortion. It is also recommended to control the maximum mismatch
impedance between V
pins (pin 24/pin 25 respect to pin 30/pin 31), mismatch that must not exceed a value of
20 mΩ.
pins (pin 21/pin 22 respect to pin 33/pin 34) and between PWGND
CC
D99AU1032
1
23789
D99AU1033
STOP
ACKNOWLEDGMENT
FROM RECEIVER
With 1 Ω feature settled the active input is IN2 (pin 17 and pin 18), therefore IN1 pins should
be let floating.
It is possible to set the load capability acting on 1 Ω pin as follows:
1 Ω pin (pin 15) < 1.5 V: two channels mode (for a minimum load of 2 Ω)
1 Ω pin (pin 15) > 2.5 V: one channel mode (for 1 Ω load).
It is to remember that 1
Ohm function is a hardware selection.
Therefore it is recommended to leave 1Ω
channels mode configuration, or to short 1Ω pin to V
pin floating or shorted to GND to set the two
to set the one channel (1Ω)
CC
configuration.
Doc ID 14103 Rev 2 17/32
Page 18
I2C bus interface TDA7575B
5.6 I2C abilitation setting
It is possible to disable the I2C interface by acting on I2C pin (pin 16) and control the
TDA7575B by means of the usual standby and mute pins. In order to activate or deactivate
this feature, I
2
● I
2
● I
It is also possible to let I
to V
CC
In particular:
2
● I
– STD mode: V
–HE mode: V
– Play mode: V
The amplifier can always be switched off by putting V
be turn on only through I
2
● I
– STD mode: 3.5V < standby (pin 5) < 5
–HE mode: V
– Play mode: V
For both STD and HE mode the play/mute mode can be set acting on V
When I
internal logic circuitry. The faults detected are the short circuit to ground, to V
the load (after an aver current detection).
2
C pin must be set as follows:
C pin (pin 16) < 1.5V: I2C bus interface deactivated
C pin (pin 16) > 2.5V: I2C bus interface activated
2
C pin floating to deactivate the I2C bus interface, or to short I2C pin
to activate it.
C enabled: I2C pin (pin 16) > 2.5 V
(pin 5) > 3.5 V, IB2(D1)=0
st-by
(pin 5) > 3.5 V, IB2(D1)=1
st-by
(pin 4) >3.5 V, IB1 (D2) = 1
mute
to 0V , but with I2C enabled it can
2
C (with V
st-by
> 3.5 V).
st-by
C disabled: I2C pin (pin 16) < 1.5 V
(pin 5) > 7 V
stby
(pin 4) > 3.5 V
mute
pin.
mute
2
C bus is disabled, when a fault is detected pin 14 (CD-OUT) is pulled down by the
and across
CC
18/32 Doc ID 14103 Rev 2
Page 19
TDA7575B Software specifications
6 Software specifications
All the functions of the TDA7575B are activated by I2C interface.
The bit 0 of the "Address Byte" defines if the next bytes are write instruction (from μP to
TDA7575B) or read instruction (from TDA7575B to µP).
Table 5. Address selection
Bit Address
A6 1
A5 1
A4 0
A3 1
A2 0
A1 B
A0 A
R/W X
If R/W = 0, the μP sends 2 "instruction bytes": IB1 and IB2.
Table 6. IB1
Bit Instruction decoding bit
D7 0
D6
D5
D4
D3 0
D2
D1 0
D0
Diagnostic enable (D6 = 1)
Diagnostic defeat (D6 = 0)
Offset detection enable (D5 = 1)
Offset detection defeat (D5 = 0)
Gain = 26 dB (D4 = 0)
Gain = 12 dB (D4 = 1)
Mute (D2 = 0)
Unmute (D2 = 1)
CD 2% (D0 = 0)
CD 10% (D0 = 1)
Doc ID 14103 Rev 2 19/32
Page 20
Software specifications TDA7575B
Table 7. IB2
Bit Instruction decoding bit
D7 0
D6 0
D5 0
D4
D3
D2
D1
D0
Standby on - Amplifier not working - (D4 = 0)
Standby off - Amplifier working - (D4 = 1)
Power amplifier mode diagnostic (D3 = 0);
Line driver mode diagnostic (D3 = 1)
Current detection diagnostic enabled (D2 = 1)
Current detection diagnostic defeat (D2 = 0)
Power amplifier working in standard mode (D1 = 0)
Power amplifier working in high efficiency mode (D1 = 1)
Current detection threshold high (D7 =0)
Current detection threshold low (D7 =1)
If R/W = 1, the TDA7575B sends 2 "Diagnostics Bytes" to μP: DB1 and DB2.
Table 8. DB1
Bit Instruction decoding bit
D7 Thermal warming (if Tchip ≥ 150°C, D7 = 1)
Diag. cycle not activated or not terminated (D6 = 0)
D6
Diag. cycle terminated (D6 = 1)
Channel 1
current detection IB2 (D0) = 0
D5
Output peak current < 250 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
Channel 1
D4
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
Channel 1
D3
Normal load (D3 = 0)
Short load (D3 = 1)
Channel 1
Turn-on diag.: No open load (D2 = 0)
D2
Open load detection (D2 = 1)
Offset diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
Channel 1
D1
No short to V
Short to V
Channel 1
D0
No short to GND (D1 = 0)
Short to GND (D1 = 1)
cc
(D1 = 1)
cc
(D1 = 0)
Channel LF
current detection IB2 (D0) = 1
Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
20/32 Doc ID 14103 Rev 2
Page 21
TDA7575B Software specifications
Table 9. DB2
Bit Instruction decoding bit
Offset detection not activated (D7 = 0)
D7
Offset detection activated (D7 = 1)
Current sensor not activated (D6 = 0)
D6
Current sensor activated (D6 = 1)
Channel LR
Current detection IB2 (D0) = 0
D5
Output peak current < 250 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
Channel 2
D4
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
Channel 2
D3
Normal load (D3 = 0)
Short load (D3 = 1)
Channel 2
Turn-on diag.: No open load (D2 = 0)
D2
Permanent diag.: No output offset (D2 = 0)
Channel 2
D1
No short to Vcc (D1 = 0)
Short to V
Channel 2
D0
No short to GND (D1 = 0)
Short to GND (D1 = 1)
Open load detection (D2 = 1)
Output offset detection (D2 = 1)
(D1 = 1)
cc
Channel LR
Current detection IB2 (D0) = 1
Output peak current < TBD mA - Open load (D5 = 1)
Output peak current > TBD mA - Normal load (D5 = 0)
Doc ID 14103 Rev 2 21/32
Page 22
Software specifications TDA7575B
6.1 Examples of bytes sequence
1 - Turn-on diagnostic - Write operation
Start Address byte with D0 = 0 ACK IB1 with D6 = 1 ACK IB2 ACK STOP
L
2 - Turn-on diagnostic - Read operation
Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK STOP
The delay from 1 to 2 can be selected by software, starting from T.B.D. ms
3a - Turn-on of the power amplifier with mute on, diagnostic defeat.
Start Address byte with D0 = 0 ACK IB1 ACK IB2 ACK STOP
X000XXXX XXX1XX1X
3b - Turn-off of the power amplifier
Start Address byte with D0 = 0 ACK IB1 ACK IB2 ACK STOP
X0XXXXXX XXX0XXXX
4 - Offset detection procedure enable
Start Address byte with D0 = 0 ACK IB1 ACK IB2 ACK STOP
XX1XX1XX XXX1XXXX
5 - Offset detection procedure stop and reading operation (the results are valid only for the
offset detection bits (D2 of the bytes DB1, DB2, DB3, DB4).
Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK STOP
● The purpose of this test is to check if a D.C. offset (2 V typ.) is present on the outputs,
produced by input capacitor with anomalous leakage current or humidity between pins.
● The delay from 4 to 5 can be selected by software, starting from T.B.D. ms
22/32 Doc ID 14103 Rev 2
Page 23
TDA7575B Diagnostics functional description
7 Diagnostics functional description
7.1 Turn-on diagnostic
It is activated at the turn-on (stand-by out) under I2C bus request. Detectable output faults are:
– Short to GND
–Short TO Vs
– Short across the speaker
– Open speaker
To verify if any of the above misconnections are in place, a subsonic (inaudible) current
pulse (Figure 29) is internally generated, sent through the speaker(s) and sunk back. The
Turn On diagnostic status is internally stored until a successive diagnostic pulse is
requested (after a I
If the "stand-by out" and "diag. enable" commands are both given through a single
programming step, the pulse takes place first (power stage still in stand-by mode, low,
outputs = high impedance).
Afterwards, when the Amplifier is biased, the PERMANENT diagnostic takes place. The
previous Turn On state is kept until a short appears at the outputs.
2
C reading).
Figure 29. Turn-on diagnostic: working principle
Vs~5V
Isource
CH+
CH-
Isink
I (mA)
Isource
Isink
~100mS
Measure time
t (ms)
Fig. Figure 30 and Figure 31 show SVR and OUTPUT waveforms at the turn-on (stand-by
out) with and without Turn-on diagnostic.
Figure 30. SVR and output behavior - case 1: without turn-on diagnostic
Vsvr
Out
Permanent diagnostic
acquisition time (100mS Typ)
Bias (power amp turn-on)
I2CB DATA
Diagnostic Enable
(Permanent)
FAULT
event
Permanent Diagnostics data (output)
permitted time
Read Data
t
Doc ID 14103 Rev 2 23/32
Page 24
Diagnostics functional description TDA7575B
Figure 31. SVR and output pin behavior - case 2: with turn-on diagnostic
Vsvr
Out
Turn-on diagnostic
acquisition time (100mS Typ)
Permanent diagnostic
acquisition time (100mS Typ)
Turn-on Diag nostics dat a (output )
permitted time
Read Data
Diagnostic Enable
(Permanent)
Permanent Diagnostics data (output)
FAULT
event
permitted time
I2CB DATA
Diagnostic Enable
(Turn-on)
Bias (power amp turn-on)
permitted time
The information related to the outputs status is read and memorized at the end of the
current pulse top. The acquisition time is 100 ms (typ.). No audible noise is generated in the
process. As for short to GND / Vs the fault-detection thresholds remain unchanged from 26
dB to 12 dB gain setting. They are as follows:
Figure 32. Short circuit detection thresholds
t
S.C. to GND x S.C. to Vs
0V 1.8V VS-1.5V V
1.2V VS-0.9V
xNormal Operation
D02AU1341
S
Concerning short across the speaker / open speaker, the threshold varies from 26 dB to 12
dB gain setting, since different loads are expected (either normal speaker's impedance or
high impedance). The values in case of 26 dB gain are as follows:
Figure 33. Load detection thresholds - high gain setting
S.C. across Load x Open Load
0V 1.5Ω
0.5Ω
If the line-driver mode (Gv= 12 dB and line driver mode diagnostic = 1) is selected, the same
thresholds will change as follows:
Figure 34. Load detection thresholds - high gain setting
S.C. across Load x Open Load
0Ω 4.5Ω 200Ω infinite
24/32 Doc ID 14103 Rev 2
1.5Ω 400Ω
70Ω
xNormal Operation
130Ω
D01AU1254
Infinite
xNormal Operation
D01AU1252
Page 25
TDA7575B Diagnostics functional description
7.2 Permanent diagnostics
Detectable conventional faults are:
– Short to GND
–Short to Vs
– Short across the speaker
The following additional features are provided:
– Output offset detection
The TDA7575B has 2 operating statuses:
1. RESTART mode. The diagnostic is not enabled. Each audio channel operates
independently from each other. If any of the a.m. faults occurs, only the channel(s)
interested is shut down. A check of the output status is made every 1 ms (fig. 30).
Restart takes place when the overload is removed.
2. DIAGNOSTIC mode. It is enabled via I
(such to cause the intervention of the short-circuit protection) occurs to the speakers
outputs. Once activated, the diagnostics procedure develops as follows (fig. 31):
– To avoid momentary re-circulation spikes from giving erroneous diagnostics, a
check of the output status is made after 1ms: if normal situation (no overloads) is
detected, the diagnostic is not performed and the channel returns back active.
– Instead, if an overload is detected during the check after 1 ms, then a diagnostic
cycle having a duration of about 100 ms is started.
– After a diagnostic cycle, the audio channel interested by the fault is switched to
RESTART mode. The relevant data are stored inside the device and can be read
by the microprocessor. When one cycle has terminated, the next one is activated
2
by an I
C reading. This is to ensure continuous diagnostics throughout the car-
radio operating time.
– To check the status of the device a sampling system is needed. The timing is
chosen at microprocessor level (over than half a second is recommended).
2
C bus and self activates if an output overload
Figure 35. Restart timing without diagnostic enable (permanent)
each 1ms time, a sampling of the fault is done
1mS
t
Short circuit removed
Overcurrent and short
circuit protection intervention
(i.e. short circuit to GND)
1-2mS
1mS 1mS 1mS
Figure 36. Restart timing with diagnostic enable (permanent)
1mS 100mS 1mS1mS
Overcurrent and short
circuit protection intervention
(i.e. short cir cuit to GND)
Doc ID 14103 Rev 2 25/32
Short circuit removed
Out
t
Page 26
Diagnostics functional description TDA7575B
7.3 Output DC offset detection
Any DC output offset exceeding ± 2 V are signalled out. This inconvenient might occur as a
consequence of initially defective or aged and worn-out input capacitors feeding a DC
component to the inputs, so putting the speakers at risk of overheating.
This diagnostic has to be performed with low-level output AC signal (or Vin = 0).
The test is run with selectable time duration by microprocessor (from a "start" to a "stop"
command):
● Start = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1
● Stop = Actual reading operation
Excess offset is signalled out if persistent throughout the assigned testing time. This feature
is disabled if any overloads leading to activation of the short-circuit protection occurs in the
process.
7.4 AC diagnostic
It is targeted at detecting accidental disconnection of tweeters in 2-way speaker and, more
in general, presence of capacitively (AC) coupled loads.
This diagnostic is based on the notion that the overall speaker's impedance (woofer +
parallel tweeter) will tend to increase towards high frequencies if the tweeter gets
disconnected, because the remaining speaker (woofer) would be out of its operating range
(high impedance). The diagnostic decision is made according to peak output current
thresholds, and it is enabled by setting (IB2-D2) = 1. Two different detection levels are
available:
● HIgh current threshold IB2 (D7) = 0
– Iout > 500 mApk = normal status
– Iout < 250 mApk = open tweeter
● Low current threshold IB2 (D7) = 1
– Iout > 250 mApk = normal status
– Iout < 125 mApk = open tweeter
To correctly implement this feature, it is necessary to briefly provide a signal tone (with the
amplifier in "play") whose frequency and magnitude are such to determine an output current
higher than 500mApk with IB2(D7)=0 (higher than 250mApk with IB2(D7)=1) in normal
conditions and lower than 250 mApk with IB2(D7)=0 (lower than 125 mApk with IB2(D7)=1)
should the parallel tweeter be missing.
The test has to last for a minimum number of 3 sine cycles starting from the activation of the
AC diagnostic function IB2<D2>) up to the I
2
C reading of the results (measuring period). To
confirm presence of tweeter, it is necessary to find at least 3 current pulses over the above
threholds over all the measuring period, else an "open tweeter" message will be issued.
The frequency / magnitude setting of the test tone depends on the impedance
characteristics of each specific speaker being used, with or without the tweeter connected
(to be calculated case by case). High-frequency tones (> 10 kHz) or even ultrasonic signals
are recommended for their negligible acoustic impact and also to maximize the impedance
module's ratio between with tweeter-on and tweeter-off.
26/32 Doc ID 14103 Rev 2
Page 27
TDA7575B Diagnostics functional description
Figure 37 shows the load impedance as a function of the peak output voltage and the
relevant diagnostic fields.
This feature is disabled if any overloads leading to activation of the short-circuit protection
occurs in the process.
Figure 37. Current detection high: load impedance |Z| vs. output peak voltage
Load |z| (Ohm)
50
Low current detection area
30
D5 = 1 of the DBx byres
20
(Open load)
Iout (peak) <250mA
Iout (peak) >500mA
10
5
3
2
1
12345678
High current detection area
(Normal load)
D5 = 0 of the DBx bytes
Vout (Peak)
IB2(D0) = 0
Figure 38. Current detection low: load impedance |Z| vs. output peak voltage
Load |z| (Ohm)
50
Low current detection area
30
D5 = 1 of the DBx byres
20
10
5
3
2
1
0.5
(Open load)
1
1.5
High current detection area
(Normal load)
D5 = 0 of the DBx bytes
2
Vout (Peak)
2.5
3
3.5 4
Iout (peak) <125mA
Iout (peak) >250mA
IB2(D0) = 1
7.5 Multiple faults
When more misconnections are simultaneously in place at the audio outputs, it is
guaranteed that at least one of them is initially read out. The others are notified after
successive cycles of I
This is true for both kinds of diagnostic (turn-on and permanent).
The table below shows all the couples of double-fault possible. It should be taken into
account that a short circuit with the 4 Ω speaker unconnected is considered as double fault.
2
C reading and faults removal, provided that the diagnostic is enabled.
Doc ID 14103 Rev 2 27/32
Page 28
Diagnostics functional description TDA7575B
Table 10. Double fault table for turn-on diagnostic
S. GND (sc) S. GND (sk) S. Vs S. Across L. Open L.
S. GND (sc) S. GND S. GND
S. GND (sk) / S. GND S. Vs S. GND Open L. (*)
S. Vs / / S. Vs S. Vs S. Vs
S. Across L. / / / S. Across L. N.A.
Open L. / / / / Open L. (*)
S. GND (so) / S. GND (sk) in the above table make a distinction according to which of the 2
outputs is shorted to ground (test-current source side= so, test-current sink side = sk). More
precisely, in both the channels SO = CH+, and SK = CH-.
In permanent diagnostic the table is the same, with only a difference concerning open load
(*), which is not among the recognizable faults. Should an open load be present during the
device's normal working, it would be detected at a subsequent turn-on diagnostic cycle (i.e.
at the successive car radio turn-on).
7.6 Faults availability
All the results coming from I2C bus, by read operations, are the consequence of
measurements inside a defined period of time. If the fault is stable throughout the whole
period, it will be sent out. This is true for DC diagnostic (turn-on and permanent), for offset
detector.
S. Vs + S.
GND
S. GND S. GND
To guarantee always resident functions, every kind of diagnostic cycles (turn-on, permanent,
offset) will be reactivate after any I
2
C reading operation. So, when the micro reads the I2C, a
new cycle will be able to start, but the read data will come from the previous diag. cycle (i.e.
The device is in turn-on state, with a short to GND, then the short is removed and micro
reads I
cycle. If another I
to observe a change in diagnostic bytes, two I
2
C. The short to GND is still present in bytes, because it is the result of the previous
2
C reading operation occurs, the bytes do not show the short). In general
2
C reading operations are necessary.
7.7 I2C programming/reading sequences
A correct turn on/off sequence respectful of the diagnostic timings and producing no audible
noises could be as follows (after battery connection):
● Turn-on: (Standby OUT + DIAG enable) --- 500 ms (min) --- muting OUT
● Turn-off: Muting IN --- 20 ms --- (DIAG disable + standby IN)
Car radio installation: DIAG enable (write) --- 20 0ms --- I
disappear).
– Offset test: device in play (no signal)
– Offset enable - 30 ms - I
(repeat I
2
C reading until high-offset message disappears).
2
C reading
2
C read (repeat until all faults
28/32 Doc ID 14103 Rev 2
Page 29
TDA7575B Package information
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Figure 39. PowerSO36 (slug up) mechanical data and package dimensions
DIM.
A 3.270 - 3.410 0.1287 - 0.1343
A2 3.100 - 3.180 0.1220 - 0.1252
A4 0.800 - 1.000 0.0315 - 0.0394
A5 - 0.200 - - 0.0079 -
a1 0.030 -
b 0.220 - 0.380 0.0087 - 0.0150
c 0.230 - 0.320 0.0091 - 0.0126
D 15.800 - 16.000 0.6220 - 0.6299
D1 9.400 - 9.800 0.3701 - 0.3858
D2 - 1.000 - - 0.0394 -
E 13.900 - 14.500 0.5472 - 0.5709
E1 10.900 - 11.100 0.4291 - 0.4370
E2 - - 2.900 - - 0.1142
E3 5.800 - 6.200 0.2283 - 0.2441
E4 2.900 - 3.200 0.1142 - 0.1260
e - 0.650 - - 0.0256 -
e3 - 11.050 - - 0.4350 -
G 0 - 0.075 0 - 0.0031
H 15.500 - 15.900 0.6102 - 0.6260
h - - 1.100 - - 0.0433
L 0.800 - 1.100 0.0315 - 0.0433
N - - 10˚ - - 10˚
s - -8˚- -8˚
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”).
(2) No intrusion allowed inwards the leads.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
-0.040
0.0012 - -0.0016
OUTLINE AND
MECHANICAL DATA
PowerSO36 (SLUG UP)
7183931 G
Doc ID 14103 Rev 2 29/32
Page 30
Package information TDA7575B
Figure 40. Flexiwatt27 (vertical) mechanical data and package dimensions
DIM.
A 4.45 4.50 4.65 0.175 0.177 0.183
B 1.80 1.90 2.00 0.070 0.074 0.079
C 1.40 0.055
D 0.75 0.90 1.05 0.029 0 .035 0.041
E 0.37 0.39 0.42 0.014 0.015 0.016
F (1) 0.57 0.022
G 0 .80 1.00 1.20 0.031 0 .040 0.047
G1 25.75 26.00 26.25 1.014 1.023 1.033
H (2) 28.90 29.23 29.30 1.139 1.150 1.153
H1 17.00 0.669
H2 12.80 0.503
H3 0.80 0.031
L (2) 22.07 22. 47 22.87 0.869 0.884 0.904
L1 18.57 18.97 19.3 7 0.731 0.747 0.762
L2 (2) 15.50 15.70 15.9 0 0.610 0.618 0.626
L3 7.70 7.85 7.95 0.303 0.309 0.313
L4 5 0.197
L5 3. 5 0.138
M 3.70 4.00 4.30 0.145 0.157 0.169
M1 3.60 4.00 4.40 0.142 0.157 0.173
N 2.20 0.086
O 2 0 .079
R 1.70 0.067
R1 0.5 0.02
R2 0.3 0.12
R3 1.25 0.049
R4 0.50 0.019
V5˚ (Typ.)
V1 3˚ (Typ.)
V2 20˚ (Typ.)
V3 45˚ (Typ.)
(1): dam-ba r protusion no t included
(2): molding pr otusion incl uded
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
MECHANICAL DATA
Flexiwatt27 (vertical)
V
C
B
H
V3
OL3 L4
L2
Pin 1
H3
G
H1
G1
H2
R3
N
F
V
A
R4
R2
R
L
L1
V2
R2
FLEX27ME
V1
R1
L5
R1 R1
M1
M
V1
D
E
7139011
30/32 Doc ID 14103 Rev 2
Page 31
TDA7575B Revision history
9 Revision history
Table 11. Document revision history
Date Revision Changes
30-Oct-2007 1 Initial release.
17-Dec-2009 2
Updated Figure 39: PowerSO36 (slug up) mechanical data and
package dimensions on page 29.
Doc ID 14103 Rev 2 31/32
Page 32
TDA7575B
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