The Device incorporates the SRS
(Sound Retrieval System) under
licencefromSRS Labs, Inc.
1 STEREOINPUTAND 1 MIXER INPUT
INPUT ATTENUATION CONTROL IN 0.5dB
STEP
TREBLEMIDDLE AND BASS CONTROL
VOICECANCELLERIS AVAILABLE
STEREO SRS SURROUND SOUND WITH
CENTER& SPACECONTROL IS AVAILABLE
THREE STANDARD SURROUND MODES
ARE AVAILABLE:
- MUSICIN 4 DIFFERENTSELECTABLE
RESPONSES
- MOVIE ANDSIMULATED IN 256
DIFFERENTSELECTABLE RESPONSES
REAR OUTPUT IS AVAILABLE TO DRIVE
EXTRA SURROUNDSPEAKERS
2 SPEAKERSOUTPUTS
- INDEPENDENTATTENUATORS IN 1dB
STEPFOR BALANCEFACILITY
- ZEROCROSSINGATTENUAT IONAVAILABLE
- INDEPENDENTMUTE FUNCTION
2 RECORD OUTPUTS
- INDEPENDENTATTENUATORS IN 1dB
STEPFOR BALANCEFACILITY
- MUXAVAILABLE FORPROCESSESSIGN AL
SELECTIO N
- INDEPENDENTMUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS
ADDRESSPIN AVAILABLE
DESCRIPTION
The TDA7465 is a volume tone (bass middle and
treble) balance (Left/Right) processorswith stereo
SRS and voicecanceller for quality audio applications in car radio, Hi-Fi, TV systems.
It reproduces SRS (Sound Retrieval System)
sound by external components and surround
sound by using phase shifters and a signal matrix. The AC signal setting is obtained by resistor
networks and switches combined with operational
amplifiers according to the SRS laboratories
specification. An Extra Mix Input is available to
TDA7465
SDIP42
ORDERING NUMBER: TDA7465
PIN CONNECTION
1
V
S
2
PS4
3
PS3
4
PS2
5
PS1R_IN
6
LP
7
LP1
8
HP1
9
HP2
VAR_L
BASSO_L
VAR_R
BASSO_R
BASS_LO
BASS_LI
BASS_RO
BASS_RI
MIDDLE_LO
MIDDLE_LI
MIDDLE_RO
MIDDLE_RI
10
11
12
13
14
15
16
17
18
19
20
21
D96AU479B
connectmicrophone for KARAOKEfeature.
Control of all the functions is accomplishedby serial bus.
Thanks to the used BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained.
THDTotal Harmonic Distortion V = 1Vrms f= 1KHz0.010.1%
S/NSignal to Noise Ratio V
S
Thermal Resistance Junction-pinsMax.85°C/W
Operating Supply Voltage11V
S
Operating Ambient Temperature-10to 85°C
Storage Temperature Range-55 to +150°C
stg
Supply Voltage7910.2V
S
CL
Max. input signal handling2Vrms
= 1Vrms (mode = OFF)106dB
out
Channel Separation f = 1KHz90dB
C
Input Attenuation Control (0.5dB)-31.50dB
Treble Control (2db step)-14+14dB
Middle Control (2db step)-14+14dB
Bass Control (2dB step)-14+14dB
Balance Control 1dB step (L
)-790dB
CH,RCH
Mute Attenuation100dB
ELECTRICALCHARACTERISTICS (referto the test circuit T
Control Range79dB
Step Resolution0.511.5dB
Attenuation set errorAv = 0 to -20dB-1.501.5dB
Av = -20 to -79dB-302dB
DC StepsAdjacent att. steps-303mV
Output Mute Condition70100dB
Input Impedance22.53037.5KΩ
Zero CrossingThresholdD7 = 0
Output Noise (OFF)Output Mute, Flat
B
= 20Hz to 20KHz
W
Output Noise (Movie) Standard
Surround Sound
Output Noise (Music) Standard
Surround Sound
Output Noise (Simulated)
Standard Surround Sound
Output Noise (SRS)
Mode =Movie ,
B
= 20Hz to 20KHz
W
Mode = Music ,
B
= 20Hz to 20KHz,
W
Mode = Simulated,
B
= 20Hz to 20KHz
W
BW= 20Hz to 20KHz50µVrms
V
S
+
20mV
2
4
5
30µVrms
30µVrms
30µVrms
Surround Sound
= 1Vrms0.010.1%
in
Channel Separation7090dB
Clipping Leveld = 0.3%22.5Vrms
Output Resistance103050Ω
DC Voltage Level3.8V
Input Low Voltage1V
Input High Voltage3V
Input Current-5+5µA
Output Voltage SDA
IO= 1.6mA0.4V
Acknowledge
Vrms
µ
Vrms
µ
6/20
Page 7
TDA7465
I2C BUSINTERFACE
Data transmission from microprocessor to the
TDA7465 and viceversa takes place through the
2 wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start andStop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
2
Figure 3: Data Validityon theI
CBUS
knowledgebit. The MSB is transferredfirst.
Acknowledge
The master (µP) puts a resistiveHIGH levelon the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
duringthisclock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can generate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor,the µP can use a simpler transmission:
simply it waits one clock without checking the
slaveacknowledging,and sendsthe new data.
This approach of course is less protected from
misworking.
Figure 4: TimingDiagram of I
2
Figure 5: Acknowledgeon the I
CBUS
2
CBUS
7/20
Page 8
TDA7465
SOFTWARESPECIFICATION
InterfaceProtocol
The interface protocol comprises:
A start condition (S)
address
A subaddressbytes
A sequenceof data (N byte + achnowledge)
A stopcondition (P)
A chip address byte, containing the TDA7465
CHIP ADDRESS
MSBLSBMSBLSBMSBLSB
S100000A0ACKACKDATAACKP
D95AU226A
SUBADDRESSDATA 1 to DATA n
BDATA
ACK = Achnowledge
S = Start
P = Stop
A = Address
B = Auto Increment
EXAMPLES
No IncrementalBus
rect chip address, a subaddresswith the MSB = 0
(no incremental bus), N-data (all these data concern the subaddressselected), a stop condition.
The TDA7465 receives a start condition, the cor-
CHIP ADDRESS
MSBLSBMSBLSBMSBLSB
S100000A0ACKACKDATAACKP
D95AU306
Incremental Bus
The TDA7465 receives a start condition, the correct chip address,a subaddresswith theMSB = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
CHIP ADDRESS
MSBLSBMSBLSBMSBLSB
S100000A0ACKACKDATAACKP
D95AU307
SUBADDRESSDATA
0D3
X X XD2 D1 D0
SUBADDRESS from ”1XXX1010” to ”1XXX1111”
of DATA are ignored.
The DATA 1 concerns thesubaddress sent, and
the DATA 2 concerns the subaddress sent plus
one in the loop etc.and, at the end, it receives the
stop condition.
SUBADDRESSDATA 1 to DATA n
1D3
X X XD2 D1 D0
8/20
Page 9
TDA7465
DATA BYTES (Address= 80(HEX) [82(HEX)if ADDRESS pin is connectedto V
S]
FUNCTIONSELECTION:
The first byte (subaddress)
MSBLSBSUBADDRESS
D7D6D5D4D3D2D1D0
BXXX0000INPUT ATTENUATION
BXXX0001SURROUND & OUT & EFFECT
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are notauthorized for useas criticalcomponentsin lifesupport devices or systems without express
written approval of SGS-THOMSON Microelectronics.