Datasheet TDA7438D, TDA7438 Datasheet (SGS Thomson Microelectronics)



DIGITALLY CONTROLLED AUDIO PROCESSOR

INPUTMULTIPLEXER

- 3 STEREO INPUTS

- SELECTABLEINPUT GAIN FOR OPTIMAL
ADAPTATIONTO DIFFERENT SOURCES

ONE STEREO OUTPUT
TREBLE, MIDDLE AND BASS CONTROL IN

2.0dB STEPS

VOLUMECONTROL IN 1.0dB STEPS
TWOSPEAKERATTENUATORS:

- TWOINDEPENDENTSPEAKERCONTROL
IN 1.0dBSTEPSFOR BALANCE FACILITY

- INDEPENDENTMUTE FUNCTION

ALL FUNCTION ARE PROGRAMMABLE VIA
SERIALBUS

TDA7438

THREE BANDS

SO28

ORDERING NUMBER: TDA7438D (SO28)

TDA7438 (DIP28)

DIP28

DESCRIPTION

The TDA7438 is a volume tone (bass, middle and
treble) balance (Left/Right) processor for quality
audio applicationsin car-radio and Hi-Fi systems.

Selectable input gain is provided. Control of all
the functions is accomplishedby serialbus.

BLOCK DIAGRAM

MUXOUTL INL

6 7 18 17 16 14 15

G

0/30dB

2dB STEP

G

8 9 19 10 11 12 13 23

MUXOUTR INR TREBLE(R)

VOLUME

VOLUME

L-IN1

L-IN2

L-IN3

R-IN1

R-IN2

R-IN3

3

100K

4

100K

5

100K

2

100K

1

100K

28

100K

INPUT

MULTIPLEXER

+ GAIN

The AC signal setting is obtained by resistor net­works and switches combined with operational
amplifiers.

Thanks to the used BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained.

TREBLE(L)

MIN(L)

TREBLE

TREBLE

MIDDLE

I2CBUS DECODER + LATCHES

MIDDLE

MIN(R) MOUT(R) BOUT(R)BIN(R)

MOUT(L)

R

M

R

M

BIN(L)

BASS

BASS

R

B

R

B

BOUT(L)

SPKR ATT

LEFT

SPKR ATT

RIGHT

V

REF

SUPPLY

CREF

27

21
22
20

26

24
25

D96AU488A

LOUT

SCL
SDA
DIG_GND

ROUT

V

S

AGND

April 1999

1/17

TDA7438

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

S

T

amb

T

stg

PIN CONNECTION

Operating Supply Voltage 10.5 V
Operating Ambient Temperature -10 to 85 °C
Storage Temperature Range -55 to 150 °C

R_IN2
R_IN1

L_IN1
L_IN2
L_IN3 V

MUXOUTL

INL

MUXOUTR

INR

MIN(R)

MOUT(R)

BIN(R)

BOUT(R)

BIN(L)

1
2
3
4
5
6
7
8
9
10
11
12
13
14

D96AU489A

28
27
26
25
24

22
21
20
19
18
17
16
15

R_IN3
LOUT
ROUT
AGND

S

CREF23
SDA
SCL
DIG-GND
TREBLE(R)
TREBLE(L)
MIN(L)
MOUT(L)
BOUT(L)

THERMAL DATA

Symbol Parameter Value Unit

R

thj-pin

Thermal ResistanceJunction-pins 85 °C/W

QUICK REFERENCE DATA

Symbol Parameter Min. Typ. Max. Unit

V

S

V

CL

THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 0.1 %

S/N Signal to Noise Ratio V

S

C

(*) Even applied to Speaker AttenuatorLeft, Speaker Attenuator Right, Volume Control stand alone or to the combination, if any.

2/17

Supply Voltage 6 9 10.2 V
Max. input signal handling 2 Vrms

= 1Vrms (mode = OFF) 106 dB

out

Channel Separation f = 1KHz 90 dB
Input Gain in (2dBstep) 0 30 dB
Volume Control (1dB step) -47 0 dB
Treble Control (2dB step) -14 +14 dB
Middle Control (2dB step) -14 +14 dB
Bass Control (2dB step) -14 +14 dB
Balance Control 1dB step -79 0 dB
Mute Attenuation (*) 80 100 dB

TDA7438

ELECTRICALCHARACTERISTICS

R

= 600Ω, all controlsflat (G = 0dB), unless otherwisespecified)

G

(refer to the test circuit T

=25°C,VS= 9V,RL= 10KΩ,

amb

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY

V

S

I

S

SVR Ripple Rejection 60 90 dB

Supply Voltage 6 9 10.2 V
Supply Current 7 mA

INPUT STAGE

G

G

R

V

S

inman

G

IN

CL

IN

inmin

step

Input Resistance 100 KΩ
Clipping Level THD = 0.3% 2 2.5 Vrms
Input Separation The selected input is grounded

80 100 dB

through a 2.2µ capacitor
Minimum Input Gain -1 0 1 dB
Maximum Input Gain 30 dB
Step Resolution 2 dB

VOLUMECONTROL

R

C

RANGE

A

VMAX

A

STEP

E

A

E

V

DC

A

mute

BASS CONTROL

Gb Control Range Max. Boost/cut +12.0 +14.0 +16.0 dB

B

STEP

R

TREBLECONTROL

Gt Control Range Max. Boost/cut +13.0 +14.0 +15.0 dB

T

STEP

MIDDLE CONTROL

Gm Control Range Max. Boost/cut +12.0 +14.0 +16.0 dB

M

STEP

R

M

Input Resistance 20 33 50 KΩ

i

Control Range 45 47 49 dB
Max. Attenuation 45 47 49 dB
Step Resolution 0.5 1 1.5 dB
Attenuation Set Error AV= 0 to-24dB -1.0 0 1.0 dB

A

= -24 to -47dB -1.5 0 1.5 dB

V

Tracking Error AV= 0 to-24dB 0 1 dB

T

A

= -24 to -47dB 0 2 dB

V

DC Step adjacent attenuation steps

from 0dB to A

V

max

0

0.5

Mute Attenuation 80 100 dB

(The center frequency and the response quality can be chosen by the ext. circuitry)

Step Resolution 1 2 3 dB
Internal FeedbackResistance 33 44 55 KΩ

B

(The centerfrequency and the response quality can be chosen by the ext.circuitry)

Step Resolution 1 2 3 dB

(The centerfrequency and the response quality can be chosen by the ext. circuitry)

Step Resolution 1 2 3 dB
Internal FeedbackResistance 18.75 25 31.25 K

3mV

SPEAKERATTENUATORS

C

RANGE

S

V

A

STEP

E

A

E

DC

mute

Control Range 76 dB
Step Resolution 0.5 1 1.5 dB
Attenuation Set Error AV= 0 to-20dB -1.5 0 1.5 dB

A

= -20 to -56dB -2 0 2 dB

V

Tracking Error AV= 0 to-24dB 0 1 dB

T

A

= -24 to -47dB 0 2 dB

V

DC Step adjacent attenuation steps 0 3 mV
Mute Attenuation 80 100 dB

mV

Ω

3/17

TDA7438

ELECTRICALCHARACTERISTICS

(continued.)

Symbol Parameter Test Condition Min. Typ. Max. Unit

AUDIOOUTPUTS

VCLIP ClippingLevel d = 0.3% 2.1 2.6 VRMS

R

L

R

O

DC DC Voltage Level 3.8 V

V

GENERAL

E

NO

Output Load Resistance 2 KΩ
Output Impedance 10 40 70

(Gain, Bass, Treble, Middle Controls Flat)

Output Noise All gains = 0dB;

515µV

BW = 20Hz to 20KHz flat

E

t

S/N Signal to Noise Ratio All gains 0dB; V

S

C

d Distortion A

Total Tracking Error

(Volume + SpeakerAttenuator)

AV= 0to -24dB 0 1 dB
A

= -24to -47dB 0 2 dB

V

A

= -47to -79dB 0 3 dB

V

O =1VRMS ; 90 106 dB

Channel Separation Left/Right 80 100 dB

=0;VI=1V

V

; 0.01 0.08 %

RMS

BUS INPUT

V

IL

V

IH

I

IN

Input Low Voltage 1V
Input High Voltage 3 V
Input Current VIN= 0.4V -5 5

Ω

A

µ

TEST CIRCUIT

L-IN1

0.47µF

L-IN2

0.47µF

L-IN3

0.47µF

R-IN1

0.47µF

R-IN2

0.47µF

R-IN3

0.47µF

5.6nF

2.2µF

3

100K

4

100K

5

100K

2

100K

1

100K

28

100K

INPUT MULTIPLEXER

MUXOUTL INL

G

0/30dB

2dB STEP

G

+ GAIN

MUXOUTR INR TREBLE(R)

TREBLE(L)

6 7 18 17 16 14 15

VOLUME

VOLUME

8 9 19 10 11 12 13 23

2.2µF

5.6nF

2.7K 5.6K

18nF 22nF 100nF 100nF

MIN(L)

MOUT(L)

R

M

TREBLE

TREBLE

MIDDLE

I2CBUS DECODER + LATCHES

MIDDLE

R

M

MOUT(R) BOUT(R)BIN(R)

MIN(R)

18nF 22nF 100nF 100nF

2.7K 5.6K

BIN(L)

BASS

BASS

BOUT(L)

R

B

SPKR ATT

LEFT

SPKR ATT

RIGHT

V

REF

R

SUPPLY

B

CREF

10µF

27

21
22
20

26

24
25

LOUT

SCL
SDA
DIGGND

ROUT

V

S

AGND

D96AU490A

4/17

TDA7438

APPLICATIONSUGGESTIONS

The first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute) for
the first one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution.
The very high resolutionallows the implementation
of systemsfreefromanynoisyacousticaleffect.
The TDA7438 audioprocessor provides 3 bands
tones control.

Bass, Middle Stages

The Bass and the middle cells have the same
structure.

The Bass cell has an internal resistor Ri = 44KΩ
typical.
The Middle cell has an internalresistor Ri = 25KΩ
typical.

Several filter types can be implemented, connect­ing external components to the Bass/Middle IN
and OUTpins.

Figure 1.

Ri internal

OUTIN

C

1

R

2

D95AU313

C

2

The fig.1 refers to basic T Type Bandpass Filter
starting from the filter component values (R1 in­ternal and R2,C1,C2 external) the centre fre­quency Fc, the gain Av at max. boost and the fil­ter Q factorare computedas follows:

=

F

C

1

2 ⋅ π ⋅√Ri, R2, C1, C2

R2 C2+R2 C1+Ri C1

A

=

V

R2 C1 + R2 C2

√Ri R2 + C1 C2

=

Q

R2 C1+R2 C2

Viceversa, once Fc, Av, and Ri internal value are
fixed, the external componentsvalues will be:

2

V

Q

A

V

−1) ⋅

2

−

⋅

C1

1Q

Q

2

C1 =

2 ⋅ π ⋅ R

=

R2

− 1

A

V

⋅ π ⋅C1⋅

2

− 1 − Q

V

F

C

C2 =

⋅ (

A

⋅ Q

i

A

TrebleStage

The treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25KΩ
typical) and an external capacitor connected be­tween treble pins andground

Typical responsesare reported in Figg. 10 to 13.

CREF

The suggested 10µF reference capacitor (CREF)
value can be reduced to 4.7µF if the application
requiresfasterpower ON.

Figure 2:

THD vs. frequency

Figure3:

THDvs. R

LOAD

5/17

TDA7438

Figure 4:

Channelseparationvs. frequency

Figure 6: Middleresponse

=25kΩ

R

i

C9= 15nF (MIN)
C6- 22nF (MOUT)
R1 = 2.7kΩ

Figure5:

Bassresponse

Figure7: Trebleresponse

Ri= 44kΩ
C9 = C10 = 100nF (Bout,Bin)
R3 = 5.6kΩ

Figure 8:

6/17

Typicaltoneresponse

TDA7438

2

C BUSINTERFACE

I
Data transmission from microprocessor to the

TDA7438 and vice versa takes place through the
2 wires I

2

C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).

Data Validity

As shown in fig. 3, thedata on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.

Start and Stop Conditions

As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran­sition of the SDA line while SCL is HIGH.

Byte Format

Every byte transferred on the SDA line must con­tain 8 bits. Each byte must be followed by an ac-

Figure 3:

Data Validityon theI

2

CBUS

knowledgebit. The MSB is transferredfirst.

Acknowledge

The master (µP)puts a resistiveHIGH level on the
SDA line during the acknowledgeclock pulse (see
fig. 5). The peripheral (audio processor) that ac­knowledges has to pull-down (LOW) the SDA line
duringthisclock pulse.

The audio processor which has been addressed
has to generate an acknowledge after the recep­tion of each byte, otherwise the SDAline remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen­erate the STOP information in order to abort the
transfer.

Transmissionwithout Acknowledge

Avoiding to detect the acknowledge of the audio
processor,the µP canuse a simplertransmission:
simply it waits one clock without checking the
slaveacknowledging,and sends the new data.

This approach of course is less protected from
misworking.

Figure 4:

TimingDiagram of I

Figure 5: Acknowledgeon the I

2

CBUS

2

CBUS

7/17

TDA7438

SOFTWARESPECIFICATION

InterfaceProtocol
The interface protocol comprises:

A start condition (S)

address
A subaddressbytes
A sequenceof data (N byte + acknowledge)
A stopcondition (P)

A chip address byte, containing the TDA7438

CHIP ADDRESS

MSB LSB MSB LSB MSB LSB

S10001000ACK ACK DATA ACK P

D96AU420

SUBADDRESS DATA 1 to DATA n

X DATA

XXB

ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment

EXAMPLES
No IncrementalBus

rect chip address, a subaddress with the B = 0
(no incremental bus), N-data (all these data con­cern the subaddressselected),a stop condition.

The TDA7438 receives a start condition, the cor-

CHIP ADDRESS

MSB LSB MSB LSB MSB LSB

S10001000ACK ACK DATA ACK P

D96AU421

IncrementalBus

The TDA7438 receive a start conditions, the cor­rect chip address, a subaddress with the B = 1
(incremental bus): now it is in a loop condition
with an autoincreaseof the subaddress whereas

CHIP ADDRESS

MSB LSB MSB LSB MSB LSB

S10001000ACK ACK DATA ACK P

D96AU422

SUBADDRESS DATA

XD3

XX0 D2D1D0

SUBADDRESS from ”XXX1000” to ”XXX1111”of
DATAare ignored.
The DATA 1 concern the subaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.

SUBADDRESS DATA 1 to DATA n

XD3

XX1 D2D1D0

8/17

POWERON RESET CONDITION

INPUT SELECTION IN2

INPUT GAIN 28dB

VOLUME MUTE

BASS 0dB

MIDDLE 2dB

TREBLE 2dB

SPEAKER MUTE

DATA BYTES

Address = 88 HEX (ADDR:OPEN).
FUNCTIONSELECTION:First byte (subaddress)

TDA7438

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

XXXB00 00INPUT SELECT
XXXB00 01INPUT GAIN
XXXB00 10VOLUME
XXXB00 11BASS
XXXB01 00MIDDLE
XXXB01 01TREBLE
XXXB01 10SPEAKER ATTENUATE ”R”
XXXB01 11SPEAKER ATTENUATE ”L”

B = 1: INCREMENTAL BUSACTIVE
B = 0: NO INCREMENTALBUS
X = DON’T CARE

SUBADDRESS

INPUT SELECTION

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

XXXXXX00 IN3
XXXXXX01 NOTALLOWED
XXXXXX10 IN2
XXXXXX11 IN1

INPUT MULTIPLEXER

9/17

TDA7438

DATA BYTES (continued)

INPUT GAIN SELECTION

MSB LSB INPUT GAIN

D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS

0000 0dB
0001 2dB
0010 4dB
0011 6dB
0100 8dB
0 1 0 1 10dB
0 1 1 0 12dB
0 1 1 1 14dB
1 0 0 0 16dB
1 0 0 1 18dB
1 0 1 0 20dB
1 0 1 1 22dB
1 1 0 0 24dB
1 1 0 1 26dB
1 1 1 0 28dB
1 1 1 1 30dB

GAIN = 0 to 30dB

VOLUMESELECTION

MSB LSB VOLUME

D7 D6 D5 D4 D3 D2 D1 D0 1dB STEPS

0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB

1 1 1 -7dB
0000 0dB
0 0 0 1 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
X 1 1 1 X X X MUTE

VOLUME = 0 to 47dB/MUTE

10/17

DATA BYTES (continued)

BASS SELECTION

MSB LSB BASS

D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS

0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB

TDA7438

MIDDLE SELECTION

MSB LSB MIDDLE

D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS

0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB

11/17

TDA7438

DATA BYTES (continued)

TREBLESELECTION

MSB LSB TREBLE

D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS

0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB

SPEAKERATTENUATE SELECTION

MSB LSB SPEAKER ATTENUATION

D7 D6 D5 D4 D3 D2 D1 D0 1dB

0 0 0 0dB

0 0 1 -1dB

0 1 0 -2dB

0 1 1 -3dB

1 0 0 -4dB

1 0 1 -5dB

1 1 0 -6dB

1 1 1 -7dB

0000 0dB
0 0 0 1 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
0 1 1 0 -48dB
0 1 1 1 -56dB
1 0 0 0 -64dB
1 0 0 1 -72dB
1 1 1 1 X X X MUTE

SPEAKER ATTENUATION = 0 to-79dB/MUTE

12/17

TDA7438

PINS:

CREF

PINS:

23

V

S

1, 2, 3, 4, 5, 28

V

S

PINS:

26,27

V

S

V

S

20K

20K

ROUT
LOUT

24

20µA

D96AU430

D96AU434

PINS:

6, 8

V

S

V

S

IN

PINS:

7, 9

INL

INR

20µA

MUXOUT

20µA

100K

GND

V

REF

V

S

D96AU425

PINS:

10, 11

V

S

D96AU491

20µA

20µA

33K

25K

MOUT(L)

MOUT(R)

D96AU431

V

D96AU427

REF

13/17

TDA7438

PINS:

PINS:

10, 17

MIN(L)

MIN(R)

13,15

PINS:

12,14

V

V

S

20µA

25K

BIN(L)

D96AU431

V

S

PINS:

BIN(R)

18, 19

S

20µA

44K

D96AU428

V

S

20µA

20µA

BOUT(L)

BOUT(R)

PINS:

20

SCL

44K

D96AU429

20µA

D96AU424

TREBLE(R)

PINS:

SDA

TREBLE(L)

50K

D96AU433

21

20µA

D96AU423

14/17

TDA7438

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.63 0.025

b 0.45 0.018

b1 0.23 0.31 0.009

b2 1.27 0.050

D 37.34 1.470

E 15.2 16.68 0.598 0.657

e 2.54 0.100

e3 33.02 1.300

F 14.1 0.555

I 4.445 0.175

L 3.3 0.130

mm inch

0.012

OUTLINE AND

MECHANICAL DATA

DIP28

15/17

TDA7438

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45° (typ.)

D 17.7 18.1 0.697 0.713

E 10 10.65 0.394 0.419

e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299
L 0.4 1.27 0.016 0.050
S8°(max.)

mm inch

OUTLINE AND

MECHANICAL DATA

SO28

16/17

TDA7438

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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publicationsupersedes and replaces all informationpreviously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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17/17