Datasheet TDA7437 Datasheet (SGS Thomson Microelectronics)



DIGITALLY CONTROLLED AUDIO PROCESSOR

INPUTMULTIPLEXER

- FOURSTEREO,ONEMONOINPUT,AND
ONEDIFFERENTIAL INPUT

- SELECTABLEINPUT GAIN FOR OPTIMAL
ADAPTATIONTO DIFFERENT SOURCES

FULLY PROGRAMMABLE LOUDNESS
FUNCTION

VOLUME CONTROL IN 1dB STEPS INCLUD­ING GAIN UP TO 16dB

ZERO CROSSINGMUTE, SOFT MUTE AND
DIRECT MUTE

BASS AND TREBLE CONTROL
FOURSPEAKERATTENUATORS

- FOURINDEPENDENT SPEAKERS
CONTROLIN 1dB STEPSFOR
BALANCEAND FADER FACILITIES

PAUSE DETECTOR PROGRAMMABLE
THRESHOLD

ALL FUNCTIONS PROGRAMMABLE VIA SE-

2

RIAL I

DESCRIPTION

The audioprocessor TDA7437 is an upgrade of
the TDA731X audioprocessorfamily.

CBUS

TDA7437

PQFP44 and TQFP44

ORDERING NUMBERS: TDA7437 (PQFP44)

TDA7437T (TQFP44)

Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained.Several new features like
softmute, and zero-crossing mute are imple­mented.
The soft Mute function can be activated in two
ways:

1 Via serial bus(Mute byte, bit D0)
2 Directly on pin 28 through an I/O line of the

microcontroller

Very low DC stepping is obtained by use of a
BICMOStechnology.

PIN CONNECTION

December 1999

TREB_R

IN_R

MUXOUT_R

LOUD_R

DIFFGND_R

DIFF_R
STEREO4_R
STEREO1_R
STEREO2_R
STEREO3_R

MONO

TREB-L

AGND

AVDD

DVDD

CREF

ADDR

SCL

SDA

44 43 42 41 3940 38 37 36 35 34

1
2
3
4
5
6
7
8
9

10

DIFF_L

STEREO4_L

STEREO1_L

171118 19 20 21 22

CSM

STEREO2_L

STEREO3_L

12 13 14 15 16

LOUD_L

DIFFGND_L

DGND

PAUSE

IN_L

MUXOUT_L

OUT_LF

33
32
31
30
29
28
27
26
25
24
23

D96AU435A

MID_LI

OUT_RF
OUT_LR
MID_RI
MID_RO
OUT_RR
SMEXT
BASS_RO
BASS_RI
BASS_LO
BASS_LI
MID_LO

1/23

TDA7437

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

,DV

AV

DD

T

amb

T

stg

THERMAL DATA

Symbol Parameter Value Unit

R

th j-amb

QUICK REFERENCE DATA

Symbol Parameter Min. Typ. Max. Unit

,DVDDSupply Voltage (AVDDand DVDDmust be at the same potential) 6 9 10.2 V

AV

DD

V

CL

THD Total Harmonic Distortion V = 1Vrms f= 1KHz 0.01 0.8 %

S/N Signal to Noise Ratio 111 dB

S

C

Operating Supply Voltage 10.5 V

DD

Operating Ambient Temperature -40 to 85 °C
Storage Temperature Range -55 to 150 °C

Thermal ResistanceJunction-pins Max. 150 °C/W

Max. input signal handling 2.1 2.6 Vrms

Channel Separation f = 1KHz 95 dB
Input Gain 1dB step 0 15 dB
Volume Control 1dB step -63 16 dB
Treble Control 2dB step -14 +14 dB
Bass Control 2dB step -14 +14 dB
Middle Control 2dB step -14 +14 dB
Fader and BalanceControl 1dB step -79 0 dB
Loudness Control 1dB step 0 20 dB
Mute Attenuation 100 dB

2/23

BLOCK DIAGRAM

TDA7437

5.6K

2.7K

100nF

18nF 100nF

5.6nF 22nF

BIN(L)BOUT(L)MIN(L)MOUT(L)

FLout

ATT

SPKR

RLout

ATT

SPKR

S-MUTE

ADDR

SDA

SCL

C BUS DECODER + LATCHES

2

I

DIGGND

RRout

ATT

SPKR

S-MUTE

FRout

ATT

SPKR

CONTROL

SOFT, ZERO

MUTE

D95AU249B

CSM

PAUSE

SMEXT

BIN(R)

100nF

BOUT(R)MIN(R)

18nF 100nF

22nF

(R)

MOUT

47nF47nF

5.6K

2.7K

TREBLE(R)

2.2µF 47nF

TREBLE(L)

LOUD(L)

IN_L

MUXOUT_L

STEREOIN1L

4 x 470nF

STEREOIN3L

STEREOIN2L

TREBLE BASSMIDDLE

VOLUME

+ LOUDN

INGAIN

DIFFINL

STEREOIN4L

2 x 4.7µF

MULTIPLEXER

MONO

DIFFINLGND

5 x 470nF

STEREOIN1R

STEREOIN2R

TREBLE BASSMIDDLE

VOLUME

+ LOUDN

INGAIN

STEREOIN3R

STEREOIN4R

DIFFINR

DIFFINRGND

2 x 4.7µF

SUPPLY

AVDD

DVDD

47nF 5.6nF

IN_R

CREF LOUD(R)

22µF

ANGND

2.2µF
MUXOUT_R

3/23

TDA7437

ELECTRICALCHARACTERISTICS (AVDD,DVDD= 9V; RL= 10KΩ;Rg=50Ω;T

amb

=25°C;

all gains= 0dB;f = 1KHz. Refer to the test circuit, unless otherwise specified.)

Symbol Parameter Test Condition Min. Typ. Max. Unit

INPUT SELECTOR (MONO AND STEREO INPUTS)

R

V

CL

S

I

R

L

G

I MIN

G

I MAX

G

step

E

a

V

DC

DIFFERENTIAL INPUT (Pin 5, 6, 13, 14)

R

CMRR Common Mode Rejection Ratio V

d Distortion V

IN

e

DIFF

G

VOLUME CONTROL

R

G

MAX

A

MAX

A

STEPC

E

A

E

t

V

DC

LOUDNESS CONTROL (Pin 4, 12)

R

A

MAX

A

step

ZERO CROSSING MUTE

V

TH

A

MUTE

V

DC

Input Resistance pin 7 to 11and 15 to 18 70 100 130 KΩ

I

Clipping Level d ≤ 0.3% 2.1 2.6 V
Input Separation 80 95 dB
Output Load Resistance 2 KΩ
Minimum Input Gain -0.75 0 +0.75 dB
Maximum Input Gain 14 15 16 dB
Step Resolution 0.5 1.0 1.5 dB
Set Error -1.0 0 1.0 dB
DC Steps Adiacent GainSteps 0.5 10 mV

to G

G

IMIN

I

Input Resistance Input selector BIT D4 = 0 (0dB) 10 15 20 KΩ

IMAX

3mV

Input selector BIT D4 = 1(-6dB) 14 20 26 KΩ

CM

RMS

I

=1V

=1V

; f =1KHz 45 70 dB

RMS

0.01 0.08 %
Input Noise 20Hz to 20KHz; Flat; D6 = 0 5 µV
Differential Gain D4 = 0 -1 0 1 dB

D4 = 1 -7 -6 -5 dB

Input Resistance Pin 2 and 20 31 44 57 KΩ

I

Maximum Gain 15 16 17 dB
Maximum Attenuation 61 63.75 66.5 dB
Step Resolution Coarse Atten. 0.5 1.0 1.5 dB
Attenuation Set Error G = 16 to -20dB -1.0 0 1.0 dB

G = -20 to -63dB -2.75 2.75 dB
Tracking Error 2dB
DC Steps Adjacent GainSteps -5 +5 mV

Adjacent Attenuation Steps -3 +3 mV

From 0dB to A

Internal Resistor Loud = On 35 50 65 KΩ

I

MAX

0.5 5 mV

Maximum Attenuation 19 20 21 dB
Step Resolution 0.5 1 1.5 dB

Zero Crossing Threshold

WIN = 11 30 mV
(note 1)

WIN = 10 60 mV

WIN = 01 110 mV

WIN = 00 220 mV
Mute Attenuation 80 100 dB
DC Step 0dB to Mute 0.1 3 mV

RMS

4/23

TDA7437

ELECTRICALCHARACTERISTICS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

SOFT MUTE

A

MUTE

T

DON

T

DOFF

R

INT

V

SMH

V

SML

BASS CONTROL

C

range

A

step

R

g

MIDDLE CONTROL

C

range

A

step

R

g

TREBLE CONTROL

C

RANGE

A

step

SPEAKER ATTENUATORS

C

RANGE

A

step

A

MUTE

E

A

V

DC

AUDIO OUTPUT

V

clip

R

L

R

O

V

DC

Mute Attenuation 50 65 dB
ON Delay Time C

OFF Current V

CSM

=22nF;0 to-20dB; I =I

CSM

=22nF;0 to-20dB; I =I

C

V

CSM
CSM

=0V;I= I
=0V;I = I

MAX

MIN

MAX

0.8 1.5 2.0 ms

MIN

25 45 60 ms
20 40 60 µA

2 µA
Pullup Resistor (pin 28) (note 2) 100 KΩ
(pin 28) Level High 3.5 V
(pin 28) Level Low Soft Mute Active 1 V

Control Range ±11.5 ±14 ±16 dB
Step Resolution 1 2 3 dB
Internal Feedback Resistance 31 44 57 KΩ

Control Range ±11.5 ±14 ±16 dB
Step Resolution 1 2 3 dB
Internal Feedback Resistance 17.5 25 32.5 KΩ

Control Range ±13 ±14 ±15 dB
Step Resolution 1 2 3 dB

Control Range 79 dB
Step Resolution AV= 0to -40dB 0.5 1 1.5 dB
Output Mute Attenuation Data Word = 1111XXXX 80 100 dB
Attenuation Set Error AV= 0to -40dB 1.5 dB
DC Steps Adjacent Attenuation Steps 0.1 3 mV

Clipping Level d = 0.3% 2.1 2.6 Vrms
Output Load Resistance 2 KΩ
Output Impedance 50 90 140 Ω
DC Voltage Level 3.5 3.8 4.1 V

5/23

TDA7437

ELECTRICALCHARACTERISTICS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

PAUSE DETECTOR

V

TH

I

DELAY

V

THP

GENERAL

V

CC

I

CC

PSRR Power SupplyRejection Ratio f = 1KHz 70 90 dB

e

NO

E

t

S/N Signal to Noise Ratio All Gains = 0dB; V

S

C

d Distortion V

Pause Threshold WIN = 11 30 mV

WIN = 10 60 mV
WIN = 01 110 mV

WIN = 00 220 mV
Pull-Up Current 15 25 35 µA
Pause Threshold 3.0 V

Supply Voltage 6 9 10.2 V
Supply Current 7 10 13 mA

Output Noise OutputMuted(B= 20to20kHzflat) 4 µV

All Gains0dB

615µV

(B=200to20kHzflat)
Total Tracking Error AV= 0to -20dB 0 1 dB

= -20to -60dB 0 2 dB

A

V

= 2.1V

O

rms

111 dB

Channel Separation L- R 80 95 dB

=1V all gain = 0dB 0.01 0.08 %

IN

BUS INPUTS

V

IL

V

lN

I

lN

V

O

Note 1: WIN represents the MUTE programming bit pair D6,D5for the zero crossing window threshold
Note 2: Internallpullup resistor toVs/2; ”LOW” = softmuteactive

Note: The ANGND and DIGGNDlayout wires must be kept separated. A 50Ω resistor is recommended to be put as far as possible

from the device.

Input Low Voltage 1V
Input High Voltage 3 V
Input Current VIN = 0.4V -5 5 µA
Output Voltage SDA

IO= 1.6mA 0.1 0.4 V
Acknowledge

The CLD - andCDR- can be shortcircuitedin applicationsproviding3 wiresCD signal

L+

L-∼R-

CD TDA7437

=

R+

L+

L-

R-

R+

D00AU1125

CLD - = DIFFINLGND
CDR - = DIFFINRGND

6/23

TDA7437

2

C BUS INTERFACE

I

Data transmission from microprocessor to the
TDA7437 and viceversa takes place thru the 2
wires I

2

C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externallyconnected).

Data Validity

As shown in fig. 3, thedata on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.

Start and Stop Conditions

As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran­sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.

Byte Format

Every byte transferred to the SDA line must con­Figure 3: Data Validity on the I

2

CBUS

tain 8 bits. Each byte must be followed by an ac­knowledgebit. The MSB is transferredfirst.

Acknowledge

The master(µP)putsa resistiveHIGHlevelon the
SDA line during the acknowledgeclock pulse (see
fig. 5). The peripheral (audioprocessor) that ac­knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAlineisstableLOWduringthis clockpulse.
The audioprocessor which has been addressed
hasto generateanacknowledgeafterthereception
ofeachbyte, otherwisethe SDAlineremainsatthe
HIGHlevelduringthe ninthclock pulsetime.In this
case the master transmitter can generate the
STOPinformation in orderto abortthetransfer.

Transmissionwithout Acknowledge

Avoiding to detect the acknowledge of the audio­processor, the µP can use a simplier transmis­sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworkingand decreasesthe noise immunity.

Figure 4: Timing Diagram of I2CBUS

2

Figure 5: Acknowledge on the I

CBUS

7/23

TDA7437

SOFTWARESPECIFICATION
Interface Protocol

The interface protocol comprises:

A start condition (s)

read (=1)/write(=0)transmission)
A subaddressbyte.
A sequenceof data (N-bytes+ acknowledge)
A stopcondition (P)

A chip address byte,(the LSB bit determines

CHIP ADDRESS SUBADDRESS DATA 1 to DATA n

MSB LSB MSB LSB MSB LSB

S100010AR/W

ACK X X X I A3 A2 A1 A0 ACK DATA ACK P

ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used

MAX CLOCK SPEED500kbits/s
ADDRpin open A = 0

ADDRpin close to Vs A = 1

AUTO INCREMENT

If bit I in the subaddressbyte is set to ”1”,the autoincrementof the subaddressis enabled

SUBADDRESS (receivemode)

MSB LSB FUNCTION

X X X I A3A2A1A0

0 0 0 0 Input Selector
0 0 0 1 Loudness
0 0 1 0 Volume
0 0 1 1 Bass, Treble
0 1 0 0 Speaker Attenuator LF
0 1 0 1 Speaker Attenuator LR
0 1 1 0 Speaker Attenuator RF
0 1 1 1 Speaker Attenuator RR
1 0 0 0 Input Gain Middle
1 0 0 1 Mute

TRANSMITTED DATA

Send Mode

MSB LSB

X X X X X SM ZM P

P = Pause(Active low)
ZM = Zero crossingmuted (HIGH active)
SM =Soft mute activated(HIGH active)
X = Not used

The transmitted data is automaticallyupdated aftereach ACK.
Transmissioncan be repeated without newchipaddress.

8/23

DATA BYTE SPECIFICATION
Input Selector

TDA7437

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

1000DIFFERENTIAL
1001STEREO 1
1010STEREO 2
1011STEREO 3
1100STEREO 4
1101MONO

X X X X 0 X X X DC CONNECT (1)

0 0 HALF-DIFF 0dB (*)
0 1 HALF-DIFF -6dB (*)
1 0 FULL-DIFF 0dB (**)
1 1 FULL-DIFF -6dB (**)

(*) Selected when using a 3 wires differential source (pins 5 and 13 shorted)
(**) Selected when using 4 wires differential source
(1) OUTR-INR (OUTL-INR) short circuited internally (no need external connection)

FUNCTION

Loudness

MSB LSB FUNCTION

D7 D6 D5 D4 D3 D2 D1 D0 LOUDNESS STEP

000000 0dB
000001 1dB
000010 2dB
000011 3dB
000100 4dB
000101 5dB
000110 6dB
000111 7dB
001000 8dB
001001 9dB
0 0 1 0 1 0 10dB
0 0 1 0 1 1 11dB
0 0 1 1 0 0 12dB
0 0 1 1 0 1 13dB
0 0 1 1 1 0 14dB
0 0 1 1 1 1 15dB
0 1 0 0 0 0 16dB
0 1 0 0 0 1 17dB
0 1 0 0 1 0 18dB
0 1 0 0 1 1 19dB
0 1 0 1 0 0 20dB
1 LOUDNESS OFF

FINE VOLUME
00 0dB
01 -0.25dB
10 -0.5dB
11 -0.75dB

9/23

TDA7437

Mute

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

0 1 Soft Mute On
0 0 1 Soft Mute with fast slope
0 1 1 Soft Mute with slow slope

0 0 1 Zero Mute

1 Direct Mute

1 Reset
0 0 0 Zerocross window (220mV)
0 1 0 Zerocross window (110mV)
1 0 0 Zerocross window (60mV)
1 1 0 Zerocross window (30mV)

0 Nonsymmetrical Bass
1 Symmetrical Bass

Volume

FUNCTION

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0dB
1 0 0 1 -1dB
1 0 1 0 -2dB
1 0 1 1 -3dB
1 1 0 0 -4dB
1 1 0 1 -5dB
1 1 1 0 -6dB
1 1 1 1 -7dB
1
1 0 0 0 0 16dB
10001 8dB
10010 0dB
1 0 0 1 1 -8dB
1 0 1 0 0 -16dB
1 0 1 0 1 -24dB
1 0 1 1 0 -32dB
1 0 1 1 1 -40dB
1 1 0 0 0 -48dB
1 1 0 0 1 -56dB
0 X X X X X X X MUTE

FUNCTION

10/23

Speaker

TDA7437

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

000 0dB
001 -1dB
010 -2dB
011 -3dB
100 -4dB
101 -5dB
110 -6dB
111 -7dB

0000 0dB
0001 -8dB
0010 -16dB
0011 -24dB
0100 -32dB
0101 -40dB
0110 -48dB
0111 -56dB
1000 -64dB
1001 -72dB
1111XXX MUTE

FUNCTION

1.25dB step

11/23

TDA7437

Bass Treble

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB

0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 126B
1 0 0 0 14dB

FUNCTION

TREBLE STEP

BASS STEPS

12/23

Input Stage Gain Middle

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

0000 0dB
0001 1dB
0010 2dB
0011 3dB
0100 4dB
0101 5dB
0110 6dB
0111 7dB
1000 8dB
1001 9dB
1 0 1 0 10dB
1 0 1 1 11dB
1 1 0 0 12dB
1 1 0 1 13dB
1 1 1 0 14dB
1 1 1 1 15dB

0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 126B
1 0 0 0 14dB

FUNCTION

IN-GAIN STEP

MIDDLE STEP

TDA7437

13/23

TDA7437

MUTE & PAUSEFEATURES

The TDA7437 provides three types of mute, con­trolledviaI2Cbus (seepag.10, MUTE BYTEregis­ter).

SOFT MUTE

Bit D0=1
Bit D0=0

→

SoftMute ON

→

Soft Mute OFF

It allows an automatic soft muting and unmuting
of the signal.
The time constant is fixed by an external capaci­tor Csm insertedbetweenpin Csm and ground.

Once fixed the external capacitor, two different
slopes (timeconstant) are selectable by program­mationof bit D1.

Bit D1=0
Bit D1=1

→ fast slope (I=Imax)
→ slowslope (I=Imin)

The soft mute generates a gradual signal de­creasing avoiding big click noise of an immediate
high attenuation, without necessity to program a
sequence of decreasing volume levels. A re­sponse example is reported in Fig.12 (mute) and
Fig.13 (unmute). The final attenuation obtained
with softmute ON is 60dBtypical.
The used reference parameter is the delay time
taken to reach 20dB attenuation (no matter what
the signal levelis).

Using a capacitorCsm=22nF this delay is:
d =1.8mswhenselectedFastslopemode(bitD1=0)
d =25ms whenselectedSlowslopemode(bitD1=1
In application, the soft mute ON programmation

should be followed by programmationof DIRECT
MUTE ON (see later) in order to achieve a final
100dB attenuation.
Beside the I2C bus programmation,the Soft Mute
ON can be generated in a fast way by forcing a
LOW level at pin SMEXT (TTL Level compatible).
This approach is recommended for fast RDS AF
switching.

The Soft Mute status can be detected via I2C
bus, reading the Transmitted Byte, bit SM (see
data sheet pag. 8).

read bit SM = 1 soft mutestatusON
read bit SM = 0 soft mutestatusOFF

DIRECT MUTE

bit D3 = 1 Direct mute ON
bit D3 = 0 Direct nute OFF

The direct mute bit forces an internal immediate
signal connectionto ground.
It is located just before the Volume/Loudness
stage, and givesa typical 100dB attenuation.

SPEAKERSMUTE

An additional direct mute function is included in
the speakers attenuators stage.

The four output LF, RF, LR, RR can be separately
muted by setting the speaker attenuator byte to
the value 01111111binary.

Typical attenuationlevel 100dB. This mute is use­ful for fader and balance functions. It should not
be applied for system mute/unmute, because it
can generate noise due to the offset of previous
stages (bass/ treble).

ZEROCROSSINGMUTE

bit D2=1 D4=0 zerocrossing mute ON
bit D2=0 D4=0 zerocrossing mute OFF
The mute activation/deactivationis delayed until

the signal waveform crosses the DC zero level
(Vref level).

The detection works separately for the left and
the right channels (see Figg. 14, 15). Four differ­ent windows threshold are software selectable by
two dedicatedbits.

bit D6 bit D5 WINDOW

00Vref DC +/-220mV
01Vref DC +/-110mV
10Vref DC +/-60mV
11Vref DC +/-30mV

The zero crossing mute activation/deactivation
starts when the AC signal level falls inside the se­lectedwindow(internalcomparator).

The ZEROCROSS Mute (and Pause) detector is
always active. It can be disabled,if the feature is
not used, by forcing the bit D4=1 Zero crossing
and Pause detector reset.

In this way the internal comparator logic is
stopped,eliminating itsswitching noise.

The zero cross mute status is detected reading
the Transmitted Byte bit ZM.

bit ZM = 1 zerocross mute status ON
bit ZM = 0 zerocross mute status OFF

PAUSEFUNCTION

On chip isimplementeda pause detectorblock.
It uses the same 4 windows threshold selectable

for the zero crossing mute, bit D6,D5 byte MUTE
(see above). The detector can be put in OFF by
forcingbit D4=1, otherwiseit is active.

The Pause detector info is available at PAUSE
pin. A capacitor must be connected between
PAUSEpin and Ground.

When the incoming signal is detected to be out­side the selected window, the external capacitor
is discharged. When the signal is inside the win­dow, the capacitor is integrating up (see Figg.16
and 17).

14/23

TDA7437

a)by reading directly the Pausepin level.

TheON/OFFvoltagethresholdis 3.0V typical.
PauseOFF = level low (< 3.0V)
PauseON = levelhigh ( ; 3.0V)

2

b)by reading via I

CbustheTra nsmi tte dByte,bitP

P=0pauseactive.
P=1no pause detected.

The external capacitor value fixes the time con­stant.

The pull up current is 25uVtypical
With input signal

Vin = 1Vrm --; Vdc pin pause = 15mV
Vin = 0Vrms--; Vdc pin pause = 5.62V
For example choosing Cpause = 100nF the

charge up constant is about 22ms. Instead with
Cpause = 15nF the charge up constant is about
360us.

The Pause detection is useful in applications like
RDS, to perform noiseless tuning frequeny jumps
avoiding to mutethe signal.

NO SYMMETRICALBASS CUT RESPONSE

bit D7=0 No symmetrical
bit D7=1 Symmetrical
The Bass stage has the option to generate an

unsymmetrical response, for cut mode settings
(bass level from-2db to - 14dB)

For example using a T-type band pass externa
The feature is useful for human ear equalization

in noisy enviromentslike carsetc.
See examples in Fig. 18 (symmetrical response)

and Fig.19 (unsymmetricalresponse).

TRANSMITTED DATA (SENDMODE)

bit P=0 Pause active
bit P=1 No pause detected

bit ZM = 1 Zerocross mute ON
bit ZM = 0 Zerocross mute OFF

bit SM = 1 Soft mute ON
bit SM = 0 Soft mute OFF

bit ST = 1 Stereosignaldetected(inputMPX)
bit ST = 0 Mono signal detected(input MPX)

The TDA7437 allows thereadingof fourinfo bits.
The type (Stereo/Mono) of received broadcasting

signal is easily checked and displayed by using

the ST bit.
The P bit check is useful in tuning jumps without

signal muting.
The SM soft mute statusbecomes active immedi-

ately, when bit D0 is set to 1 (soft mute ON,
MUTE byte) and not when the signal level has
reachedthe 60 dB final attenuation.

TDA7437 I

The protocol is standard I

2

C BUS PROTOCOL

2

C, using subaddress

byte plus data bytes(see pagg.8to 13).
The optional Autoincrement mode allows to re-

fresh all the bytes registers with transmission of a
single subaddress, reducing drastically the total
transmission time.

Without autoincrement, subaddress bit I=0,to
refresh all the bytes registers (10), it is necessary
to transmit 10 times the chip address,the subad­dress and the data byte.

Working with a 100Kb/s clock speed the total time
would be :

[(9*3+2)*10]bits*10us=2.9ms
Instead using autoincrement mode, subaddress

bit I=1, the total time will be:
(9*12+2)*10us=1.1ms.
The autoincrementmode is useful also to refresh

partially the data. For example to refresh the 4
speakersattenuatorsit is possibleto programthe
subaddress Spkr LF (code XX010100), followed
by the data byte of SPKR LF, LR, RF, RR in se­quence.

Note:
that the autoincrement mode has a module 16
counter, whereas the total used register bytes are

10.
It is not correct to refresh all the 10 bytes starting

froma subaddressdifferent than XX010000.
For example using subaddress XX010010 (vol-

ume) the registers from Volume to Mute (see
pag. 8) are correctly updated but the next two
transmitted bytes instead to refer to the wanted
Input selector and Loudness are discharged. (the
solution in this case is to send two separatedpat­tern in autoinc mode, the first composed by ad­dress, subaddress XX010010, 8 data bytes, and
the second composed by address, subaddress
XX010000,2 data bytes).

With autoincrement disabled, the protocol allows
the transmission in sequenceof N data bytes of a
specificregister, without necessity to resend each
time the addressand subaddressbytes.

This feature can be implemented, for example, if
a gradual Volume change has to be performed
(the MCU has not to send the STOP condition,
keepingactivethe TDA7437 communication).

15/23

TDA7437

WARNING

The TDA7437 always needs to receive a STOP
condition, before beginning a new START condi­tion. The device doesn’trecognize a START con­dition if a previously active communication was
not endedby a STOPcondition.

2

C BUS READ MODE

I

The TDA7437 gives to the master a 1 byte
”TRANSMITTED INFO” via I2C bus in read
mode. The read mode is Master activated by
sending the chip address with LSB set to 1, fol­lowed byacknowledge bit.

The TDA7437 recognizes the request. At the fol­lowing master generated clocks bits, the
TDA7437 issues the TRANSMITTED INFO byte
on the SDA data bus line (MSB transmitted first).

At thenineth clockbit theMCU master can:

- acknowledge the reception, starting in this
way the transmission of another byte from
the TDA7437.

- no acknowledge, stopping the read mode
communication.

LOUDNESSSTAGE

The previous SGS-THOMSON audioprocessors
were implementing a fixed loudness response,
only ON/OFFsw programmable.

No possibility to change the loud boost rate at a
certain volume level.
The TDA7437 implements a fully programmable
loudnesscontrolin 20 steps of 1dB.

It allows a customized loudness response for
each application.
The external network connected to the loudness
pins LOUD_Land LOUD_R fixes thetype of loud­ness response

1) SimpleCapacitor
The loudness effect is only a boost of low fre­quencies.(see Fig.20)

2)Second order Loudness (boost of low and
high frequencies).

3)Second order decreased type Loudness
(lowerboost of low and high frequencies).

4)Second order modifiedtype Loudness(higher
boost of low and high frequencies).

BASS & MID FILTERS

Severalbass filter types can be implemented.
Normallyit is usedthebasi cT-typeBandpassFilter .
Starting from the filter component values (R1 in­ternal and R2, C1, C2 external), the centre fre­quency Fc, the gain Av at max bass boost and
the filter Q factor are computedas follows:

=

F

c

1

2 ⋅ Π ⋅√(R1 ⋅ R2 ⋅ C1 ⋅ C2)

R2⋅C2+R2⋅C1+R1⋅C1

A

=

v

R2 ⋅ C1 +R2 ⋅ C2

√(R1⋅R2⋅C1⋅C2)

Q =

R2 ⋅ C1 + R2 ⋅ C2

Viceversa fixed Fc, Av, and R1 (internal typ.+/­30%), the external componentvaluesare:

A

− 1

v

⋅ Π ⋅R1⋅

2

Q ⋅ Q ⋅ C1

−1−Q⋅

A

v

−1−Q⋅

A

v

Q

Q

Q

⋅ (Av− 1) ⋅ Q

c

R2 =

2 ⋅ Π ⋅ C1 ⋅ F

C1 =

C2

=

TREBLE STAGE

The Treble stage is a simplehigh pass filter which
time constant is fixed by internalresistor (50Kohm
typ) and an external capacitorconnectedbetween
pins TREB_R/TREB_Land Ground.

IN-OUT PINS

The multiplexer output is available at OUT_R and
OUT_L pins for optional connection of external
graphic equalizer(TDA7316/TDA7317), surround
chip (TDA7346) etc. The signal is fed in again at
pins IN_L and IN-R. In case of applicationwithout
external devices the pins OUT_L/OUT_R and
IN_L/IN_R can be left unconnected if bit D3 byte
input selector is forced= 0 (DC connect)insteadif
bit D3 is kept =1 anexternaldecouplingcapacitor
must be provided between OUTR/INR and
OUTL/INR necessary to avoid signal DC jumps,
generating”Clicking” output noise.
The input impedance of the next volume stage is
44Kohm typical (minimum 31Kohm). A capacitor
no lower than1µF shouldbe used.

INPUT SELECTOR

The multiplexer selector can choose one of the
followinginputs:

- a differential CD stereo input.

- a mono input.

- fourstereoinput
The signal fed to the input pins must be decou-

pled via series capacitors. The minimum allowed
value depends on the correspondentinput imped­ance. For the CD diff input (Zi=10Kohm worst
case) a Cin=4.7uFis recommended.

16/23

TDA7437

Figure 8: Poweron Time Constant vs Cref

Capacitor C

V

(1V/div)

OUT LF

CREF

BWL TIME0.5s/DIV

REF

=4.7µF

D95AU380

2
1

Figure 10: Poweron Time Constant vs Cref Ca-

pacitor C

V

(1V)

REF

=22µF

D95AU382

Figure9: Poweron Time Constant vs Cref

Capacitor C

V

(1V/div)

OUT LF

CREF

BWL TIME0.5s/DIV

REF

=10µF

D95AU381

Figure12: SoftMute ON

2
1

OUT LF

CREF

BWL TIME1s/DIV

Figure 11: SVRRvs. Frequency

S

VRR

(dB)

-40

-50

-60

-70

-80

-90

47µF

22

µF

4.7µF

10

µ

F

D95AU383

VS=8V
Ripple=0.2VRMS
AV=-15dB

V

Main Menu

SOFT MUTE=ON SLOPE=FAST Vout=500mVrms

D95AU384

2
1

Pin Csm

V

Chan

= T/div

1ms 0.2V

Chan
1ms 2V

TIME

1ms

2

3

Vout

SOFT MUTE

CH1 9VDC CH1 0.5V

CH2 20mVx~
CH3 0.2V

CH4 20mV

x

~

10

10

x

=

10

x

10

-100
10 100 1K 10K Freq(Hz)

17/23

TDA7437

Figure 13: SoftMute OFF

SOFT MUTE=OFF SLOPE=FAST Vout=500mVrms

V

Main Menu

Pin Csm

V

Vout

CH1 9V DC

SOFT MUTE

D95AU387

TIME

Chan

2

1ms 0.2V

Chan

1

1ms 2V

Figure14: Zero Crossing Mute ON

Panel

STATUS

Memory
Save

PANEL
Recall
Auxiliary

Setups
Memory

Card
X-Y mode

Persistance
mode

Return

ZERO CROSSING MUTE = ON

V

LEFT

RIGHT

CH2 528mV DC

D95AU389

Figure15: Zero Crossing MuteOFF

Main Menu

Zoom

Multi
off

ZERO CROSSING MUTE = OFF

V

LEFT RIGHT

D95AU390

0.5ms 0.2V

x Chan 2

0.5ms 0.2V

TIME

x Chan 1

x Chan

0.2ms 1V

x Chan

0.2ms 0.5V

2

1

Figure 16: PauseDetector

PAUSE DETECTOR ZCW=160mV Cpause=100nF

V

Main Menu

18/23

Vout

CH2 4.12V DC

D95AU391

TIME

Chan

1

20ms 0.2V
Chan

2

20ms 2V

2ms

CH1 2.7V DC

Figure17: Pause Detector

PAUSE DETECTOR ZCW=160mV Cpause=100nF

Main Menu

Vout

CH2 4.08V DC

BWL

TIME

D95AU392

CH1 20mV
CH2 0.2Vx=

10

CH3 20mV
CH4 5mV

10

Chan 2
20ms 2V
Chan 3
20ms 0.2V

x

~

10

x

~

10

x

~ T/div 20ms

TDA7437

Figure 18: Sym_Bass

(dB)

10

5

0

-5

-10

-15
10 100 1K 10K Freq(Hz)

Figure 20: Loudness

ATT
(dB)

18
16
14
12
10

8
6
4
2
0

10 100 1K 10K Freq(Hz)

D95AU393

D98AU887

Figure19: Non_Sym_Bass

ATT
(dB)

10

5
0

-5

-10

-15

-20

-25
10 100 1K 10K Freq(Hz)

D95AU394

19/23

TDA7437

TEST BOARD DIAGRAM

CON1

GND V

CC

DIFG_R

DIFF_R

ST4_R

ST1_R

ST2_R

ST3_R

MONO

DIFG_L

DIFF_L

ST4_L

ST1_L

ST2_L

ST3_L

CON4

CON5

C17

22µF

C20 5.6nF

C21

2.2µF

C22 4.7nF

C23 4.7µF

C24 4.7µF

C25 470nF

C26 470nF

C27 470nF

C28 470nF

C29 470nF

C30 4.7nF

C31 4.7µF

C32 4.7µF

C33 470nF

C34 470nF

C35 470nF

C36 470nF

TRR

IN_R

O_R

LOUDR

DIFG_R

DIFF_R

ST4_R

ST1_R

ST2_R

ST3_R

MONO

LOUDR

DIFG_R

C18

100nF

C19

5.6nF

TRL

AGND43AVDD42DVDD41ADDR

44

1

2

3

4

5

6

7

8

9

10

11

12

13

14

DIFF_R

R4

2.7K

JP1JP2

C11

18nF

MIDRI30MIDRO27BASSRO26BASSRI

40 31

15

ST4_R

ST1_R

C10

22nF

16

17

ST2_R

ST3_R

C8

100nF

R3

5.6K

C7

100nF

CREF

39

25

24

23

22

20

21

38

28

37

36

34

33

18

19

CSM

PAUSE

C15

C1

10µF

2.2nF

32

29

35

OUTRR

BASSLO

BASSLI

MIDLO

MIDLI

I_L

O_L

SCL

SMEX

SDA

DGND

OUTLF

RF

LR

C16 22µF

C6 100nF

C5 100nF

C4 22nF

C3 18nF

C2

2.2µF

JP3

C14

C13

C12

C9

D98AU882

R5

R2

5.6K

R1

2.7K

CON2

SCL

SMEX

SDA

DGND

50

CON3

LF

RF

LR

RR

GND

20/23

TDA7437

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.60 0.063

A1 0.05 0.15 0.002

0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.30 0.37 0.45 0.012 0.014 0.018
C 0.09 0.20 0.004

0.008

D 12.00 0.472
D1 10.00 0.394
D3 8.00 0.315

e 0.80 0.031

E 12.00 0.472
E1 10.00 0.394
E3 8.00 0.315

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

K 0°(min.), 3.5°(typ.), 7°(max.)

OUTLINE AND

MECHANICAL DATA

TQFP44 (10 x 10)

D

D1

A1

2333

34

B

44

1

e

11

TQFP4410

22

E

E1

12

L

0.10mm
.004

Seating Plane

B

K

A

A2

C

21/23

TDA7437

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.45 0.096

A1 0.25

0.010

A2 1.95 2.00 2.10 0.077 0.079 0.083

B 0.30 0.45 0.012 0.018

c 0.13 0.23 0.005 0.009

D 12.95 13.20 13.45 0.51 0.52 0.53
D1 9.90 10.00 10.10 0.390 0.394 0.398
D3 8.00 0.315

e 0.80 0.031

E 12.95 13.20 13.45 0.510 0.520 0.530
E1 9.90 10.00 10.10 0.390 0.394 0.398
E3 8.00 0.315

L 0.65 0.80 0.95 0.026 0.031 0.037

L1 1.60 0.063

K0°(min.), 7°(max.)

OUTLINE AND

MECHANICAL DATA

PQFP44 (10 x 10)

D

D1

A1

33

34

B

44

1

e

23

11

PQFP44

22

L1

E

L

E3D3E1

12

0.10mm
.004

Seating Plane

B

K

A

A2

C

22/23

TDA7437

Purchase of I2C Componentsof STMicrolectronics, conveys a license under the Philips I2C Patent
Rights to use these components in an I

2

C system, provided that the system conforms to the I2C

Standard Specificationsas definedby Philips.

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publicationsupersedes and replaces all informationpreviously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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23/23