Datasheet TDA5153X, TDA5153BG Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA5153

Pre-amplifier for Hard Disk Drive
(HDD) with MR-read/inductive write
heads

Preliminary specification
File under Integrated Circuits, IC11

1997 Jul 02

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 QUICK REFERENCE DATA
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 Read mode

8.2 Write mode

8.3 Sleep mode

8.4 Standby mode

8.5 Active mode

8.6 Bi-directional serial interface

8.7 Addressing

8.8 Programming data

8.9 Reading data

8.10 Operation of the serial interface

8.10.1 Configuration

8.10.2 Power control

8.10.3 Head select

8.10.4 Servo write

8.10.5 Test

8.10.5.1 MR head test

8.10.5.2 Temperature monitor

8.10.5.3 Thermal asperity detector

8.10.6 Write amplifier programmable capacitors

8.10.7 High frequency gain attenuator pole register

8.10.8 High frequency gain boost register

8.10.9 Settle pulse

8.10.10 Address registers

8.11 Head unsafe

8.12 HUS survey
9 LIMITING VALUES
10 HANDLING
11 THERMAL RESISTANCE
12 RECOMMENDED OPERATION

CONDITIONS
13 CHARACTERISTICS
14 PACKAGE OUTLINE
15 SOLDERING
16 DEFINITION
17 LIFE SUPPORT APPLICATIONS

TDA5153

1997 Jul 02 2

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

1 FEATURES

• Designed for 4 (TDA5153BG) or 6 dual-stripe

MR-read/inductive write heads

• Current bias-current sense architecture

• Single supply voltage (5.0 V ±10%); a separate write

drivers supply pin can be biased from VCC to 8 V +10%

• MR elements connected to ground (GND)

• Equal bias currents in the two MR stripes of each head

• On-chip AC couplings eliminate MR head DC offset

• 3-wire serial interface for programming

• Programmable high-frequency zero-pole gain boost

• Programmable write driver compensation capacitance

• Programmable MR bias currents and write currents

• 1-bit programmable read gain

• Sleep, standby, active and test modes available

• Measurement of head resistances in test mode

• In test mode, one MR bias current may be forced to a

minimum current

• Short write current rise and fall times with near rail-to-rail

voltage swing

• Head unsafe pin for signalling of abnormal conditions

and behaviour

• Low supply voltage write-current inhibit (active or

inactive)

• Supports servo writing

• Provides temperature monitor

• Thermal asperity detection with programmable

threshold level

• Requires only one external resistor.

2 APPLICATIONS

• Hard Disk Drive (HDD).

TDA5153

3 GENERAL DESCRIPTION

The 5.0 V pre-amplifier for HDD described here is
designed for five terminals, dual stripe Magneto-Resistive
(MR)-read/inductive-write heads. The disks of the disk
drive are connected to ground. To avoid voltage
break-through between the heads and the disk, the MR
elements of the heads are also connected to ground. The
symmetry of the dual-stripe head-amplifier combination
automatically distinguishes between the differential
signals such as signals and the common-mode effects like
interference. The latter are rejected by the amplifier.

The IC incorporates read amplifiers, write amplifiers, serial
interface, digital-to-analog converters, reference and
control circuits which operate on a single supply voltage of
5V±10%. The output drivers have a separate supply
voltage pin which can be connected to a higher supply
voltage of up to 8 V +10%. The complementary output
stages of the write amplifier allow writing with near
rail-to-rail peak voltages across the inductive write head.

The read amplifier has a low input impedance. The DC
offset between the two stripes of the MR head is eliminated
using on-chip AC coupling. Fast settling features are used
to keep the transients short. As an option, the read
amplifier may be left biased during writing so as to reduce
the duration of these transients even more. Series
inductance in the leads between the amplifier and MR
heads influences the bandwidth which can be
compensated by using a programmable high-frequency
gain-boost (HF zero). HF noise and bandwidth can be
attenuated using a programmable high-frequency
gain-attenuator (HF pole).

On-chip digital-to-analog converters for MR bias currents
and write currents are programmed via a 3-wire serial
interface. Head selection, mode control, testing and servo
writing can also be programmed using the serial interface.
In sleep mode the CMOS serial interface is operational.
Figure 1 shows the block diagram of the device.

4 ORDERING INFORMATION

TYPE

NUMBER

TDA5153X − naked die −
TDA5153AG;

TDA5153BG

1997 Jul 02 3

NAME DESCRIPTION VERSION

LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

PACKAGE

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

5 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

V

CC(WD)

F noise figure R

V

nir

G

v(dif)

B

−3db

CMRR common mode rejection ratio;

PSRR power supply rejection ratio

t

, t

r

f

I

MR(PR)

I

WR(PR)(b-p)

f

SCLK

supply voltage 4.5 5.0 5.5 V
write drivers supply voltage V

=28Ω; IMR=10mA;

MR

T

=25°C; f = 20 MHz

amb

input referred noise voltage; see
note 3 in Chapter 13

RMR=28Ω; IMR=10mA;
T

=25°C; f = 20 MHz

amb

CC

− 3.0 3.2 dB

− 0.9 1.0 nV/√Hz

8.0 8.8 V

differential voltage gain from head inputs to RDx, RDy;

RMR=28Ω; IMR=10mA

d4 = logic 0 − 160 −
d4 = logic 1 − 226 −

−3 dB frequency bandwidth upper bandwidth without gain

− 220 − MHz

boost (4 nH lead inductance)
IMR= 10 mA; f < 1 MHz − 45 − dB

R

mismatch <5%

MR

I

= 10 mA; f < 100 MHz − 25 − dB

MR

f < 1 MHz − 80 − dB

(input referred);

mismatch <5%

R

MR

f < 100 MHz − 50 − dB

rise/fall times (10% to 90%) Lh= 150 nH; IWR=35mA;

f = 20 MHz

programming MR bias current R
programming write current

V
V

ext

R

ext

= 8.0 V −−1.8 ns

CC(WD)

= 6.5 V −−2.1 ns

CC(WD)

=10kΩ 5 − 20.5 mA
=10kΩ 20 − 51 mA

range (base-to-peak)
serial interface clock rate −−25 MHz

1997 Jul 02 4

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

6 BLOCK DIAGRAM

handbook, full pagewidth

WDlx
WDly

(1)

IWDlx

(1)

IWDly

HUS

R

ext

2
3

1

12

WRITE DRIVER

INPUT

HEAD UNSAFE

INDICATOR

LOW SUPPLY

VOLTAGE

INDICATOR

V

CC

11

TDA5153

FF

WRITE

CURRENT

SOURCE

VOLTAGE

REFERENCE

TDA5153

V

CC(WD)

(5 to 8 V)

48

(2)

15

(3)

6

(3)

6

(3)

6

WRITE DRIVER

AND

READ PREAMP

(3)

(6×)

, 20, 26,

33, 39, 44

(2)

14

, 19, 25,

32, 38, 43

(2)

nWy
nWx

(2)

+V

CC

4

R/W

SEN

RDx
RDy

7
5

6

9
10

SCLK

SDATA

Pin numbers correspond to TDA5153AG and TDA5153BG only. See Fig.3 and Chapter 7 for pinning of TDA5153X.
(1) Only available on naked die.
(2) Absent on TDA5153BG (4 channel version).
(3) 4 on TDA5153BG.

SERIAL

INTERFACE

20 kΩ

5

4
4

GND n

TAS

DETECTOR

4

head select

CURRENT

SOURCE

8, 13

5
3

(3)

6

R

MR

6

6

6

(3)

(3)

(3)

(2)

18

, 23, 29,

36, 42, 47

(2)

17

, 22, 28,

35, 41, 46

(2)

16

, 21, 27,

34, 40, 45

(2)

(2)

(2)

MGK422

nRy

nGND

nRx

Fig.1 Block diagram.

1997 Jul 02 5

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

7 PINNING

SYMBOL

HUS 1 1 1 head unsafe output
WDIx 2 2 2 write data input (differential; voltage input)
WDIy 3 3 3 write data input (differential; voltage input)
IWDIx −−4 write data input (differential; current input)
IWDIy −−5 write data input (differential; current input)

W 4 4 6 read/write (read = HIGH; write = LOW)

R/
SEN 5 5 7 serial bus enable
SDATA 6 6 8 serial bus data
SCLK 7 7 9 serial bus clock
GND1 8 8 10 ground connection 1
RDx 9 9 11 read data output (differential x − y)
RDy 10 10 12 read data output (differential x − y)
GND3 −−13 ground connection 3
V

CC

R

ext

GND2 13 13 16 ground connection 2
0Wx 14 − 17 inductive write head connection for head H0 (differential x − y)
0Wy 15 − 18 inductive write head connection for head H0 (differential x − y)
0Rx 16 − 19 MR-read head connection for head H0 (differential x − y)
0GND 17 − 20 ground connection for head H0
0Ry 18 − 21 MR-read head connection for head H0 (differential x − y)
n.c. − 14 − not connected
n.c. − 15 − not connected
n.c. − 16 − not connected
n.c. − 17 − not connected
n.c. − 18 − not connected
1Wx 19 19 22 inductive write head connection for head H1 (differential x − y)
1Wy 20 20 23 inductive write head connection for head H1 (differential x − y)
1Rx 21 21 24 MR-read head connection for head H1 (differential x − y)
1GND 22 22 25 ground connection for head H1
1Ry 23 23 26 MR-read head connection for head H1 (differential x − y)
n.c. 24 24 − not connected
2Wx 25 25 27 inductive write head connection for head H2 (differential x − y)
2Wy 26 26 28 inductive write head connection for head H2 (differential x − y)
2Rx 27 27 29 MR-read head connection for head H2 (differential x − y)
2GND 28 28 30 ground connection for head H2
2Ry 29 29 31 MR-read head connection for head H2 (differential x − y)
n.c. 30 30 − not connected

TDA5153AG TDA5153BG TDA5153X

PIN PAD

DESCRIPTION

11 11 14 supply voltage

12 12 15 10 kΩ external resistor

1997 Jul 02 6

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

SYMBOL

n.c. 31 31 − not connected
3Wx 32 32 32 inductive write head connection for head H3 (differential x − y)
3Wy 33 33 33 inductive write head connection for head H3 (differential x − y)
3Rx 34 34 34 MR-read head connection for head H3 (differential x − y)
3GND 35 35 35 ground connection for head H3
3Ry 36 36 36 MR-read head connection for head H3 (differential x − y)
n.c. 37 37 − not connected
4Wx 38 38 37 inductive write head connection for head H4 (differential x − y)
4Wy 39 39 38 inductive write head connection for head H4 (differential x − y)
4Rx 40 40 39 MR-read head connection for head H4 (differential x − y)
4GND 41 41 40 ground connection for head H4
4Ry 42 42 41 MR-read head connection for head H4 (differential x − y)
5Wx 43 − 42 inductive write head connection for head H5 (differential x − y)
5Wy 44 − 43 inductive write head connection for head H5 (differential x − y)
5Rx 45 − 44 MR-read head connection for head H5 (differential x − y);
5GND 46 − 45 ground connection for head H5
5Ry 47 − 46 MR-read head connection for head H5 (differential x − y)
n.c. − 43 − not connected
n.c. − 44 − not connected
n.c. − 45 − not connected
n.c. − 46 − not connected
n.c. − 47 − not connected
V

CC(WD)

GND4 −−48 ground connection 4

TDA5153AG TDA5153BG TDA5153X

PIN PAD

DESCRIPTION

48 48 47 supply voltage for the write drivers

1997 Jul 02 7

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

handbook, full pagewidth

HUS
WDIx
WDIy

R/W

SEN

SDATA

SCLK

GND1

RDx
RDy

V

CC

R

ext

CC(WD)

V
48

1
2
3
4
5
6
7
8

9
10
11
12

5Ry
47

5Rx

5GND
464544

TDA5153AG

5Wy

5Wx
43

4Ry
42

4GND
41

4Rx
40

4Wy
39

4Wx
38

n.c.

TDA5153

36

3Ry

35

3GND

34

3Rx

33

3Wy

32

3Wx

31

n.c.
n.c.

30
29

2Ry
2GND

28
27

2Rx

26

2Wy
2Wx

25

handbook, full pagewidth

HUS
WDIx
WDIy

R/W

SEN

SDATA

SCLK

GND1

RDx
RDy

V

CC

R

ext

13

14

151617

0Wx

0Wy

GND2

CC(WD)

n.c.

V

n.c.

48

47

46

1
2
3
4
5
6
7
8

9
10
11
12

0Rx

0GND

n.c.

n.c.

n.c.

45

44

43

TDA5153BG

18
0Ry

19

1Wx

4Ry
42

20

1Wy

4GND
41

21

1Rx

4Rx
40

4Wy
39

22

1GND

23

1Ry

4Wx
38

24 37

n.c.

n.c.

MGK424

36
35
34
33
32
31
30
29
28
27
26
25

3Ry
3GND
3Rx
3Wy
3Wx
n.c.
n.c.
2Ry
2GND
2Rx
2Wy
2Wx

13

14

15

16

17

n.c.

n.c.

n.c.

GND2

n.c.

Fig.2 Pin configurations.

1997 Jul 02 8

18
n.c.

19

1Wx

20

1Wy

21

1Rx

22

1GND

23

1Ry

24 37
n.c.

MGK420

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

handbook, full pagewidth

CC(WD)

5Ry

5GND

5Rx

5Wy

TDA5153X

GND4

HUS

WDIx

WDIy

IWDIx

IWDIy

R/W

SEN

SDATA

SCLK

V

48

47 46 45 44 43 42 41 40 39 38 37

1

2

3

4

5

6

7

8

9

5Wx

4Ry

4GND

4Rx

4Wy

4Wx

TDA5153

3Ry

36

3GND

35

3Rx

34

3Wy

33

3Wx

32

GND1

RDx

RDy

GND3

V

CC

R

ext

10

11

12

13

14

16 17 18 19 20 21 22 23 24 25 26

15

GND2

0Wx

0Wy

0Rx

0GND

0Ry

1Wx

1Wy

1Rx

Fig.3 TDA5153X pad configuration.

1GND

1Ry

31

30

29

28

27

MGK421

2Ry

2GND

2Rx

2Wy

2Wx

1997 Jul 02 9

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

8 FUNCTIONAL DESCRIPTION

8.1 Read mode

The read mode disables the write circuitry to save power
while reading. The read circuitry is de-activated for write,
sleep and standby modes. The read circuitry may also be
biased during write mode to shorten transients.
The selected head is connected to a multiplexed low-noise
read amplifier. The read amplifier has low-impedance
inputs nRx and nRy (n is the number of the head) and
low-impedance outputs RDx and RDy. The signal polarity
is non-inverting from x and y inputs to x and y outputs.

Ambient magnetic fields at the MR elements result in a
relative change in MR resistance

∆R

MR

--------------- ­R

MR

This change produces a current variation

∆R

MR

×

=

∆ I

MRIMR

where I

is the bias current in the MR element.

MR

The current variation is amplified to form the read data
output signal voltage, which is available at RDx − RDy.
AC coupling between MR elements and amplifier stages
prevents the amplifier input stages from overload by DC
voltages across the MR elements. A fast settling
procedure shortens DC settling transients.

An on-chip generated stable temperature reference
voltage (1.32 V), available at the R
across an external resistor (10 kΩ) to form a global
reference current for the write and the MR bias currents.
The MR bias current DACs are programmed through the
serial interface according to the following formula

MR

10 kΩ

------------------ ­2R

⋅

ext

I

(in mA), where d4 to d0 are bits (either logic 0 or logic 1).
At power-up, all bits are set to logic 0, which results in a
default MR current of 5 mA. The adjustable range of the
MR currents is 5 mA to 20.5 mA. The MR bias currents are
equal for the two stripes of each head. The gain amplifier
is 1-bit programmable. The amplifier gain can be set to its
nominal value or to the nominal value +3 dB.

8.2 Write mode

To minimize power dissipation, the read circuitry may be
disabled in write mode. The write circuitry is disabled in

,

--------------- ­R

MR

pin, is dropped

ext

10 16 d4⋅ 8d3⋅ 4d2⋅ 2d1⋅ d0+ ++++()=

TDA5153

read, sleep and standby modes. In write mode, a
programmable current is forced through the selected two
terminals inductive write head. The push-pull output
drivers yield near rail-to-rail voltage swing for fast current
polarity switching.

The differential write data input WDIx − WDIy is PECL
(Positive Emitter Coupled Logic) compatible. The write
data flip-flop can either be used or passed-by. In the case
that the write data flip-flop is used, current polarity is
toggled at the falling edges of the V

data=VWDIx

Switching to Write Mode initializes the data flip-flop so that
the write current flows in the write head from x to y. In the
case that the write data flip-flop is not used, the signal
polarity is non-inverting from x and y inputs to x and y
outputs.

The write current magnitude is controlled through on-chip
DACs. The write current is defined as follows:

10 kΩ

I

WR

----------------

20 16 d4⋅ 8d3⋅ 4d2⋅ 2d1⋅ d0+ ++++()=

R

ext

(in mA) where d4 to d0 are bits (either logic 0 or logic 1).
The adjustable range of the write current is 20 mA to
51 mA. At power-up, the default values
d4 = d3 = d2 = d1 = d0 = logic 0 are initialized,
corresponding to I

= 20 mA. IWR is the current provided

WR

by the write drivers: the current in the write coil and in the
damping resistor together. The static current in the write
coil is

I

WR

,

---------------- ­R

h

1

+

------ ­R

d

where R
R

d

is the resistance of the coil including leads and

h

is the damping resistor.

8.3 Sleep mode

In sleep mode, the device is accessible via the serial
interface. All circuits are inactive, except the circuits of the
CMOS serial interface and the circuit which forces the data
registers to their default values at power-up and which
fixes the DC level of RDx − RDy (required when operating
with more than one amplifier). Typical static current
consumption is −30 µA. Dynamic current consumption
during operation of the serial interface in the sleep mode
and owing to external activity at the inputs to the serial
interface is not included. In all modes including the sleep
mode, data registers can be programmed. Sleep is the
default mode at power-up. Switching to other modes takes
less than 0.1 ms.

− V

WDIy

.

1997 Jul 02 10

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

8.4 Standby mode

The circuit can be put in standby mode using the serial
interface. In standby mode, typical DC current
consumption is 330 µA. Transients from standby mode to
active mode are two orders of magnitude shorter than from
sleep mode to active mode. This is important in the case
of cylinder mode operation with multiple amplifiers.
All amplifiers can operate from standby mode and all head
switch times can be kept just as short as in the case of
operation with a single amplifier. Head switching times are
summarized in the switching characteristics.

8.5 Active mode

Active mode is either read mode or write mode depending
on the R/

8.6 Bi-directional serial interface

The serial interface is used for programming of the device
and for reading of status information. 16 bits (8 bits for
data and 8 for address) are used to program the device.
The serial interface requires 3 pins: SDATA, SCLK and
SEN. These pins (and R/
input R/W has an internal 20 kΩ pull-up resistor and the
SEN logic input has an internal 20 kΩ pull-down resistor.
Thus, in case the SEN line is opened, no data will be
registered and in case the R/W line is opened, the device
will never be in write mode.

SDATA: serial data; bi-directional data interface. In all
circumstances, the LSB is transmitted first.

SCLK: serial clock; 25 MHz clock frequency.
SEN: serial enable; data transfer takes place when SEN is

HIGH. When SEN is LOW, data and clock signals are
prohibited from entering the circuit.

Three phases in the communication are distinguishable:
addressing, programming and reading. Each
communication sequence starts with an addressing
phase, followed by either a programming phase or a
reading phase.

W pin.

W) are CMOS inputs. The logic

TDA5153

8.7 Addressing

When SEN goes HIGH, bits are latched in at rising edges
of SCLK. The first eight bits a7 to a0, starting with a0, are
shifted serially into an address register. If SEN goes LOW
before 16 bits have been received, the operation is
ignored. When more than 16 bits (address and data) are
latched in before SEN goes LOW, the first 8 bits are
interpreted as an address and the last 8 bits as data.
SEN should go HIGH at least 5 ns before the first rising
edge of SCLK. Data should be valid at least 5 ns before
and after a rising edge of SCLK. The bits a7 to a4
constitute the register address.To validate the
communication with the preamplifier, bits a1, a2 and a3
have to be programmed as (1, 0, 0).

If bit a0 = logic 0, a programming sequence starts.
If bit a0 = logic 1, reading data from the pre-amplifier can
start.

8.8 Programming data

If a0 = logic 0, the last eight bits d7 to d0 before SEN goes
LOW are shifted into an input register. Bits d6 and d7 are
don’t care. When SEN goes LOW, the communication
sequence is ended and the data in the input register is
copied in parallel to the data register that corresponds to
the decoded address a7 to a4. SEN should go LOW at
least 5 ns after the last rising edge of SCLK.

8.9 Reading data

Immediately after the IC detects that a0 = logic 1, data
from the data register (address a7 to a4) is copied in
parallel to the input register. Two wait clock cycles must
follow before the controller can start inputting data. At the
first falling edge of SCLK after the 2 wait rising edges of
SCLK, the LSB d0 is placed on SDATA line followed by d1
at the next falling edge of SCLK etc. If SEN goes LOW
before 8 address bits (a7 to a0) have been detected, the
communication is ignored.

1997 Jul 02 11

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

handbook, full pagewidth

SEN

SCLK

SDATA

>5 ns >5 ns

0d0a1 d1a2 d2a3 d3a4 d4a5 d5a6 a7 d6 d7

address data

TDA5153

MGK423

handbook, full pagewidth

SEN

SCLK

SDATA

Fig.4 Timing diagram of the serial interface operation; writing sequence (a0 = 0).

1d0a1 d1a2 d2a3 d3a4 d4a5 d5a6 a7

address data

wait

cycles

MGK419

Fig.5 Timing diagram of the serial interface operation; reading sequence (a0 = 1).

1997 Jul 02 12

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

8.10 Operation of the serial interface

data

=

ONFIGURATION

V

–

WDIxVWDIy

-------------------------------------­2

=28Ω. If d4 = logic 1, the

MR

8.10.1 C
d0

By default (d0 = logic 0), write data passes from the
write data input via the data flip-flop to the write driver.
The write driver toggles the current in the head at the
falling edges of

V

When d0 = logic 1, the flip-flop is not used. The signal
polarity is non-inverting from WDIx and WDIy to Wx and
Wy.

d1

By default (d1 = logic 0) the pre-amplifier senses PECL
write signals at WDIx and WDIy. d1 should remain
logic 0.

d2

By default, (d2 = logic 0) the write current is inhibited
under low supply voltage conditions. The write current
inhibit is made inactive by programming d2 to logic 1.

d3

By default (d3 = logic 0), in write mode low supply
voltage, open head, and other conditions are monitored
and flagged at HUS. If d3 = logic 1, HUS is LOW in write
mode and HIGH in read mode.

d4

The amplifier read gain may be programmed in the
configuration register. By default (d4 = logic 0), the read
gain is typically 160 with R
read amplifier typical gain is 3 dB higher (i.e. 226 if
RMR=28Ω).

TDA5153

If d1 = d0 = logic 1, the circuit goes in active mode, (read
or write mode depending on the R/

8.10.3 H

EAD SELECT

d2, d1 and d0 are used to select head H0 to H5 for the
6 channel version and to select head H1 to H4 for the
4 channel version.

8.10.4 S

ERVO WRITE

The circuit is prepared for servo writing. However, the chip
will not be guaranteed.

8.10.5 T

EST

d2 = d1 = d0 = logic 0. The circuit is not in test mode. This
is the default situation.

8.10.5.1 MR head test

d2 = logic 0, d1 = logic 0, d0 = logic 1. In read mode, the
voltages at Rx and Ry (at the top of the MR elements) of
the selected head are fed to RDx and RDy outputs. By
measuring the output voltages single-ended at two
different I

currents, the MR resistance can be accurately

MR

measured according to the following formula:

R

MRx

RDx1VRDx2

=

-------------------------------------- ­I

–

MRx1IMRx2

for the x side for instance.

V

–

Open head and head short-circuited to ground conditions
can therefore be detected.

d2 = logic 0, d1 = logic 1, d0 = logic 0. Same as before,
with the difference that I

is fixed to a minimum constant

MR2

value of 5 mA. Measuring in the same way as above with
I

> 5 mA, enables the detection of MR elements

MR1

connected together.

W input).

d5

In order to minimize the write-to-read recovery times,
the first stage of the read amplifier may be kept biased
during write mode. By default, (d5 = logic 0) the read
amplifier is powered-down during write mode, and the
fast settling procedure is activated after write-to-read
switching. If d5 = logic 1 the read amplifier is kept biased
during write mode, and the fast settling procedure still
occurs if the head is changed or the MR current is
re-programmed.

8.10.2 P

OWER CONTROL

By default d0 = d1 = logic 0, the pre-amplifier powers-up in
sleep mode. If d1 = logic 0, d0 = logic 1 or d1 = logic 1,
d0 = logic 0 the circuit goes in standby mode.

1997 Jul 02 13

8.10.5.2 Temperature monitor

d2 = logic 0, d1 = logic 1, d0 = logic 1. The temperature
monitor voltages are connected to RDx and RDy. The
output differential voltage depends on the temperature
according to: ,

dV 0.00364– T 1.7+×= 0 T 140 °C<<
The temperature may be measured with a typical precision
of 5 °C.

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

8.10.5.3 Thermal asperity detector

d2 = logic 1, d1 = don’t care, d0 = either logic or 1. Unlike
the above tests, the thermal asperity detection does not
use the RDx to RDy outputs. Thus, the reader is fully
operational. In case a thermal asperity is detected, it is
flagged at the HUS pin.

The threshold voltage for the thermal asperity detection is
2-bit programmable. These 2 bits consist of d0 (LSB) of
the test mode register (address = 0XXX0110), as the
MSB, and b2 of the compensation register
(address = 0XXX0111).

V

where d0 is d0 of test mode register and b2 is d2 of
capacitor compensation register.

8.10.6 WRITE AMPLIFIER PROGRAMMABLE CAPACITORS
By default (d2 = d1 = d0 = logic 0) the programmable

capacitors are zero. These capacitors are used to improve
the performance of the write amplifier according to the
write amplifier output load.

210 560 d0⋅ 280 b2⋅++()µV=

th

,

TDA5153

attenuator provides a pole which limits the bandwidth and
reduces the high-frequency noise. The HF pole can be
used in combination with the HF zero in order to boost the
HF gain locally and yet limit the very high frequency noise
enhancement.

8.10.8 H
By default (d3 = d2 = d1 = d0 = logic 0), the high

frequency gain boost is not active. The gain boost provides
a zero which allows to optimize the bandwidth of the read
amplifier and to correct for attenuation caused by series
inductances in the leads between the MR-heads and the
read amplifier inputs.

8.10.9 S
By default (d2 = d1 = d0 = logic 0) the settle pulse has a

nominal duration of 3 µs. Its value can be programmed
from 2.125 µs to 3 µs according to the following formula:

t

st

IGH FREQUENCY GAIN BOOST REGISTER

ETTLE PULSE

2

-------------------------------------------------------------------------­4d2⋅ 2d1⋅ 1d0⋅ 1+++()

1

µ s+=

8.10.7 H

By default (d3 = d2 = d1 = d0 = logic 0), the high
frequency gain attenuator is not active. The gain

8.10.10 A

A7 A6 A5 A4 A3 A2 A1 A0 DESCRIPTION

00000010configuration register:

00010010power control register:

00100010head select register:

IGH FREQUENCY GAIN ATTENUATOR POLE

REGISTER

DDRESS REGISTERS; note 1

d0 = 0: use data flip-flop; d0 = 1: by-pass data flip-flop
d1 = 0: the WDI inputs are PECL levels; d1 = 1: invalid
d2 = 0: write current inhibit active; d2 = 1: write current inhibit inactive
read mode: d3 = 0: HUS active; d3 = 1: HUS HIGH

write mode: d3 = 0: HUS active; d3 = 1: HUS LOW
d4 = 0: read gain nominal; d4 = 1: read gain nominal + 3 dB
d5 = 0: read amplifier OFF during write mode; d5 = 1: read amplifier ON

during write mode

(d1, d0) = (0, 0): sleep mode
(d1, d0) = (1, 0) or (0, 1): standby mode
(d1, d0) = (1, 1): active mode (write or read)

6 channels: (d2,d1,d0) = (0,0,0) to (1,0,1): H0 to H5
4 channels: (d2,d1,d0) = (0, 0, 1) to (1, 0, 0): H1 to H4

1997 Jul 02 14

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

A7 A6 A5 A4 A3 A2 A1 A0 DESCRIPTION

00110010

01000010

01010010servo write register:

01100010test mode register:

01110010compensation capacitor register:

10000010

10010010

10100010

11110011chip ID register:

a7a6a5a40011when a0 = 1, data from the register with address a7 to a4 is read out on

MR current DAC register:

10 kΩ

I

MR



0.5

× 10 16 d4⋅ 8d3⋅ 4d2⋅ 2d1⋅ 1d0⋅+++++()mA×=

----------------



R

ext

write current DAC register:

I

WR



----------------



R

ext

20 16 d4⋅ 8d3⋅ 4d2⋅ 2d1⋅ 1d0⋅+ ++++()mA×=

10 kΩ

(d0, d1) = (0, 0) = one head
(d0, d1) = (1, 1) = all heads

(d2,d1,d0) = (0,0,0) = not in test mode
(d2,d1,d0) = (0,0,1) = read head test (I
(d2,d1,d0) = (0,1,0) = read head test (I

MR1=IMR2

= 5 mA fixed)

MR2

(d2,d1,d0) = (0,1,1) = temperature monitor
(d2,d1,d0) = (1, X, d0) = thermal asperity detection

V

210 560 d0⋅ 280 b2⋅++()µV=

th

equivalent differential capacitance:

, see note 2

4d2⋅ 2d1⋅ 1d0⋅++()2pF×

high frequency gain attenuator register:

nominal pole frequency:

------------------------------------------------------------------------------ ­8d3⋅ 4d2⋅ 2d1⋅ 1d0⋅+++

800 MHz

high-frequency gain boost register:

nominal zero frequency:

------------------------------------------------------------------------------ ­8d3⋅ 4d2⋅ 2d1⋅ 1d0⋅+++

800 MHz

settle time register:

settle time:

ID 8 d3⋅ 4d2⋅ 2d1⋅ 1d0⋅+++=

2

t

st

-------------------------------------------------------------------------­4d2⋅ 2d1⋅ 1d0⋅ 1+++()

1

, d3 to d0 are preset to (0, 0, 1, 1)

SDATA

)

µ s+=

Notes

1. Not used bits in the registers (indicated by X) are don’t care. Default data, initialized at power-up, is zero in all
registers. For VCC< 2.5 V, the register contents are not guaranteed.

2. Vth programming uses both test mode register and compensation capacitor register. d0 in the formula above is the
LSB of the test mode register and b2 is the data bit d2 of the compensation register.

1997 Jul 02 15

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

8.11 Head unsafe

The HUS pin is an open-collector output. Consequently,
when the pin is not connected to an external pull-up
resistor, HUS is LOW. HUS pins can be connected
together in case of operation with more than one amplifier.
It is used to detect abnormal/unexpected operation.

Sleep mode: HUS is HIGH, to permit working with more
than one amplifier.

Standby mode: HUS is HIGH, to permit working with
more than one amplifier.

Read mode:

• if in the configuration register d3 = 1, HUS is HIGH

• if in the configuration register d3 = 0, HUS goes LOW

for:
–R

pin open, short-circuited to ground or to V

ext

(read current too low or too high)

– Low VCC and V

conditions. A low supply

CC(WD)

voltage detector is placed close to the VCC and
V

CC(WD)

pins.

Detection of low VCC (main general supply): a VCC supply
voltage below 4.0 V ±5% is flagged to the HUS pin.
The voltage detection range is then 4.2 to 3.8 V with an
hysteresis of 110 mV ±10%. Detection of low V
(writer dedicated supply): a fault will be flagged at HUS pin
if V

drops 0.8 V ±10% below VCC. One must be

CC(WD)

aware that such a detection is only aimed to warn for a
catastrophic situation. Indeed, V

should never be

CC(WD)

below VCC.

CC

CC(WD)

TDA5153

Test mode: HUS is HIGH except when the TAS detector
is ON. If a thermal asperity is detected, HUS goes LOW.

Servo write mode: HUS is LOW
Write mode:

• if in the configuration register d3 = 1, HUS is LOW

• if in the configuration register d3 = 0, HUS goes HIGH

for: the write current may be inhibited if d1 = 0 in the
configuration register.

–R

pin open, short-circuited to ground or to V

ext

(write current too low or too high)
– Write data input frequency too low (WDIx − WDIy)
– Write head Wx − Wy open, Wx or Wy short-circuited

to ground (switching to write mode makes HUS LOW;

after the transient the HUS detection circuitry is

activated; the target for the head-open detect time is

15 ns)
– Write-head still left biased while not selected
– Low VCC and V

conditions (write current inhibit

CC(WD)

can be active or inactive).

The same detector is used for read and write mode. HUS
goes LOW again between 0.5 and 1 µs after the last
unsafe condition was detected.

CC

8.12 HUS survey HUS DATA BIT D3

MODE STATE 0 1

Sleep mode −− HIGH HIGH

Standby mode −− HIGH HIGH

Read mode ACTIVE HIGH

(1)

(1)
(2)

HIGH HIGH

HIGH HIGH
LOW LOW

Active mode

Read

Write

A-test mode
TAS mode ACTIVE ACTIVE
Write mode ACTIVE LOW
A-test mode
Servo mode

Notes

1. HUS survey: A-test mode = analog test mode.

2. In servo mode, the performance of the IC is not guaranteed.

1997 Jul 02 16

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

V

CC(WD)

V

IL

V

IH

V

n1

V

n2

V

n3

I

nGND

T

stg

T

j

supply voltage −0.5 +6.0 V
write driver supply voltage −0.5 +9.5 V
LOW level digital input voltage −0.5 +5.5 V
HIGH level digital input voltage −0.5 +5.5 V
voltage on all pins except VCC, read inputs nRx, nRy and

−0.5 +5.5 V

write outputs nWx, nWy (n = 0 to 9)

but not higher than − V

+ 0.5 V

CC

voltage on write driver outputs nWx, nWy −0.5 +8.8 V

but not higher than − V

CC(WD)

+ 0.8 V
voltage on read inputs nRx, nRy −0.5 1 V
current through pins nGND − 0.1 A
storage temperature −65 +150 °C
junction temperature − 150 °C

10 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS device.

11 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITION VALUE UNIT

R

th j-a

thermal resistance from junction to ambient

TDA5153AG, TDA5153BG in free air 70 K/W
TDA5153X see note 1

Note

1. The TDA5153X is shipped in naked dies. The thermal resistance depends on the flex used.

1997 Jul 02 17

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

12 RECOMMENDED OPERATION CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT

V

CC

V

CC(WD)

V

IH

V

IL

V

i(dif)(p-p)

V

IH(PECL)

V

IL(PECL)

T

amb

T

j

R

MR

∆R

MR

L

l(tot)

R

l(tot)

V

MR

V

sig(dif)(p-p)

L

wh

R

wh

C

wh

R

ext

supply voltage range note 1 4.5 − 5.5 V
write driver supply voltage note2 V

CC

HIGH level input voltage (CMOS) 3.5 − V

− 8.8 V

CC

V
LOW level input voltage (CMOS) 0 − 0.8 V
differential input voltage

note 3 0.4 0.7 1.5 V

(peak-to-peak value)
HIGH level PECL input voltage note 3 1.5 2.85 V

CC

V
LOW level PECL input voltage note 3 − 2.15 − V
ambient temperature 0 − 70 °C
junction temperature reading −−110 °C

writing (V

=8V) −−130 °C

CC(WD)

MR element resistance 15 28 34 Ω
RMR mismatch note 4 −−4Ω
total lead inductance to the head in each lead; note 5 − 35 − nH
total lead resistance to the head in each lead; note 5 − 1.5 −Ω
voltage on top of MR elements note 6 −−0.5 V
differential MR head input signal

0.4 1 2 mV

(peak-to-peak value)
write head inductance including lead; note 5 − 0.15 −µH
write head resistance including lead; note 5 − 10 −Ω
write head capacitance including lead; note 5 − 5 − pF
external reference resistor − 10 − k Ω

V

I

ref

ref

=

---------- ­R

ext

Notes

1. A supply by-pass capacitor from VCC to ground or a low-pass filter may be used to optimize the PSRR.

2. The supply voltage V

must never be below VCC in normal mode, and two diode voltages above VCC in servo

CC(WD)

mode.

3. The given values should be interpreted in such a way that the single-ended voltage could swing 0.2 to 0.75 V and
that the common mode voltage should be such that for any of the two states, V

IH(max)<VCC

and V

IL(min)

> 1.5 V.

PECL voltage swing: a wider peak-to-peak voltage swing can be used. In that case a current will flow through the
WDI inputs. This current is approximately equal to

WDIx WDIy–()1.4–

----------------------------------------------------------­200

4. The mismatch refers to the resistance of the two stripes of the same head. This is defined as follows:
∆R

MR

= R

MR1

− R

MR2



5. These parameters depend on the head model. The values given are those used for testing.

6. The combination of maximum head resistance, lead resistance and bias current is not permitted. To avoid voltage
break-through between heads and disk, the voltage over the MR elements is limited by two diodes.

1997 Jul 02 18

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

13 CHARACTERISTICS

= 5.0 V; V

V

CC

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Read characteristics

I

MR

∆I

MR

G

v(dif)

R

i(dif)

C

i(dif)

THD total harmonic distortion − 1 − %
B

L

B

H

F noise figure; note 3 RMR=28Ω; IMR= 10mA;

V

nir

f

B(L)

f

B(H)

α

cs

PSRR power supply rejection ratio; note 5 f < 1 MHz; I

CMRR common mode rejection ratio;

DR rejection of SCLK and SDATA;

V

O(R)(dif)

Z

o(R)

=8V; V

CC(WD)

MR current adjust range R
tolerance (excluding R

IMRI

–

MR(PR)

--------------------------------- ­I

MR(PR)

MR(PR)

=10mA

with I

GND

=0V; T

)

ext

=25°C; unless otherwise specified.

amb

=10kΩ; 0.5 mA steps 5 − 20.5 mA

ext

−±4−%

differential voltage gain; note 1 from head inputs to RDx, RDy;

RMR=28Ω; IMR=10mA;
f = 20 MHz;

d4 = 0 − 160 −

d4 = 1 − 226 −
differential input resistance IMR=10mA − 13 −Ω
differential input capacitance − 16 − pF

signal gain pass band edge; note 2 −3dB −−100 kHz
signal gain pass band edge without

gain boost; note 2

−3 dB (4 nH lead inductance) − 220 − MHz

−3 dB (50 nH lead inductance) − 170 − MHz

− 3.0 3.2 dB

T

=25°C; f = 20 MHz

amb

input referred noise voltage; note 3 RMR=28Ω; IMR= 10mA;

T

=25°C; f = 20 MHz

amb

+3 dB noise low corner frequency RMR=28Ω; IMR= 10 mA;

T

=25°C; no lead

amb

− 0.9 1.0 nV/√Hz

− 400 kHz

inductance

+3 dB noise upper corner
frequency

RMR=28Ω; IMR= 10 mA;
T

=25°C; no lead

amb

− 220 MHz

inductance

channel separation; note 4 unselected head − 50 dB

=10mA − 80 dB

MR

f < 100 MHz; I

=10mA − 50 dB

MR

from nRx − nRy to RDx − RDy;

note 5

R

mismatch < 5%;

MR

IMR= 10 mA;

f<1MHz − 45 dB

f < 100 MHz − 25 dB

note 6
output DC offset voltage in read

mode (differential after DC settling)

from SCLK, SDATA inputs to
the RDx − RDy outputs; note 7

DC voltage between
RDx − RDy (in read mode)

− 50 dB

−−±0.2 V

output impedance in read mode single ended − 16 −Ω

1997 Jul 02 19

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

o(max)(dif)

V

o(cm)

∆V

ocm

---------------­∆V

CC

Z

o(n)(dif)

Write characteristics

I

WR

∆I

WR

V

s(max)(p-p)

R

o(dif)

, t

t

r

f

t

as

t

pd

α

cs

Switching characteristics

f

SCLK

∆V

o(cm)

t

rec(W-R)

t

sw(R)

t

off(R)

maximum differential output

− 4 − mA

current
common mode output voltage in

RDx, RDy 1.0 1.5 2.0 V

read mode
common mode DC supply rejection

− 20 − dB

in read mode

differential output impedance in

− 50 − kΩ

other modes (write, standby, sleep)

write current adjust range (in the

R

=10kΩ; 1 mA steps 20 35 51 mA

ext

write drivers)
tolerance (excluding R

–

I

WRIRW(PR)

----------------------------------- ­I

RW(PR)

maximum voltage swing
(peak-to-peak value)

ext

);

I

V
V

=35mA −±7−%

WR(PR)

=5V −−8V

CC(WD)

= 8 V (differential) −−13 V

CC(WD)

differential output resistance − 200 −Ω
write current rise/fall time without

flip-flop (10% to 90%); note 8

V

=8V; Lh= 150 nH,

CC(WD)

Rh=10Ω; IWR= 35 mA;

−− 1.8 ns

f = 20 MHz

write current asymmetry; note 9 percentage of tr/t

f

−−5%

(tr, tf and logic asymmetry)

propagation delay 50% of
(WDIx/WDIy) to 50% of (Wx, Wy)

write head short circuited; data
flip-flop by passed

−−5ns

channel separation unselected head − 45 − dB

serial interface clock rate −−25 MHz
output common mode DC voltage

IMR= 10 mA; IWR=35mA − 200 − mV

change from Read to Write modes
write to read recovery time

(AC and DC settling); note 10

from 50% of the rising edge of
R/W to steady state read-back
signal: AC and DC settling at
90% (without load at
RDx − RDy)

read amplifier OFF: d5 = 0 − 3 4.5 µs
read amplifier ON: d5 = 1 − 100 150 µs

head switching (in read mode),
standby to read active and MR
current change recovery time;

from falling edge of SEN to
steady state read-back signal;
(without load at RDx − RDy)

− 3 4.5 µs

(AC and DC settling); note 11
read amplifier off time from falling edge of R/W to

−−50 ns

read head inactive

1997 Jul 02 20

Philips Semiconductors Preliminary specification







Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

st(W)

t

off(W)

t

sw(W)

t

sw(S)

DC characteristics

I

CC(R)

I

CC(W)

I

DD(stb)

I

DD(S)

V

ref

write settle times; note 12 from 50%of the falling edge of

−−70 ns
R/W to 90% of the steady state
write current (in Write Mode)

write amplifier off time from rising edge of R/W to

−−50 ns
IWR-programmed /10
(IWR= 35 mA)

head switching (in write mode),
and standby to write head active

sleep to (and from) any other

from falling edge of SEN to
write head active

− 50 70 ns

−−100 µs

modes

supply current; note 13 read mode; IMR=10mA − 72 80 mA
supply current; note 14 write mode; IWR=35mA

from V
from V

(5 V) − 33 41 mA

CC

(5 to 8 V) − 54 61 mA

CC(WD)

standby mode supply current − 0.25 1 mA
sleep mode supply current static − 0.025 − mA
reference voltage for R

ext

− 1.32 − V

Notes to the characteristics

1. The differential voltage gain depends on the MR
resistance. It can be improved by programming the
d4 bit in the configuration register using the serial
interface.

2. The gain boost implements a pole-zero combination:
The +3 dB gain boost corner frequency is

------------------------------------------------------------------------------------­8d3⋅ 4d2⋅ 2d1⋅ 1d0⋅+++()

800 MHz

The −3 dB gain attenuation corner frequency is

------------------------------------------------------------------------------------­8d3⋅ 4d2⋅ 2d1⋅ 1d0⋅+++()

800 MHz

where d3, d2, d1, d0 are bits (0, 1) to be programmed
via the Serial Interface. In practical use, the bandwidth
is limited by the inductance of the connection between
the MR heads and the pre-amplifier.

3. Noise calculation
a) Definitions: The amplifier has a low-ohmic input.

No lead resistance is taken into account. The input
referred noise voltage, excluding the noise of the
MR resistors, is defined as follows:

2

V

nir

where G

no



-------- ­G



is the voltage gain and Vno is the noise

v

v

4kT R

+()× V–=

MR1RMR2

2

V

voltage at the output of the amplifier, k is the

Boltzmann constant and T is the temperature in K.
The noise figure is defined as follows:

2

V

no




F 10 log

× dB=




----------------------------------------------------------- ­4kT R



-------- ­G



v

+()×

MR1RMR2



in 1 Hz bandwidth. Note that R

includes all

MR

resistances between Rx or Ry to ground.

b) Noise figure versus I

and RMR: Table 1 shows

MR

the variation of the noise figure with IMR (mA) and
RMR (Ω).

c) Input noise voltage consideration: the input

referred noise voltage calculation can significantly
be different (from 1.0 to 0.44 nV/√Hz for instance)
by taking into account an equivalent
signal-to-noise ratio when using two MR stripes
(28 Ω for each stripe) or one MR stripes (42 W).

It assumes that the signal coming from the head is
larger for a dual stripe head than for a single stripe
head (50% extra signal for dual stripe head).

4. The channel separation is defined by the ratio of the
gain response of the amplifier using the selected head
H(n) to the gain response of the amplifier using the
adjacent head H(n ±1), Head H(n) being selected.

1997 Jul 02 21

Philips Semiconductors Preliminary specification





Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

5. The PSRR (in dB) is defined as input referred ratio:
G

v

PSRR 20 log

Where Gv is the differential input to differential output
gain, and G
gain. The CMRR (in dB) is defined as input referred

CMRR 20 log

ratio:
where G

gain and G

is the differential input to differential output

v

cm

output gain. Flex and board lay-out may affect
significantly these parameters.

6. This refers to the crosstalk from SCLK and SDATA

inputs via the read inputs to RDx − RDy. Two cases
can be distinguished:

a) With SEN LOW, SCLK and SDATA are prohibited

from entering the device and crosstalk is low.

b) Programming via the serial interface is done with

SEN HIGH. Then crosstalk can occur. A careful
design of the board or flex-foil is required in order
not to get crosstalk via this path.

7. A 200 mV peak-to-peak signal is applied to SCLK or

SDATA inputs at 25 MHz, and measurement is
performed at RDx − RDy.



×=

------­G



p

is the power supply to differential output

p

G

v



×=

---------- ­G



cm

is the common mode input to differential

TDA5153

8. The rise and fall times depend on the write
amplifier-write head combination. L
the components on the evaluation board. Parasitic
capacitances also limit the performance.

9. The write current rise/fall time asymmetry is defined by

–

t

rtf

-----------------------

+()

2t

rtf

10. Write-to-read recovery time includes the write mode to
read mode switching using the R/
head (see Fig.6). The AC signal reaches its full
amplitude few tenth of ns after appearing at the reader
RDx and RDy outputs.

11. In read mode, the head switching, standby to read
active switching and changing MR current include fast
current settling (see Fig.7). Same note regarding the
AC signals at the reader outputs as above.

12. Write settle time includes read mode to write mode
switching using the R/W pin.

13. The typical supply current in read mode depends on
the bias current for the MR element.

14. The typical supply current in write mode also depends
on the write current.

and Rh represent

h

W pin on the same

Table 1 Noise figure

RMR(Ω)

20 2.7 2.9 3.1
25 2.8 3.0 3.3
30 2.9 3.1 3.5

F (dB)

IMR= 7 mA IMR=10mA IMR=15mA

1997 Jul 02 22

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

handbook, full pagewidth

R/W

RDx-RDy

t

rec(W-R)

t

off(R)

TDA5153

MGG985

handbook, full pagewidth

Fig.6 Timing diagram of the reader: write-to-read switching on the same logic head.

SEN

RDx-RDy

t

sw(R)

MGG986

Fig.7 Timing diagram of the reader: typical head, current and standby-to-read characteristics.

1997 Jul 02 23

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

14 PACKAGE OUTLINE

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

c

y

X

36

37

25

Z

24

E

A

TDA5153

SOT313-2

e

w M

pin 1 index

48

1

e

DIMENSIONS (mm are the original dimensions)

mm

A

A1A2A3bpcE

max.

0.20

0.05

1.45

1.35

1.60

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

b

p

0.25

w M

D

H

D

0.27

0.17

12

Z

D

(1) (1)(1)

D

0.18

7.1

0.12

6.9

b

p

13

v M

B

v M

0 2.5 5 mm

scale

(1)

eH

H

7.1

6.9

0.5

9.15

8.85

D

E

A

B

9.15

8.85

H

E

LLpQZywv θ

E

0.75

0.45

A

2

A

A

1

detail X

0.69

0.59

0.12 0.10.21.0

Q

(A )

3

θ

L

p

L

Z

E

D

0.95

0.55

0.95

0.55

o

7

o

0

OUTLINE
VERSION

SOT313-2

IEC JEDEC EIAJ

REFERENCES

1997 Jul 02 24

EUROPEAN

PROJECTION

ISSUE DATE

93-06-15
94-12-19

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

15 SOLDERING

15.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

15.2 Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

15.3 Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

(order code 9398 652 90011).

TDA5153

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Jul 02 25

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)

TDA5153

with MR-read/inductive write heads

16 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1997 Jul 02 26

Philips Semiconductors Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

NOTES

TDA5153

1997 Jul 02 27

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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
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© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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Printed in The Netherlands 297027/25/01/pp28 Date of release: 1997Jul 02 Document order number: 9397 750 01904