Datasheet TDA4886A Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA4886A

140 MHz video controller with

2

I

C-bus

Product specification
File under Integrated Circuits, IC02

1998 Dec 04

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 QUICK REFERENCE DATA
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION

7.1 Signal input stage (input clamping, blanking
and clipping)

7.2 Electronic potentiometer stages

7.3 Output stage

7.4 Pedestal blanking

7.5 Output clamping, feedback references and
DAC outputs

7.6 Clamping and blanking pulses

7.7 On Screen Display (OSD)

7.8 Subcontrast adjustment, contrast modulation
and beam current limiting

7.9 I2C-bus control

7.10 I2C-bus data buffer

8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 CHARACTERISTICS
11 I2C-BUS PROTOCOL
12 TEST AND APPLICATION INFORMATION

12.1 Test boards

12.2 Recommendations for building the application
board

13 INTERNAL CIRCUITRY
14 PACKAGE OUTLINE
15 SOLDERING

15.1 Introduction to soldering through-hole mount
packages

15.2 Soldering by dipping or by solder wave

15.3 Manual soldering

15.4 Suitability of through-hole mount IC packages
for dipping and wave soldering methods

16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
18 PURCHASE OF PHILIPS I2C COMPONENTS

TDA4886A

1998 Dec 04 2

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

1 FEATURES

• 140 MHz pixel rate

• 2.8 ns rise time, 3.8 ns fall time

• I2C-bus control

• I2C-bus data buffer for synchronization of adjustments

• Grey scale tracking

• On Screen Display (OSD) mixing with 50 MHz pixel rate

• OSD contrast

• Negative feedback for DC-coupled cathodes

• Especially for AC-coupled cathodes

– Black level adaptable to kind of post amplifier
– Internal positive feedback
– DAC outputs for black level restoration.

• Integrated black level storage capacitors

• Beam current limiting

• Subcontrast/contrast modulation

• Pedestal blanking

• Sync clipping.

TDA4886A

2 GENERAL DESCRIPTION

The TDA4886A is a monolithic integrated RGB
pre-amplifier for colour monitor systems (e.g. 15" and 17")
with I2C-bus control and OSD. In addition to bus control,
beam current limiting and contrast modulation are
possible. The signals are amplified in order to drive
commonly used video modules or discrete solutions.
Individual black level control with negative feedback from
the cathode (DC coupling) or gradually adaptable black
level control with positive feedback and 3 DAC outputs for
external cut-off control (AC coupling) is possible.

With special advantages the circuit can be used in
conjunction with the TDA485X monitor deflection IC
family.

3 ORDERING INFORMATION

TYPE

NUMBER

TDA4886A SDIP24 plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1

NAME DESCRIPTION VERSION

PACKAGE

1998 Dec 04 3

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

P

I

P

V

P1,2,3

I

P1,2,3

V

i(b-w)

supply voltage (pin 7) 7.6 8.0 8.8 V
supply current (pin 7) − 21 25 mA
channel supply voltage (pins 21, 18 and 15) 7.6 8.0 8.8 V
channel supply current (pins 21, 18 and 15) − 21 25 mA
input voltage

− 0.7 1.0 V

(black-to-white value; pins 6, 8 and 10)

V

o(b-w)

V

o(b-w)(max)

V

o

V

bl(DC)

nominal output voltage swing
(black-to-white value; pins 22, 19 and 16)

maximum output voltage swing
(black-to-white value; pins 22, 19 and 16)

output voltage level (pins 22, 19 and 16) 0.05 − VP− 1V
typical reference black level for DC coupling

nominal contrast;

− 2.8 − V

maximum gain
maximum contrast;

− 4.54 − V

maximum gain

control bit FPOL = 0 0.5 − 2.5 V

(pins 22, 19 and 16)

V

bl(AC)

typical reference black level for AC coupling
(pins 22, 19 and 16)

control bit FPOL = 1 and
PEDST = 0

BLH2 = 0; BLH1 = 0 − 0.77 − V
BLH2 = 0; BLH1 = 1 − 1.01 − V
BLH2 = 1; BLH1 = 0 − 1.25 − V
BLH2 = 1; BLH1 = 1 − 1.49 − V

I

o(sink)

I

o(source)

peak output sink current during fast signal transients −−20 mA

peak output source current during fast signal transients −40 −− mA
B bandwidth −3 dB (small signal) − 165 − MHz
t

r(o)

video rise time at signal outputs

− 2.8 − ns

(pins 22, 19 and 16)
t

f(o)

video fall time at signal outputs

− 3.8 − ns

(pins 22, 19 and 16)
dV

o

overshoot at signal outputs

minimum rise time 8 17 30 %

(pins 22, 19 and 16)

α

C
TR

ct(f)

C

o

crosstalk suppression by frequency f = 50 MHz 25 −− dB

contrast control related to nominal contrast −28 − +4.2 dB

tracking of output signals for contrast

− 0.0 0.5 dB

variation from maximum to minimum
G

C

BC brightness control (typical black level

gain control related to maximum gain −7.3 − 0dB

−10 − +30 %
voltage change related to nominal output
signal amplitude)

V

o(OSD)(max)

maximum OSD output voltage swing related
to nominal output voltage swing

maximum OSD contrast;
maximum gain

− 120 − %

(pins 22, 19 and 16)

C

OSD

OSD contrast control related to maximum

−12 − 0dB
OSD contrast

1998 Dec 04 4

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1998 Dec 04 5

book, full pagewidth

5 BLOCK DIAGRAM

140 MHz video controller with I

Philips Semiconductors Product specification

LIM

V

V

V

I1

I2

I3

24

6

8

10

input clamping

REGISTER

INPUT
CLAMPING
BLANKING

INPUT
CLAMPING
BLANKING

INPUT
CLAMPING
BLANKING

DISO

SDA SCL

12 13

6

I2C-BUS

PEDST
DISO
DISV
FPOL
BLH1
BLH2

fast

blanking

FBL OSD1OSD2OSD

CONTRAST MODULATION

OSD INPUT

1234

SUBCONTRAST

LIMITING

CONTRAST

CONTRAST

CONTRAST

3

6

6-BIT

DAC

OSD

CONTRAST

OSD

CONTRAST

OSD

CONTRAST

4 6 6 6 6

4-BIT

DAC

6-BIT

DAC

BRIGHTNESS

BLANKING

BRIGHTNESS

BRIGHTNESS

BRIGHTNESS

INPUT CLAMPING

VERTICAL BLANKING

511

6-BIT

DAC

GAIN

GAIN

GAIN

vertical
blanking

6-BIT

DAC

6-BIT

DAC

PEDESTAL
BLANKING

PEDST

PEDESTAL
BLANKING

PEDST

PEDESTAL
BLANKING

PEDST

blanking

TDA4886A

output
clamping

BLANKING

OUTPUT CLAMPING

HFBCLI

8

8-BIT

DAC

8

8-BIT

DAC

8

8-BIT

DAC

FPOL

FPOL
FPOL

FPOL
FPOL

FPOL

DISV

BLH2

BLH1

CHANNEL 1

REFERENCE

CHANNEL 2

REFERENCE

CHANNEL 3

REFERENCE

SUPPLY

V

P

FPOL

FPOL

FPOL

79

GND

21

22

23
18

19

20
15

16

17
14

MHB264

V

P1

V

O1

FB/R
V

P2

V

O2

FB/R
V

P3

V

O3

FB/R
GNDX

2

1

2

3

C-bus

TDA4886A

Fig.1 Block diagram.

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

6 PINNING

SYMBOL PIN DESCRIPTION

FBL 1 fast blanking input for OSD insertion
OSD

1

OSD

2

OSD

3

CLI 5 input clamping; vertical blanking

V

I1

V

P

V

I2

GND 9 ground
V

I3

HFB 11 horizontal flyback input

SDA 12 I2C-bus serial data input/output
SCL 13 I
GNDX 14 ground channels 1, 2 and 3
V

P3

V

O3

FB/R

3

V

P2

V

O2

FB/R

2

V

P1

V

O1

FB/R

1

LIM 24 subcontrast, contrast modulation,

2 OSD input channel 1
3 OSD input channel 2
4 OSD input channel 3

input
6 signal input channel 1
7 supply voltage
8 signal input channel 2

10 signal input channel 3

(output clamping, blanking)

2

C-bus clock input

15 supply voltage channel 3
16 signal output channel 3
17 feedback input/reference voltage

output channel 3

18 supply voltage channel 2
19 signal output channel 2
20 feedback input/reference voltage

output channel 2

21 supply voltage channel 1
22 signal output channel 1
23 feedback input/reference voltage

output channel 1

beam current limiting input

handbook, halfpage

FBL

1

OSD

2

1

OSD

3

2

OSD

4

3

CLI

5

V

6

I1

TDA4886A

V

7

P

V

8

I2

GND

9

V

10

I3

HFB

11

SDA

12

MHB265

Fig.2 Pin configuration.

TDA4886A

LIM

24

FB/R

23

1

V

22

O1

V

21

P1

FB/R

20

2

V

19

O2

V

18

P2

FB/R

17

3

V

16

O3

V

15

P3

GNDX

14

SCL

13

1998 Dec 04 6

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

7 FUNCTIONAL DESCRIPTION

See block diagram (Fig.1) and definition of levels and
output signals (see Chapter “Characteristics” notes 1 to 3;
Figs 3 to 6).

7.1 Signal input stage (input clamping, blanking and clipping)

The RGB input signals with nominal signal amplitude of

0.7 V are capacitively coupled into the TDA4886A from a

low-ohmic source (75 Ω recommended) and actively
clamped to an internal DC voltage during signal black
level. Because of the high-ohmic input impedance of the
TDA4886A the coupling capacitor (which also functions as
a storage capacitor between clamping pulses) can be
relatively small (10 nF recommended). Very small input
currents will discharge the coupling capacitor resulting in
black output signals for missing input clamping pulses.

Composite signals will not disturb normal operation
because a clipping circuit cuts all signal parts below
black level.

A fast signal blanking stage belongs to the input stage
which is driven by several blanking pulses (see Section
“Clamping and blanking pulses”) and control bit DISV = 1.
During the off condition the internal reference black level
will be inserted instead of the input signals.

7.2 Electronic potentiometer stages

7.2.1 C

ONTRAST CONTROL (DRIVEN BY I

6-

BIT DAC)

The input signals related to the internal reference black
level can be simultaneously adjusted by contrast control
with a control range of typically 32 dB. The nominal
contrast setting is defined for 26H (4.2 dB below
maximum).

7.2.2 B

RIGHTNESS CONTROL (DRIVEN BY I

BIT DAC)

6-

With brightness control the video black level will be shifted
in relation to the reference black level simultaneously for
all three channels. With a negative setting (maximum 10%
of nominal signal amplitude) dark signal parts will be lost in
ultra black while for positive settings (maximum 30% of
nominal signal amplitude) the background will alter from
black to grey. The nominal brightness setting (10H) is no
shift. The brightness setting is also valid for OSD signals.
During blanking and output clamping the video black level
will be blanked to reference black level (brightness
blanking).

2

C-BUS,

2

C-BUS,

TDA4886A

7.2.3 G

AIN CONTROL (DRIVEN BY I

AND GREY SCALE TRACKING

Gain control is used for white point adjustment (correction
for different voltage to light amplification of the three colour
channels) and therefore individual for the three channels.
The video signals related to the reference black level can
be gain controlled within a range of typically 7.3 dB.
The nominal setting is maximum gain. The video signal is
the addition of the contrast controlled input signal and the
brightness shift. The gain setting is also valid for OSD
signals, thus the complete ‘grey scale’ is effected by gain
control.

7.3 Output stage

In the output stage the nominal input signal will be
amplified to 2.8 V output colour signal at nominal contrast
and maximum gain. The maximum input to output
amplification at maximum contrast and gain settings is

16.2 dB. By output clamping the reference black level
can be adjusted. In order to achieve fast rise and fall times
of the output signals with minimum crosstalk between the
channels, each output stage has its own supply voltage
pin.

7.4 Pedestal blanking

For the video portion the reference black level should
correspond to the ‘extended cut-off voltage’ at the
cathode. Nevertheless during vertical flyback retrace lines
may be visible, though blanking to spot cut-off is useful.
With control bit PEDST = 1 the pedestal black level will be
adjusted by output clamping instead of the reference black
level (see Fig.5). The pedestal black level is more negative
than the video black level at minimum brightness setting
and the voltage difference to reference black level is fixed.

7.5 Output clamping, feedback references and DAC outputs

The aim of the output clamping (pins FB/R
and FB/R3 with control bit FPOL = 0, internal feedback
with control bit FPOL = 1) is to set the reference black level
of the signal outputs to a value which corresponds to the
‘extended cut-off voltage’ of the CRT cathodes. With a lack
of output clamping pulses the integrated storage
capacitors will be discharged resulting in output signals
going to switch-off voltage. Feedback references are
driven by the I2C-bus.

2

C-BUS,6-BIT DAC)

, FB/R

1

2

1998 Dec 04 7

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

1. Control bit FPOL = 0
The cathode voltage (DC-coupled) is divided by a

voltage divider and fed back to the IC. During the
output clamping pulse it is compared with an
adjustable feedback reference voltage with a range of
approximately 5.77 to 4.05 V. Any difference will lead
to a reference black level correction (control bit
PEDST = 0) or pedestal black level correction (control
bit PEDST = 1) by charging or discharging the
integrated capacitor which stores the black level
information between the output clamping pulses.
The DC voltages of the output stages should be
designed in such a way that the reference black
level/pedestal black level is within the range of

0.5 to 2.5 V.
For correct operation it is necessary that there is

enough headroom for ultra black signals (negative
brightness setting, pedestal black level if control bit
PEDST = 1). Any clipping with the video supply
voltage at the cathode can disturb the signal rise/fall
times or the black level stabilization.

2. Control bit FPOL = 1
For applications with AC-coupled cathodes the signal

outputs are fed back internally. During the output
clamping pulse they are compared with a feedback
reference voltage of approximately 0.75, 1.0, 1.25 or

1.5 V (depending on the values of control bits BLH2
and BLH1). These values ensure a good adaptability
to discrete and integrated post amplifiers as well.

For black level restoration the DAC outputs (FB/R1,
FB/R2 and FB/R3) with a range of approximately

5.77 to 4.05 V can be used.
The use of pedestal blanking allows a very simple

black level restoration with a DC diode clamp instead
of a complicated pulse restoration circuit because the
pedestal black level is the most negative output signal.

7.6 Clamping and blanking pulses

The pin CLI of TDA4886A can be directly connected to
pin CLBL of e.g. TDA4855 sync processor for input
clamping pulses and vertical blanking pulses.
The threshold for the input clamping pulse (typical 3 V) is
higher than the threshold for the vertical blanking pulse
(typical 1.4 V) but there must be no blanking during input
clamping. Thus vertical blanking only is enabled if no input
clamping is detected. For this reason the input clamping
pulse must have rise/fall times faster than 75 ns/V during
the transition from 1.2 to 3.5 V and vice versa. The internal
vertical blanking pulse will be delayed by typical 270 ns.

TDA4886A

During the vertical blanking pulse at pin CLI signal
blanking, brightness blanking and with control bit
PEDST = 1 pedestal blanking will be activated. Input
clamping pulses during vertical blanking will not switch off
blanking.

For proper input clamping the input signals have to be at
black level during the input clamping pulse.

An input pulse at pin HFB (e.g. horizontal flyback pulse)
will be scanned with two thresholds. If the input pulse
exceeds the first one (typical 1.4 V) signal blanking,

brightness blanking and if control bit PEDST = 1
pedestal blanking will be activated. If the input pulse
exceeds the second one (typical 3 V) additionally output
clamping will be activated. The vertical blanking pulse can

also be mixed with the horizontal flyback pulse at pin HFB.

7.7 On Screen Display (OSD)

If the fast blanking input signal at pin FBL exceeds the
threshold (typical 1.4 V) the input signals are blanked
(signal blanking) and OSD signals are enabled. Then any
signal at pins OSD
threshold will create an insertion signal with an amplitude
of 120% of the nominal colour signal (approximately 74%
of the maximum colour signal). The amplitude can be
controlled by OSD contrast (driven by the I2C-bus) with a
range of 12 dB. The OSD signals are inserted at the same
point as the contrast controlled input signals and will be
treated with brightness and gain control like normal input
signals.

With control bit DISO = 1 the OSD signal insertion and fast
blanking (pin FBL) are disabled.

7.8 Subcontrast adjustment, contrast modulation and beam current limiting

The pin LIM is a linear contrast control pin which allows
subcontrast setting, contrast modulation and beam current
limiting. The maximum contrast is defined by the actual
I2C-bus setting. Input signals at pin LIM act on video and
OSD signals and do not affect the contrast bit resolution.

To achieve brightness uniformity over the screen, scan
dependent contrast modulation is possible.

, OSD2 or OSD3 exceeding the same

1

1998 Dec 04 8

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

7.9 I2C-bus control

The TDA4886A contains an I2C-bus receiver for several
control functions:

1. Contrast control with 6-bit DAC

2. Brightness control with 6-bit DAC

3. OSD contrast control with 4-bit DAC

4. Gain control for each channel with 6-bit DAC

5. Internal feedback reference and external reference
voltage control for each channel with 8-bit DAC

6. Control register with control bits BLH2, BLH1, FPOL,
DISV, DISO and PEDST.

After power-up and after internal power-on reset of the
I2C-bus the registers are set to the following values:

• Control bit FPOL to logic 1

• Control bits BLH2, BLH1, DISV, DISO and PEDST to

logic 0

• All other alignment registers to logic 0 (minimum value

for control registers).

TDA4886A

2. Direct mode
Adjustments via the I
a) Most significant bit (MSB) of subaddresses is set to

logic 0.

b) Number of I2C-bus transmissions in direct mode is

unlimited.

c) Adjustments take effect directly at the end of each

I2C-bus transmission.

d) Direct mode can be used for all adjustments but

large changes of control values may appear as

visual disturbances in the picture on the monitor.
e) Auto-increment is possible.
f) Vertical blanking pulse is not necessary.

2

C-bus take effect immediately.

2

7.10 I

1. Buffered mode

C-bus data buffer

Adjustments via the I2C-bus are synchronized with
vertical blanking pulse at CLI.

a) Most significant bit (MSB) of subaddresses is set to

logic 1.

b) Only one I2C-bus transmission in buffered mode is

accepted before the start of the vertical blanking
pulse. Following transmission trials will get no

acknowledge.
c) Received data is stored in one internal 8-bit buffer.
d) Adjustments will take effect with detection of the

first vertical blanking pulse after the end of

according I2C-bus transmission.
e) Waiting for vertical blanking pulse in buffered mode

can be interrupted by power-on reset.
f) Auto-increment is impossible.
g) Buffered mode should be used for user

adjustments such as contrast, OSD contrast and

brightness while picture on monitor is visible.

1998 Dec 04 9

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

P

V

P1, 2,3

supply voltage (pin 7) 0 8.8 V
supply voltage channels 1, 2 and 3 (pins 21,

0 8.8 V

18 and 15)

V

i

V

ext

input voltage (pins 6, 8 and 10) −0.1 V
external DC voltage applied to the following pins:

pins 1 to 4 −0.1 V
pins 5 and 11 −0.1 V
pins 12 and 13 −0.1 V
pins 23, 20 and 17 −0.1 V

P

P

+ 0.7 V

P
P

+ 0.7 V

P

pins 22, 19 and 16 note 1 note 1

I

o(av)

I

OM

P
T
T
T
V

tot
stg
amb
j
ESD

pin 24 −0.1 V
average output current (pins 22, 19 and 16) − 20 mA
peak output current (pins 22, 19 and 16) − 50 mA
total power dissipation − 1400 mW
storage temperature −25 +150 °C
operating ambient temperature −20 +70 °C
junction temperature −25 +150 °C
electrostatic handling for all pins

P

machine model note 2 −250 +250 V

human body model note 3 −2000 +2000 V

V

V

V

V

Notes

1. No external voltages.

2. Equivalent to discharging a 200 pF capacitor via a 0.75 µH inductance (

3. Equivalent to discharging a 100 pF capacitor via a 1500 Ω series resistor (

“UZW-B0/FQ-B302”

“UZW-B0/FQ-A302”

).

).

9 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 55 K/W

1998 Dec 04 10

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

10 CHARACTERISTICS

All voltages and currents are measured in a dedicated test circuit which is optimized for best high frequency
performance; all voltages are measured with respect to GND (pins 9 and 14); VP=V
18 and 15); T
outputs (pins 22, 19 and 16); reference black level (V

=25°C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; nominal colour signals at signal

amb

) approximately 0.77 V; nominal settings for brightness and

rbl

= 8 V (pins 7, 21,

P1, 2,3

contrast; maximum settings for OSD contrast and gain; no subcontrast, modulation of contrast or limiting (V24≥ 5 V);
no OSD fast blanking (pin 1 connected to ground); notes 1 to 3; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

P

I

P

V

P1,2,3

supply voltage (pin 7) 7.6 8.0 8.8 V
supply current (pin 7) note 4 − 21 25 mA
channel supply voltage

7.6 8.0 8.8 V

(pins 21, 18 and 15)

I

P1,2,3

V

PSO

Input clamping and vertical blanking input, validation of buffered I

V

5

channel supply current
(pins 21, 18 and 15)

supply voltage for signal switch
off (threshold at pin 7)

input clamping and vertical
blanking input signal

signal outputs (pins 22,
19 and 16) open-circuit;
V

≈ 0.77 V; notes 4 and 5

rbl

signal outputs switched to
switch-off voltage

2

C-bus data (pin 5)

notes 6 and 7

no vertical blanking,

− 21 25 mA

−−7.2 V

−0.1 − +1.2 V

no input clamping
vertical blanking,

1.6 − 2.6 V

no input clamping
input clamping,

3.5 − V

V

P

no vertical blanking

I

5

input current V5=1V −−0.2 −µA

pin 5 connected to ground;

−80 −60 −30 µA

note 8
V5= −0.1 V; note 8 −250 −200 −100 µA

t

r/f5

rise/fall time for input clamping

note 6; see Fig.7 −−75 ns/V
pulse, disable for vertical
blanking

t

W5

t

W5I2C

width of input clamping pulse 0.6 −−µs
width of vertical blanking pulse

for validation of buffered

leading and trailing edge

threshold V5= 1.4 V; note 7

10 −−µs

I2C-bus data

t

I2Cvalid

t

I2Cdead

delay between leading edge of
vertical blanking pulse and
validation of buffered I2C-bus
data

dead time of I2C-bus receiver
after synchronizing vertical

I2C-bus transmission in

buffered mode completed;

leading edge threshold

V5= 1.4 V; note 7

leading edge threshold

V5= 1.4 V; note 7

−−2µs

15 −−µs

blanking pulse in case of a
completed I2C-bus transmission
in buffered mode

1998 Dec 04 11

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

dl5

delay between leading edges of
vertical blanking input pulse and
signal blanking at signal outputs

V11< 0.8 V; input pulse with

50 ns/V; threshold for rising

input pulse V5= 1.4 V;

− 270 − ns

threshold after input clamping

pulse V5=3V; V

I(b-w)

= 0.7 V;

see Fig.7

t

dt5

delay between trailing edges of
vertical blanking input pulse and
internal blanking pulse

V11< 0.8 V; input pulse with

50 ns/V; threshold V5= 1.4 V;

see Fig.7

− 115 − ns

Output clamping and blanking input (pin 11)

V

11

output clamping and blanking
input signal

note 9

no blanking,

−0.1 − +0.8 V

no output clamping
blanking, no output clamping 2.0 − 2.6 V
blanking, output clamping 3.5 − V

I

11

input current V11= 0.8 V −−0.4 −µA

pin 11 connected to ground;

−80 −60 −30 µA

P

note 8

V

= −0.1 V; note 8 −250 −200 −100 µA

11

t

W11

width of output clamping pulse threshold V11=3V 1 −−µs

Video signal inputs (channel 1: pin 6; channel 2: pin 8; channel 3: pin 10)

V

i(b-w)6,8,10

positive input signal referred to

− 0.7 1.0 V

black

I

I6,8,10

DC input current no input clamping;

V

I6,8,10=VI(clamp)6, 8,10

T

= −20 to +70 °C

amb

during input clamping;

V

I6,8,10=VI(clamp)6,8,10

0.02 0.20 0.35 µA

;

±100 ±135 ±170 µA

±0.7 V

Signal blanking

α

ct(blank)

crosstalk suppression from
input to output during blanking

control bit DISV = 1; f = 80 MHz 20 −−dB

control bit DISV = 1;

10 −−dB

f = 120 MHz

V

Clipping of negative input signals (measured at signal outputs)

∆V

clipp

offset during sync clipping
related to nominal colour signal

V

I6,8,10=VI(clamp)6,8,10

see Fig.3

Contrast control; see Fig.8 and note 11
d

C

colour signal related to nominal
colour signal

3FH (maximum) − 4.2 − dB

26H (nominal) − 0 − dB

00H (minimum) −−28 − dB

∆G

track

tracking of output colour signals

3FH to 00H; note 12 − 0.0 0.5 dB
of channels 1, 2 and 3

1998 Dec 04 12

; note 10;

−−2%

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Fast blanking (pin 1) and OSD signal insertion (channel 1: pin 2; channel 2: pin 3; channel 3: pin 4); note 13

V

1

fast blanking input signal no video signal blanking,

0 − 1.1 V

OSD signal insertion disabled

video signal blanking,

1.7 − V

V

P

OSD signal insertion enabled

V

2,3,4

OSD input signal V1> 1.7 V

no internal OSD signal

0 − 1.1 V

insertion

t

r(OSD)

t

f(OSD)

t

g(CO)

t

g(OC)

dV

OSD

rise time of OSD colour signals
(pins 22, 19 and 16)

fall time of OSD colour signals
(pins 22, 19 and 16)

width of (negative going) OSD
signal insertion glitch, leading
edge (pins 22, 19 and 16)

width of (negative going) OSD
signal insertion glitch, trailing
edge (pins 22, 19 and 16)

overshoot/undershoot of OSD
colour signal related to actual

internal OSD signal insertion 1.7 − V

10 to 90% amplitude;

−−4ns

input pulse with 1.2 ns/V

90 to 10% amplitude;

−−7ns

input pulse with 1.2 ns/V

identical pulses at fast blanking

0 − 6ns
input (pin 1) and OSD signal
inputs (pins 2, 3 and 4)

identical pulses at fast blanking

0 − 6ns
input (pin 1) and OSD signal
inputs (pins 2, 3 and 4)

pulse with 1.2 ns/V at OSD

−−30 %

signal inputs (pins 2, 3 and 4)

V

P

OSD output pulse amplitude
(pins 22, 19 and 16)

V

OSD(max)

maximum OSD colour signal
related to nominal colour signal

maximum OSD contrast;
maximum gain

100 120 140 %

(pins 22, 19 and 16)
OSD contrast control; see Fig.9 and note 14
d

OC

OSD colour signal related to

maximum OSD colour signal

0FH (maximum) − 0 − dB

00H (minimum) −14 −12 −10 dB
Subcontrast adjustment, contrast modulation and beam current limiting (pin 24); see Fig.8 and note 15
V

24(nom)

V

24(start)

nominal input voltage pin 24 open-circuit 4.7 5.0 5.3 V
starting voltage for contrast

4.2 4.5 4.8 V

and OSD contrast reduction

V

24(stop)

B

24

stop voltage for contrast and
OSD contrast reduction

bandwidth of contrast

−32 dB below maximum colour

1.5 2.0 2.5 V

signal (contrast setting 3FH)

−3dB 4 −−MHz

modulation

I

24(max)

maximum input current V24=0V −1.0 −−µA
Brightness control; see Fig.10 and notes 16 and 17
∆V

bl

difference between black level

and reference black level at

signal outputs related to

nominal colour signal

3FH (maximum) 25 30 35 %
10H (nominal) − 0 − %
00H (minimum) −12 −10 −8%

1998 Dec 04 13

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Gain control; see Fig.11 and note 18

d

G

video signal related to video

signal at maximum gain

3FH (maximum) − 0 − dB
00H (minimum) −8.3 −7.3 −6.3 dB

Pedestal blanking

∆V

22,19,16(PED)

difference from pedestal black

note 19; see Fig.5 −18 −16 −14 %
level to video black level at
nominal brightness, measured
at signal output pins related to
nominal colour signal

Signal outputs (channel 1: pin 22; channel 2: pin 19; channel 3: pin 16)

V

22,19,16(nom)

nominal colour signal nominal contrast; maximum

gain; V

= 0.7 V; without

i(b-w)

2.5 2.8 3.1 V

load

V

22,19,16(max)

maximum colour signal maximum contrast; maximum

gain; V

= 0.7 V; without

i(b-w)

4.1 4.54 5 V

load

V

22,19,16(min)

switch-off voltage

− 0.05 0.1 V

(minimum output voltage level)

V

22,19,16(top)

maximum output voltage level at arbitrary input signals,

VP− 2 − VP− 1V
contrast, brightness and gain
adjustments; without load

R

(o)22,19,16

I

22,19,16(source)

I

22,19,16(M)(source)

output resistance − 75 −Ω
maximum source current −15 −−mA
peak source current during fast positive signal

−40 −−mA

transients

I

22,19,16(sink)

maximum sink current
(built-in current source)

output voltage
V

22,19,16

≈ 0.77 V; note 20

output voltage V

22,19,16

=6V;

3.2 4 − mA

1.6 2 − mA

note 20

I

22,19,16(M)(sink)

peak sink current during fast negative signal

−−20 mA

transients

S/N signal-to-noise ratio note 21 44 −−dB
D

22,19,16(th)

output thermal distortion note 22 −−0.6 %

1998 Dec 04 14

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Frequency response at signal outputs (channel 1: pin 22; channel 2: pin 19; channel 3: pin 16)

∆G

22,19,16(f)

t

r(22,19,16)

amplification decrease by
frequency response

rise time of fast transients input rise time=1ns;

f = 165 MHz;
V

≤ 0.2 V (small signal)

i(b-w)

− 1.2 3.0 dB

− 2.8 3.1 ns

10 to 90% amplitude;
nominal colour signal; note 23

t

f(22,19,16)

fall time of fast transients input fall time = 1 ns;

− 3.8 4.1 ns
90 to 10% amplitude;
nominal colour signal; note 23

dV

22,19,16

overshoot of output signal pulse
related to actual output pulse

input rise time=1ns;
nominal colour signal

8 1730%

amplitude
undershoot of output signal

pulse related to actual output

input fall time = 1 ns;
nominal colour signal

3 1325%

pulse amplitude

Crosstalk at signal outputs (channel 1: pin 22; channel 2: pin 19; channel 3: pin 16)

α

ct(tr)

transient crosstalk suppression input rise/fall time=1ns;

10 −−dB

note 24

α

ct(f)

crosstalk suppression by
frequency

f = 50 MHz 25 −−dB
f = 100 MHz 10 −−dB

Internal feedback reference voltage; see Fig.12 and note 25
V

V

ref(n)

ref(p)

internal reference voltage for
negative feedback polarity

internal reference voltage for
positive feedback polarity

FFH (minimum); FPOL = 0 3.85 4.05 4.2 V
00H (maximum); FPOL = 0 5.6 5.77 5.9 V
FPOL = 1

BLH2 = 0; BLH1 = 0 0.71 0.77 0.83 V
BLH2 = 0; BLH1 = 1 0.95 1.01 1.07 V
BLH2 = 1; BLH1 = 0 1.19 1.25 1.31 V
BLH2 = 1; BLH1 = 1 1.43 1.49 1.55 V

Output clamping, feedback inputs for DC coupling (channel 1: pin 23; channel 2: pin 20; channel 3: pin 17)

I

23,20,17(max)

maximum input current during output clamping;

V11> 3.5 V; V

23,20,17

= 0.5 V;

−500 −200 −60 nA

FPOL = 0

V

22,19,16(rbl)(min)

minimum reference black level PEDST = 0; V11> 3.5 V;

0.01 0.1 0.5 V
FPOL = 0

minimum pedestal black level PEDST = 1; V

> 3.5 V;

11

0.01 0.1 0.5 V
FPOL = 0

V

22,19,16(rbl)(max)

maximum reference black level PEDST = 0; V11> 3.5 V;

2.4 2.8 − V
FPOL = 0

maximum pedestal black level PEDST = 1; V

> 3.5 V;

11

2.4 2.8 − V
FPOL = 0

∆V

bl(CRT)

black level variation at CRT FPOL = 0; note 26 −−200 mV

1998 Dec 04 15

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆V

22,19,16(bl)(lf)

black level variation between
clamping pulses related to
nominal colour signal

FPOL = 0;
line frequency = 60 kHz;
10% duty cycle

− 0.25 0.5 %

Output clamping for AC coupling (internal feedback of signal outputs)

V

22,19,16(rbl)

reference black level V11> 3.5 V; FPOL = 1;

PEDST = 0

BLH2 = 0; BLH1 = 0 0.71 0.77 0.83 V
BLH2 = 0; BLH1 = 1 0.95 1.01 1.07 V
BLH2 = 1; BLH1 = 0 1.19 1.25 1.31 V
BLH2 = 1; BLH1 = 1 1.43 1.49 1.55 V

pedestal black level V

> 3.5 V; FPOL = 1;

11

PEDST = 1

BLH2 = 0; BLH1 = 0 0.71 0.77 0.83 V
BLH2 = 0; BLH1 = 1 0.95 1.01 1.07 V
BLH2 = 1; BLH1 = 0 1.19 1.25 1.31 V
BLH2 = 1; BLH1 = 1 1.43 1.49 1.55 V

∆V

22,19,16(bl)(lf)

black level variation between
clamping pulses related to
nominal colour signal

FPOL = 1;
line frequency = 60 kHz;
10% duty cycle

− 0.25 0.5 %

External reference voltages for AC coupling (FB/R

note 27
V

23,20,17

external reference voltage FFH (minimum); FPOL = 1 3.85 4.05 4.2 V

00H (maximum); FPOL = 1 5.6 5.77 5.9 V

R

23,20,17

I

23,20,17(sink)

I

23,20,17(source)

2

C-bus inputs (SDA: pin 12; SCL: pin 13); note 28

I

f

SCL

V

IL

V

IH

I

IL

I

IH

V

OL

I

12(ack)

output resistance FPOL = 1 − 100 −Ω
maximum sink current FPOL = 1 −−400 µA
maximum source current FPOL = 1 −−330 −280 µA

SCL clock frequency −−100 kHz
LOW-level input voltage 0.0 − 1.5 V
HIGH-level input voltage 3.0 − 5.0 V
LOW-level input current VIL=0V −10 −−µA
HIGH-level input current VIH=5V −10 −−µA
LOW-level output voltage during acknowledge 0.0 − 0.4 V
output current at pin 12 during

VOL= 0.4 V 3.0 − 5.0 mA

acknowledge

V

th(POR)(r)

threshold for power-on reset on rising supply voltage − 1.5 2.0 V

falling supply voltage − 3.5 − V

V

th(POR)(f)

threshold for power-on reset off rising supply voltage −−7.0 V

falling supply voltage − 1.5 − V

: pin 23; FB/R2: pin 20; FB/R3: pin 17); see Fig.13 and

1

1998 Dec 04 16

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

Notes to the characteristics

1. Definition of levels (see Figs 3 to 5)
Reference black level:this is the level to which the input level is clamped during the input clamping pulse

(V5> 3.5 V). It is used internally as a reference for the gain settings. It can be observed on the outputs:
a) When the input is at black and the brightness setting is nominal (subaddress 01H = 10H)
b) During output blanking/clamping (V11> 3.5 V) if control bit PEDST = 0.

Video black level:this is the black level of the actual video. On the input it is still equal to the reference black level.

On the output it may deviate from it according to the brightness setting. Contrast setting leaves the video black level
unaltered. Gain setting biases the video black level due to its influence on brightness. This is important for correct

grey scale tracking.
Pedestal black level: this is anultra black level which deviates from reference black level by a fixed amount. It can

be observed on the output during output blanking/clamping (V11> 3.5 V) if control bit PEDST = 1.

Switch-off voltage: this is the lowest signal voltage at outputs. The signals will be switched off by discharging the
internal black level storage capacitors if the supply voltage is less than V

PSO

.

Blanking level: this level equals reference black (control bit PEDST = 0) or pedestal black (control bit PEDST = 1).

2. Explanation to black level adjustment:

The three reference black levels are aligned correctly when they are made equal to the ‘extended cut-off levels’ of
the three cathodes. Full raster and spot cut-off can only be achieved by enabling the pedestal blanking or by applying
a negative pulse to the control grid G1.

Negative feedback for DC-coupled cathodes (control bit FPOL = 0): the actual blanking level on the outputs
depends on the external feedback application for output clamping. The loop will function correctly only if it is within
the control range of V

22,19,16(rbl)(min)

to V

22,19,16(rbl)(max)

. It should be noted that changing control bit PEDST in a given
application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three black
levels).

Positive feedback for AC-coupled cathodes (control bit FPOL = 1): the feedback loop for output clamping is
closed internally. The actual blanking level at the outputs depends on control bits BLH2 and BLH1 only. Four discrete
blanking levels between approximately 0.75 and 1.5 V can be chosen. It should be noted that changing control bit
PEDST will not affect the blanking level selected by control bits BLH2 and BLH1, but instead shifts the video (and
needs re-alignment of the three black levels).

3. Definition of output signals (see Fig.6):

Colour signal: all positive voltages referred to black level at signal outputs.
Nominal colour signal: colour signal with nominal input signal (0.7 V

), nominal contrast setting and maximum

b-w

gain setting.

Video signal: all positive voltages referred to reference black level at signal outputs. The video signal is the
superimposing of the brightness information (∆Vbl) and the colour signal.

4. The total supply current IP=I7+I21+I18+I15 depends on the supply voltage with a factor of approximately 4.4 mA/V
and varies in the temperature range from −20 to +70 °C by approximately ±5% (V

22,19,16

= 0.77 V).

5. The channel supply current depends on the signal output current, the channel supply voltage and the signal output
voltage. With I

I

21,18,15IpxI22,19,16

px=I21,18,15

at V

4.4

mA

-------- ­V

P1,2,3

= 8 V and V

V

P1,2,3

8V–()× 1

22,19,16

= 0.77 V:

mA

-------- ­V

V

22 19 16,,

0.77 V–()×–++≈

1998 Dec 04 17

Philips Semiconductors Product specification









140 MHz video controller with I2C-bus

TDA4886A

6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and
if control bit PEDST = 1 pedestal blanking). With a fast clamping pulse (transition between V5= 1.2 to 3.5 V and vice
versa in less than 75 ns/V) no blanking will occur during input clamping.

For 75 ns/V < t

≤ 280 ns/V the generation of the internal vertical blanking pulse is uncertain. For t

r/f5

> 280 ns/V

r/f5

the internal blanking pulse will be generated.
Pin 5 open-circuited will activate permanent input clamping and undefined blanking.

7. Pin 5 can be used to synchronize all adjustments via the I2C-bus (one by one). In case of a completed I2C-bus
transmission in buffered mode only the leading edge of a vertical blanking pulse activates an adjustment. See also
Section 7.10.

After the adjustment has been activated (validation of buffered I2C-bus data) the I2C-bus will be reset and further
transmissions in direct or buffered mode are enabled.

I2C-bus transmissions in direct mode need no synchronization pulses.

8. Input voltages less than −0.1 V can produce internal substrate currents which disturb the leakage currents at the
signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or less. Feeding
clamping/blanking pulses via a resistor of some kΩ protects the pin from negative voltages.

9. Pin 11 should be used for output clamping and/or blanking. Pin 11 open-circuited will activate permanent blanking
and output clamping.

10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below
input reference black level (see Fig.3).

2

11. Contrast control acts on internal colour signals under I

C-bus control; subaddress 02H (bit resolution 1.6% of

contrast range).

A

A

1



12.

∆G

track

A

: colour signal output amplitude in channel n = 1, 2 or 3 at any contrast setting.

n

A

: colour signal output amplitude in channel n = 1, 2 or 3 at nominal contrast setting and same gain setting.

n0

20 maximum of

× dB=



log

-------- ­A





13. When OSD fast blanking is active and V

20

×

-------- ­A

10

2

are HIGH (V1> 1.7 V, V

2,3,4



log



A

-------- ­A

A

1

30

×

-------- ­A

10

3



log;;



2,3,4

A

A

2

30

×

-------- -

-------- -

A

A

20

3

> 1.7 V) the OSD colour signals will be
inserted in front of the gain potentiometers. This assures a correct grey scale of all video signals. The amplitudes of
the inserted OSD signals can be controlled simultaneously by OSD contrast via the I2C-bus.

14. OSD contrast control acts on inserted OSD colour signals under I2C-bus control; subaddress 03H (bit resolution

6.7% of OSD contrast range).

15. This pin can be used for subcontrast setting, beam current limiting and contrast modulation. Both the video and OSD
contrast are reduced simultaneously (see Figs 8 and 9). Because of the high-ohmic input impedance the pin should
be tied to a voltage of more than 5 V or applied with a capacitor of some nF if not used.

16. Brightness control adds an I2C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution

1.6% of brightness range).

17. The voltage difference between video black level and reference black level is related to the colour signal (see note 3)
with nominal 0.7 V (p-p) input signal, at nominal contrast (subaddress 02H = 26H) and for any gain setting.
The voltage difference (in Volts) is proportional to the gain setting (grey scale tracking). Therefore ∆Vbl (in percent)
is constant for any gain setting. The given values of ∆Vbl are valid only for video black levels higher than the signal
output switch-off voltage V

22,19,16(min)

.

18. Gain control acts on video signals and inserted OSD video signals under I2C-bus control; subaddress 04H
(channel 1), 05H (channel 2) and 06H (channel 3; bit resolution 1.6% of gain range respectively).

1998 Dec 04 18

Philips Semiconductors Product specification



140 MHz video controller with I2C-bus

TDA4886A

19. Pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative
signal at the signal output pins. The reference black level which should correspond to the ‘extended cut-off voltage’
at the cathodes is approximately ∆V

22,19,16(PED)

higher (see Fig.5). The use of pedestal blanking with AC-coupled
cathodes (control bit FPOL = 1) allows a very simple black level restoration with a DC diode clamp instead of a
complicated pulse restoration circuit.

20. DC load currents of signal outputs must not exceed maximum sink currents, otherwise signal distortions may occur.

21. The signal-to-noise ratio is calculated by the formula (range 1 to 120 MHz):
S

20

--- ­N

22. Large output currents e.g. I

peak-to-peak value of the nominal signal output voltage

--------------------------------------------------------------------------------------------------------------------------------------------------­RMS value of the noise output voltage

22,19,16(M)(source)

lead to signal depending power dissipation in output transistors. Thermal

dBlog×=

VBE variation is compensated.

23. Following formula can be used to approximately determine the output rise/fall time for any other input rise/fall time:

2

t

r/f, measured

2

t

r/f (22,19,16)

2

t

+=



r/f, input

–

2

1ns()

24. Transient crosstalk between any two output pins:
a) Input conditions: any channel (channel A) with nominal input signal and 1 ns rise time. The inputs of the other

two channels are capacitively coupled to ground (channel B). Gain setting to maximum (3FH). Contrast setting to
nominal (26H). No limiting/modulation of contrast (V

24

≥ 5V)

b) Output conditions: black level set to approximately 0.77 V for each channel at signal outputs. Output signals

are VA and VB respectively

V

c) Transient crosstalk suppression:

α

ct(tr)

20

------ ­V

A

dBlog×=

B

25. The internal feedback reference voltages are not influenced by the value of control bit PEDST but depend on the
individual adjustments via the I2C-bus, the selected feedback polarity (control bit FPOL = 0 or 1) and the selected
black level for positive feedback polarity (control bit FPOL = 1 and control bits BLH2=0or1 and BLH1 = 0 or 1):

Control bit FPOL = 0: the internal feedback reference voltage acts under I2C-bus control; subaddress 07H
(channel 1), 08H (channel 2) and 09H (channel 3; bit resolution 0.4% of voltage range). Rising values of the data
bytes, e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs
(pins 22, 19 and 16). The internal feedback reference voltages can be measured at feedback inputs
(pins 23, 20 and 17) during output clamping (V11> 3.5 V) in closed feedback loop. The feedback loop remains
operative at reference black levels between the specified values of V

22,19,16(rbl)(min)

and V

22,19,16(rbl)(max)

.

Control bit FPOL = 1: the internal feedback reference voltage can be measured at signal outputs
(pins 22, 19 and 16) during output clamping (V11> 3.5 V). By means of control bits BLH2 and BLH1 it is possible to
choose one of the four specified values between approximately 0.75 and 1.5 V. This facilitates the adaption to
different kinds of post amplifiers.

26. Slow variations of video supply voltage V
A change of V

with 5 V leads to a specified change of the cathode voltage.

CRT

will be suppressed at the CRT cathode by the clamping feedback loop.

CRT

27. The external reference voltages act under I2C-bus control for control bit FPOL = 1; subaddress 07H (FB/R1), 08H
(FB/R2) and 09H (FB/R3; bit resolution 0.4% of voltage range).

28. All adjustments via the I2C-bus can be synchronized with vertical blanking pulse at pin CLI. This is called I2C-bus
transmission in buffered mode. The adjustments via the I2C-bus will take effect immediately in the so called direct
mode.

The timing of I2C-bus transmissions in buffered mode is related to the vertical blanking. See specification of pin 5
(vertical blanking input) and note 7.

1998 Dec 04 19

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

input signals

input video signal

with syncs

at pins 6, 8 and 10

input clamping pulses

at pin 5

blanking/output

clamping pulses

at pin 11

TDA4886A

input reference
black level

the syncs will be clipped
to reference black level
internally

MHA344

The input video signals have to be on black level during input clamping.

Fig.3 Input signals.

1998 Dec 04 20

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

blanking pulse,
output clamping pulse
at pin 11

blanking signal
output signals

pins 22, 19 and 16

maximum gain setting,
nominal contrast setting,
maximum/nominal/minimum
brightness setting

switch-off voltage

ground

(1)

(2)

(3)

TDA4886A

video black levels at
maximum brightness
nominal brightness
minimum brightness

reference black level

maximum gain setting,
maximum brightness setting,
maximum/nominal/minimum
contrast setting

switch-off voltage

maximum brightness setting,
nominal contrast setting,
maximum/minimum
gain setting

switch-off voltage

(1) Maximum.
(2) Nominal.
(3) Minimum.

ground

ground

(1)

(2)

(3)

(1)

(3)

video black level
(maximum brightness)

reference black level

video black level
(maximum brightness)

reference black level

MHB187

Fig.4 Definition of levels, function of brightness setting, contrast setting, gain setting, no pedestal blanking

(PEDST = 0).

1998 Dec 04 21

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

blanking pulse,
output clamping pulse
at pin 11

blanking signal
output signals

pins 22, 19 and 16

PEDST = 0
no pedestal blanking

maximum gain setting,
nominal contrast setting,
maximum/minimum
brightness setting

switch-off voltage

ground

(1)

(2)

TDA4886A

video black levels at
maximum brightness
minimum brightness

reference black level

PEDST = 1
pedestal blanking

maximum gain setting,
nominal contrast setting,
maximum/minimum
brightness setting

(1) Maximum.
(2) Minimum.

(1)

video black levels at

(2)

switch-off voltage

ground

maximum brightness
minimum brightness

reference black level
pedestal black level

Fig.5 Output signals without (PEDST = 0) and with pedestal blanking (PEDST = 1).

MHB188

1998 Dec 04 22

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

output signals
pins 22, 19 and 16

PEDST = 0
no pedestal blanking

maximum gain setting,
nominal contrast setting,
maximum/minimum
brightness setting

video black levels at
maximum brightness
minimum brightness

colour signals video signals

TDA4886A

reference black level

MHB189

handbook, full pagewidth

input pulses at pin 5

internal pulse for
input clamping

internal pulse for
vertical blanking

Fig.6 Definition of output signals.

t

dl5

t

dt5

3 V

t

≤ 75 ns/V

rf5

1.4 V

t

dl5

MHB190

Fig.7 Timing of pulses at pin 5 and derived internal pulses.

1998 Dec 04 23

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

colour signal

amplitude
related to

nominal colour

signal amplitude

(dB)

(1) No contrast reduction by subcontrast.
(2) Partial contrast reduction by subcontrast.
(3) Full contrast reduction by subcontrast.

4.2

−28

0

00H

10H

20H 30H

26H

TDA4886A

MHB191

(1)

(2)

(3)

3FH

contrast control data byte

Fig.8 Contrast control characteristic with subcontrast (equal to contrast modulation and limiting).

handbook, full pagewidth

OSD signal

amplitude

related to

nominal colour

signal amplitude

(%)

(1) No OSD contrast reduction by subcontrast.
(2) Partial OSD contrast reduction by subcontrast.
(3) Full OSD contrast reduction by subcontrast.

maximum colour signal amplitude

160

maximum OSD signal amplitude

125

nominal colour signal amplitude

100

(1)

(2)

30

00H 0FH

(3)

OSD contrast control data byte

MHA351

Fig.9 OSD contrast control characteristic with subcontrast (equal to contrast modulation and limiting).

1998 Dec 04 24

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

difference of

video black level

and reference

black level

related to

nominal colour

signal amplitude

(%)

(1) Nominal adjustment.
(2) Nominal brightness reference black level.

−10

30

0

00H

(1)

(2)

10H

20H 30H

brightness control data byte

TDA4886A

MHA352

3FH

handbook, full pagewidth

video signal gain

related to

maximum video

signal gain

(%)

100

45

0

00H

Fig.10 Brightness control characteristic.

10H

20H 30H

MHA353

3FH

gain control data byte

Fig.11 Gain control characteristic.

1998 Dec 04 25

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

internal feedback
reference voltage

(V)

5.77

4.05

1.49

1.25

1.01

0.77

0
00H 20H 40H 60H 80H A0H C0H E0H FFH

(1)

(2)

TDA4886A

MHB192

(3)

(4)

(5)

feedback reference data byte

(1) Control bit FPOL = 0.
(2) Control bits FPOL = 1, BLH2 = 1, BLH1 = 1.
(3) Control bits FPOL = 1, BLH2 = 1, BLH1 = 0.
(4) Control bits FPOL = 1, BLH2 = 0, BLH1 = 1.
(5) Control bits FPOL = 1, BLH2 = 0, BLH1 = 0.

handbook, full pagewidth

external

reference voltage

(V)

5.77

4.05

0
00H 20H 40H 60H 80H A0H C0H E0H FFH

Fig.12 Internal feedback reference voltages.

MHB193

(1)

feedback reference data byte

(1) Control bit FPOL = 1.

Fig.13 External feedback reference voltages.

1998 Dec 04 26

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

11 I2C-BUS PROTOCOL Table 1 Slave address

A6

(1)

A5

(1)

A4

(1)

A3

(1)

A2

(1)

A1

(1)

A0

(1)

W

(2)

10001000

Notes

1. Address bit.

2. Write bit.

Table 2 Slave receiver format

(1)

S

SLAVE ADDRESS A

(2)

SUBADDRESS A

(3)

DATA BYTE A

(4)

(5)

P

Notes

1. START condition.

2. A = acknowledge.

3. All subaddresses within the range 00H to 09H are automatically incremented. The subaddress counter wraps around
from 09H to 00H. For subaddresses within the range 80H to 8FH no auto-increment takes place. Subaddresses
outside the ranges 00H to 0FH and 80H to 8FH are acknowledged by the device but neither auto-increment nor any
other internal operation takes place.

4. Single data byte in case of no auto-increment of subaddresses. More than one data byte with auto-increment of
subaddresses.

5. STOP condition.

1998 Dec 04 27

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

TDA4886A

Table 3 Subaddress byte format

(1)

BUFFERED

MODE

S7

FUNCTION

SUBADDRESS

DIRECT

MODE

Control register 00H 80H B
Brightness control 01H 81H B
Contrast control 02H 82H B
OSD contrast control 03H 83H B
Gain control channel 1 04H 84H B
Gain control channel 2 05H 85H B
Gain control channel 3 06H 86H B
Black level reference channel 1 07H 87H B
Black level reference channel 2 08H 88H B
Black level reference channel 3 09H 89H B

(2)S6(2)S5(2)

(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)

SUBADDRESS BYTE

(2)S3(2)S2(2)S1(2)S0(2)

S4

0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001

0AH to 0FH 8AH to 8FH not used

Notes

1. The most significant bit (MSB) of the subaddress enables an I

2

C-bus transmission in direct or in buffered mode

(see note 3). Subaddresses outside the ranges 00H to 0FH and 80H to 8FH are not used.

2. Subaddress bit.

3. Most significant bit of subaddress byte. I2C-bus transmission in direct mode: B = 0. I2C-bus transmission in
buffered mode: B = 1.

1998 Dec 04 28

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

Table 4 Subaddress and data byte format

MODE

(1)

(4)D6(4)

D7

(5)X(5)
(5)X(5)
(5)X(5)
(5)X(5)

(5)X(5)

(5)X(5)

(5)X(5)

SUBADDRESS

FUNCTION

BUFFERED

MODE

Control register 00H 80H X
Brightness control 01H 81H X
Contrast control 02H 82H X
OSD contrast

03H 83H X

control
Gain control

04H 84H X

channel 1
Gain control

05H 85H X

channel 2
Gain control

06H 86H X

channel 3
Black level

07H 87H A77 A76 A75 A74 A73 A72 A71 A70 −

reference channel 1
Black level

08H 88H A87 A86 A85 A84 A83 A82 A81 A80 −

reference channel 2
Black level

09H 89H A97 A96 A95 A94 A93 A92 A91 A90 −

reference channel 3

TDA4886A

DATA BYTE

D5

(4)

D4

(4)

BLH2 BLH1 FPOL DISV DISO PEDST 08H

A15 A14 A13 A12 A11 A10 10H
A25 A24 A23 A22 A21 A20 26H

(5)

X

(5)

X

A45 A44 A43 A42 A41 A40 3FH

A55 A54 A53 A52 A51 A50 3FH

A65 A64 A63 A62 A61 A60 3FH

(2)

NOMINAL

D3

(4)

D2

(4)

D1

(4)

D0

(4)

VALUE

A33 A32 A31 A30 0FH

(3)DIRECT

Notes

1. See Table 3 (Subaddress byte format).

2. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0).

3. Under certain conditions the nominal values lead to nominal colour signals etc. (see note 3 of Chapter
“Characteristics”).

2

After power-up and after internal power-on reset of the I

C-bus the registers are set to the following values:
a) Control bit FPOL to logic 1.
b) Control bits BLH2, BLH1, DISV, DISO and PEDST to logic 0.
c) All other alignment registers to logic 0 (minimum value for control registers).

4. Data bit.

5. X means don’t care but for software compatibility with other video ICs with the same slave address, they are
preferably set to logic 0.

1998 Dec 04 29

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

Table 5 Control register

BIT FUNCTION

PEDST = 0 no pedestal blanking
PEDST = 1 pedestal blanking enabled
DISO = 0 OSD signals enabled
DISO = 1 OSD signals disabled
DISV = 0 video signals enabled
DISV = 1 video signals disabled
FPOL = 0 negative feedback polarity; pins 23, 20 and 17 as external feedback inputs; no external

feedback reference voltages

FPOL = 1 positive feedback polarity; pins 23, 20 and 17 as external reference voltage outputs;

internal feedback of signal outputs

BLH2 = 0 BLH1 = 0 for positive feedback polarity only: internal feedback reference voltage switched to

approximately 0.75 V

BLH2 = 0 BLH1 = 1 for positive feedback polarity only: internal feedback reference voltage switched to

approximately 1.0 V

BLH2 = 1 BLH1 = 0 for positive feedback polarity only: internal feedback reference voltage switched to

approximately 1.25 V

BLH2 = 1 BLH1 = 1 for positive feedback polarity only: internal feedback reference voltage switched to

approximately 1.5 V

TDA4886A

1998 Dec 04 30

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

LOAD PRESET CONTROL BITS

LOAD FACTORY SETTINGS

(CHANNEL 1, 2, 3)

FEEDBACK REFERENCES

(CHANNEL 1, 2, 3)

LOAD USER PRESET VALUES

CONTRAST

BRIGHTNESS

OSD CONTRAST

START

FPOL

PEDST

DISV = 1

DISO = 1

BLH2
BLH1

GAIN

load from program
ROM code or EEPROM

load from EEPROM

load from EEPROM

TDA4886A

(1) Only synchronized video should

be displayed. Each new mode
can be displayed by OSD.

(2) Data transmission should be

synchronized with vertical
blanking of the monitor.

DEFLECTION

CONTROL

IC LOCKED

yes

DISV = 0
DISO = 0

DISPLAY NEW MODE

DISO = 1

USER INPUT

yes

RESPONSE TO USER INPUTS

(CONTRAST, BRIGHTNESS, OSD CONTRAST)

DISO = 0

DISO = 1

DEFLECTION

CONTROL

IC LOCKED

yes

no

(1)

no

(2)

no

DISV = 1

MHB194

Fig.14 I2C-bus control flow.

1998 Dec 04 31

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

12 TEST AND APPLICATION INFORMATION

handbook, full pagewidth

fast blanking

24

232

223

214

205

19

187

OSD

inputs

1

6

TDA4886A

contrast modulation input

subcontrast setting

90 V

70 V

TDA4886A

limiting input

Application with integated
post amplifier, DC-coupled cathode
and negative feedback.

to cathode

BLACK LEVEL

RESTORATION

to cathode
Application with integated
post amplifier, AC-coupled cathode
and black level restoration cicuit.

178

8 V

16

1510

14

13

output clamping

input clamping

vertical blanking

90 V

Application with discrete
post amplifier, DC-coupled
cathode and negative
feedback.

to cathode

5 V

blanking

9

11

12

resistors

I2C-BUS

pull-up

Fig.15 Basic applications for different kinds of post amplifiers with DC or AC coupling.

MHB266

12.1 Test boards

For high frequency measurements a special test
application and printed-circuit board with only a few
external components is built. It utilizes the internal positive
feedback of the output signals during output clamping with
control bit FPOL = 1. Figure 16 shows the test application

1998 Dec 04 32

circuit and Figs 17 and 18 show the layout and mounting
of the double-sided printed-circuit board. Most
components are of SMD type. Short HF loops and
minimum crosstalk between the channels and between
signal inputs and outputs are achieved by properly shaped
ground areas.

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

5.6 Ω

100

1 kΩ

FBL

1

OSD

1

2

OSD

2

3

OSD

3

4

CLI

5

V

I1

6

V

P

7

100

pF

nF

V

GND

V

HFB

SDA

I2

8

9

I3

10

11

12

handbook, full pagewidth

FBL

OSD

1

OSD

2

OSD

3

CLI

V

I1

V

I2

V

I3

HFB

50

50

50

50

Ω

Ω

Ω

Ω

10 nF

150 pF

10 nF

150 pF

10 nF

150 pF

50 Ω

50 Ω

50 Ω

50 Ω

50 Ω

5 kΩ

J1

5 kΩ

J2

5 kΩ

J3

150pF10

0.47 µF
(63 V)

nF

TDA4886A

TDA4886A

LIM

24

10

kΩ

10

kΩ

10
kΩ

FB/R

1

solder pin

FB/R

2

solder pin

FB/R

3

solder pin

V

O1

V

O2

V

O3

FB/R

1

23

150

150

150

pF

pF

pF

channel 1

100

nF

channel 2

100

nF

channel 3

100

nF

1 kΩ

5.6 Ω

0.47 µF
(63 V)

5.6 Ω

0.47 µF
(63 V)

5.6 Ω

0.47 µF
(63 V)

3.3

3.3

3.3

pF

pF

pF

V

O1

22

V

P1

21

FB/R

2

20

V

O2

19

V

P2

18

FB/R

3

17

V

O3

16

V

P3

15

GNDX

14

SCL

13

SDA

5 V

SCL

10 nF

50

Ω

10 kΩ

10 kΩ

LIMAC

Fig.16 Test board utilizing internal positive feedback only (FPOL = 1).

1998 Dec 04 33

10 nF

10 kΩ

MHB267

VPX
VP1 sense

VP sense
V

P

GND

VINDC
LIM
5 V

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

TDA4886A

103

81

CLI

50 Ω

V

V

V

HFB

I1

I2

I3

OSD

3

50 Ω 50 Ω

50 Ω

10 nF
150 pF

10 nF

50 Ω
150 pF

5 kΩ

50 Ω

10 nF

5 kΩ

50 Ω

10 kΩ 10 kΩ

OSD

5 kΩ

J1
J2

+

0.47 µF

−

J3

2

150 pF

SCLSDA

OSD

FBL

1

50 Ω 50 Ω

3.3 pF

100 nF

TDA4886A

3.3 pF
100 nF

50 Ω

LIMAC

10 nF

Dimensions are in mm.

Fig.17 Top view of the printed-circuit board (for the bottom view see Fig.18).

1998 Dec 04 34

10 kΩ

3.3 pF

150 pF

5.6 Ω
1 kΩ

150 pF

10 kΩ

100

nF

10 kΩ

150 pF

10 kΩ
10 nF

V

O1

1 kΩ

−

0.47 µF

+

V

O2

V

O3

0.47 µF

0.47 µF

−
+

−
+

U19

5.6 Ω

5.6 Ω

5.6 Ω

MHB268

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

handbook, full pagewidth

TDA4886A

103

81

Dimensions are in mm.

Fig.18 Bottom view of the printed-circuit board (for the top view see Fig.17).

1998 Dec 04 35

100 pF
100 nF

100 nF
100 pF

MHB217

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

12.2 Recommendations for building the application
board

• General

– Double-sided board
– Short HF loops by large ground plane on the rear
– SMD components with minimum parasitics.

• Voltage outputs

– Capacitive loads as small as possible
– Be aware of internal output resistance

(typically 75 Ω).

• Supply voltages

– Capacitors as near as possible to the pins
– Use electrolytic capacitors with small serial

resistance and inductance.

TDA4886A

1998 Dec 04 36

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1998 Dec 04 37

13 INTERNAL CIRCUITRY

SYMBOL AND

PIN

DESCRIPTION

1 FBL; fast

blanking input
for OSD
insertion

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

open-circuit base

MHA653

5 V

0 V

V

P

1

1 kΩ

50 µA 50 µA 50 µA 50 µA

signal
blanking

OSD1
blanking

OSD2
blanking

Philips Semiconductors Product specification

140 MHz video controller with I

OSD3
blanking

MHA928

2 OSD1; OSD

input channel 1

3 OSD

; OSD

2

input channel 2

open-circuit base

open-circuit base

MHA653

MHA653

5 V

0 V

5 V

0 V

V

P

V

50 µA

P

50 µA

1 kΩ

1 kΩ

signal blanking

disable OSD

FBL

signal blanking

FBL

MHB197

disable OSD

MHB198

2

C-bus

V

P

2

3

1 kΩ

V

P

1 kΩ

TDA4886A

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1998 Dec 04 38

SYMBOL AND

PIN

DESCRIPTION

4 OSD

input channel 3

; OSD

3

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

open-circuit base

MHA653

5 V

0 V

V

P

V

P

4

1 kΩ

50 µA

signal blanking

disable OSD

Philips Semiconductors Product specification

140 MHz video controller with I

5 CLI; vertical

blanking input
(input clamping)

V5> 0.2 V:
open-circuit base

≤ 0.2 V:

V

5

source current rising
with decreasing
voltage

MHA651

5 V

2.5 V
0 V

2V

BE

1 kΩ

V

P

6 kΩ

V

P

5

10 kΩ

1 kΩ

10 kΩ

power

on/down

26 µA

FBL

MHA619

MHB199

3 V + V

BE

2

C-bus

TDA4886A

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1998 Dec 04 39

SYMBOL AND

PIN

DESCRIPTION

6V

; signal input

I1

channel 1

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

outside clamping
pulse: open-circuit
base with base
current
compensation

during clamping:

black

shoulder

video signal

sync

4.7 V

4 V

3.7 V

MIRROR

1 : 1

V

P

6

V

P

−135 to +135 µA

input clamping (pin 5)

MHA652

1.8 V + V

BE

135 µA
0 µA

240 µA

700 Ω

220 µA

signal

MHB200

Philips Semiconductors Product specification

140 MHz video controller with I

2

C-bus

7V

; supply

P

voltage

21 mA

7

MHA621

TDA4886A

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1998 Dec 04 40

SYMBOL AND

PIN

DESCRIPTION

8V

; signal input

I2

channel 2

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

outside clamping
pulse: open-circuit
base with base
current
compensation

during clamping:

black

shoulder

video signal

sync

4.7 V

4 V

3.7 V

MIRROR

1 : 1

V

P

8

V

P

−135 to +135 µA

input clamping (pin 5)

MHA652

1.8 V + V

BE

135 µA
0 µA

240 µA

700 Ω

220 µA

signal

MHB201

Philips Semiconductors Product specification

140 MHz video controller with I

2

C-bus

9 GND; ground

10 V

; signal input

I3

channel 3

outside clamping
pulse: open-circuit
base with base
current
compensation

during clamping:

−135 to +135 µA

black

shoulder

sync

input clamping (pin 5)

video signal

4.7 V

4 V

3.7 V

MHA652

10

1.8 V + V

V

BE

P

135 µA
0 µA

9

MIRROR

1 : 1

240 µA

MHA623

700 Ω

V

P

signal

220 µA

MHB202

TDA4886A

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1998 Dec 04 41

SYMBOL AND

PIN

DESCRIPTION

11 HFB; horizontal

flyback input
(output
clamping,
blanking)

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

> 0.2 V:

V

11

open-circuit base
V

≤ 0.2 V: source

11

current rising with

MHA649

5 V

0 V

2V

BE

6 kΩ

V

P

10 kΩ

27 µA

clamping

decreasing voltage

12 kΩ

Philips Semiconductors Product specification

140 MHz video controller with I

27 µA

blanking

12 SDA; I2C-bus

serial data
input/output

13 SCL; I2C-bus

clock input

no acknowledge:
open-circuit base

during
acknowledge:
I

=4mA

12

open-circuit base

MHA648

5 V

0 V

MHA647

5 V

0 V

V

P

11

3 V + V

BE

1 kΩ

3 µA 70 µA 19 µA

10

12

acknowledge

13

kΩ

10 kΩ

10 kΩ

power on/down

2.46 V + V

MHB203

19 µA

BE

1.7 V

MHA625

2

C-bus

TDA4886A

2.46 V + V

MHB204

BE

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1998 Dec 04 42

SYMBOL AND

PIN

DESCRIPTION

14 GNDX; signal

channel ground

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

14

MHB205

Philips Semiconductors Product specification

140 MHz video controller with I

15 V

P3

voltage
channel 3

16 V

O3

output channel 3

; supply

; signal

I15=21mA

reference black level

0.1 to 2.8 V

pedestal black level

0.1 to 2.8 V

MHA655

brightness

reference black level during output clamping

control bit PEDST = 0

MHA656

brightness

pedestal black level during output clamping

15

MHB206

V

P

8 kΩ

1.5 kΩ

3.5 pF

500 Ω

2

C-bus

V

P

16

75 Ω

1 kΩ

10 µA

MHB207

control bit PEDST = 1

TDA4886A

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1998 Dec 04 43

SYMBOL AND

PIN

DESCRIPTION

17 FB/R

feedback input/
reference
voltage output
channel 3

;

3

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

open-circuit base

−300 to +300 µA;

5.77 to 4.05 V

feedback reference 5.77 to 4.05 V

PEDST = 0

PEDST = 1

control bit FPOL = 0
control bit FPOL = 1

MHB215

V

P

40 I

17

100 Ω

1 kΩ

3 kΩ

I

2 I

5.77 to 4.05 V

Philips Semiconductors Product specification

140 MHz video controller with I

18 VP2; supply

voltage
channel 2

I18=21mA

10 µA10 µA

15 kΩ

15 kΩ

1 kΩ

5.77 to 4.05 V

DC coupling; Vs1 = 0 V; Vs2 = 1 V; I = 0 (control bit FPOL = 0)
AC coupling; Vs1 = 1 V; Vs2 = 0 V; I = 7.5 µA (control bit FPOL = 1)

18

MHB218

Vs1

Vs2

MHB208

2

C-bus

TDA4886A

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1998 Dec 04 44

SYMBOL AND

PIN

DESCRIPTION

19 V

O2

output channel 2

; signal

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

reference black level

0.1 to 2.8 V

brightness

MHA655

V

P

V

P

500 Ω

Philips Semiconductors Product specification

140 MHz video controller with I

pedestal black level

0.1 to 2.8 V

reference black level during output clamping

control bit PEDST = 0

MHA656

brightness

pedestal black level during output clamping

control bit PEDST = 1

19

75 Ω

1 kΩ

10 µA

MHB209

8 kΩ

1.5 kΩ

3.5 pF

2

C-bus

TDA4886A

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1998 Dec 04 45

SYMBOL AND

PIN

DESCRIPTION

20 FB/R

feedback input/
reference
voltage output
channel 2

;

2

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

open-circuit base

−300 to +300 µA;

5.77 to 4.05 V

feedback reference 5.77 to 4.05 V

PEDST = 0

PEDST = 1

control bit FPOL = 0
control bit FPOL = 1

MHB215

V

P

40 I

20

100 Ω

1 kΩ

3 kΩ

I

2 I

5.77 to 4.05 V

Philips Semiconductors Product specification

140 MHz video controller with I

21 VP1; supply

voltage
channel 1

I21=21mA

10 µA10 µA

15 kΩ

15 kΩ

1 kΩ

5.77 to 4.05 V

DC coupling; Vs1 = 0 V; Vs2 = 1 V; I = 0 (control bit FPOL = 0)
AC coupling; Vs1 = 1 V; Vs2 = 0 V; I = 7.5 µA (control bit FPOL = 1)

21

MHB211

Vs1

Vs2

MHB210

2

C-bus

TDA4886A

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1998 Dec 04 46

SYMBOL AND

PIN

DESCRIPTION

22 V

O1

output channel 1

; signal

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

reference black level

0.1 to 2.8 V

brightness

MHA655

V

P

V

P

500 Ω

Philips Semiconductors Product specification

140 MHz video controller with I

pedestal black level

0.1 to 2.8 V

reference black level during output clamping

control bit PEDST = 0

MHA656

brightness

pedestal black level during output clamping

control bit PEDST = 1

22

75 Ω

1 kΩ

10 µA

MHB212

8 kΩ

1.5 kΩ

3.5 pF

2

C-bus

TDA4886A

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1998 Dec 04 47

SYMBOL AND

PIN

DESCRIPTION

23 FB/R

feedback input/
reference
voltage output
channel 1

;

1

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

open-circuit base

−300 to +300 µA;

5.77 to 4.05 V

feedback reference 5.77 to 4.05 V

PEDST = 0

PEDST = 1

control bit FPOL = 0
control bit FPOL = 1

MHB215

V

P

40 I

23

100 Ω

1 kΩ

3 kΩ

I

2 I

5.77 to 4.05 V

Philips Semiconductors Product specification

140 MHz video controller with I

10 µA10 µA

15 kΩ

15 kΩ

1 kΩ

5.77 to 4.05 V

DC coupling; Vs1 = 0 V; Vs2 = 1 V; I = 0 (control bit FPOL = 0)
AC coupling; Vs1 = 1 V; Vs2 = 0 V; I = 7.5 µA (control bit FPOL = 1)

Vs1

Vs2

MHB213

2

C-bus

TDA4886A

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1998 Dec 04 48

SYMBOL AND

PIN

DESCRIPTION

24 LIM; beam

current limiting
input

CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT

open-circuit voltage

= 5.0 V

V

24

V

< 4.5 V:

24

open-circuit base

V

P

24

1 kΩ

10 kΩ

21 µA

5.0 V

MHB214

Philips Semiconductors Product specification

140 MHz video controller with I

2

C-bus

TDA4886A

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

14 PACKAGE OUTLINE

SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)

D

seating plane

L

Z

24

e

b

b

13

TDA4886A

SOT234-1

M

E

A

2

A

A

1

w M

1

c

(e )

M

1

H

pin 1 index

1

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

A

A

UNIT b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

mm

OUTLINE
VERSION

SOT234-1

max.

4.7 0.51 3.8

12

min.

max.

IEC JEDEC EIAJ

1.3

0.8

b

1

0.53

0.40

REFERENCES

cEe M

0.32

0.23

(1) (1)

D

22.3

21.4

9.1

8.7

E

12

(1)

Z

L

3.2

2.8

EUROPEAN

PROJECTION

M

10.7

10.2

E

12.2

10.5

e

1

w

H

0.181.778 10.16

ISSUE DATE

92-11-17
95-02-04

max.

1.6

1998 Dec 04 49

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

15 SOLDERING

15.1 Introduction to soldering through-hole mount
packages

This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can be
found in our

Packages”

Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.

15.2 Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.

15.4 Suitability of through-hole mount IC packages for dipping and wave soldering methods

DBS, DIP, HDIP, SDIP, SIL suitable suitable

“Data Handbook IC26; Integrated Circuit

(document order number 9398 652 90011).

PACKAGE

The total contact time of successive solder waves must not
exceed 5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

15.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.

SOLDERING METHOD

DIPPING WAVE

(1)

TDA4886A

). If the

stg(max)

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

1998 Dec 04 50

Philips Semiconductors Product specification

140 MHz video controller with I2C-bus

16 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

TDA4886A

18 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1998 Dec 04 51

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone]

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545104/00/01/pp52 Date of release: 1998 Dec 04 Document order number: 9397 750 04817