Datasheet TDA4882 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA4882

Advanced monitor video controller
for OSD

Preliminary specification
File under Integrated Circuits, IC02

Philips Semiconductors

December 1994

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

FEA TURES

• 85 MHz video controller

• Fully DC controllable

• 3 separate video channels

• Input black level clamping

• White level adjustment for 2

channels only

• Brightness control with correct grey
scale tracking

• Contrast control for all 3 channels
simultaneously

• Cathode feedback to internal
reference for cut-off control, which
allows unstabilized video supply
voltage

• Current outputs for RGB signal
currents

• RGB voltage outputs to external
peaking circuits

• Blanking and switch-off input for
screen protection

• Sync on green operation possible

• OSD application very easily.

GENERAL DESCRIPTION

The TDA4882 is an RGB amplifier for
colour monitor systems with super
VGA performance, intended for DC or
AC coupling of the colour signals to
the cathodes of the CRT.

With special advantages the circuit
can be used in conjunction with the
TDA485X monitor deflection IC
family.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
I

P

V

P

I(b-w)

positive supply voltage (pin 7) 7.2 8.0 8.8 V
supply current − 48 − mA
input voltage (black-to-white;

− 0.7 1.0 V

pins 2, 5 and 8)

V

O(b-w)

I

O(b-w)

output voltage (black-to-white;
pins 19, 16 and 13)

output current (black-to-white;

nominal contrast; pins 3
and 11 open-circuit

− 0.79 − V

− 50 − mA

pins 20, 17 and 14)

I

OM

peak output current (pins 20,

−−100 mA

17 and 14)
B bandwidth −3dB 70 85 − MHz
G

nom

∆G gain control difference for

nominal gain (pins 2, 5 and 8

to pins 19, 16 and 13)

nominal contrast; pins 3
and 11 open-circuit

relative to G

nom

− 1 − dB

−5 − +2.6 dB

2 channels
C
C
∆V

c
OSD

bl

contrast control V6= 1 to 6 V −22 − +3.4 dB

minimum contrast for OSD V6= 0.7 V −−40 − dB

brightness control related to

−11 − +34 %
nominal output signal
amplitude

T

amb

operating ambient temperature −20 − +70 °C

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA4882 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

December 1994 2

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

BLOCK DIAGRAM

handbook, full pagewidth

V

P

10 kΩ

brightness

control

signal

22 nF

input

75 Ω

10 MΩ

V

P

10 kΩ

gain
control

signal

22 nF

input

75 Ω

10 MΩ

V

P

10 kΩ

contrast
control

VP = 8 V

VOLTAGE

1

CONVERTER

2

3

4

5

6

CLAMP

CLIPPING

VOLTAGE

CONVERTER

CLAMP

CLIPPING

REF

GAIN

VOLTAGE

CONVERTER

CHANNEL 1

CHANNEL 2

TDA4882

20

19

18

17

16

15

6.2 V

current
output

voltage
output

33 Ω 33 Ω

feedback

current
output

voltage
output

33 Ω 33 Ω

feedback

BFQ235

BFQ235

1.5 kΩ

68 kΩ

6.8 kΩ

1.5 kΩ

BFQ236

1 kΩ

BFQ256

10 Ω

15 kΩ

10 Ω

BAV21

V

= 90 V

CRT

220 Ω

8 V

10 kΩ

cut-off
control

V

= 90 V

CRT

BAV21

220 Ω

68 kΩ

15 kΩ

6.8 kΩ

40 MHz

8 V

10 kΩ
cut-off

control

25 MHz

CRT

60 MHz

P

22 nF

10 MΩ

7

8

9

10

input
clamping

blanking

+

CLAMP

CLIPPING

VOLTAGE

CONVERTER

PULSE

DECODER

CHANNEL 3

test mode
ultra black

output clamping

14

13

12

5.8 V
11

V

signal
input

75 Ω

horizontal blanking
switch off

clamping pulse
vertical blanking
test mode

Fig.1 Block diagram and basic application circuit for DC and AC coupling.

December 1994 3

current
output

voltage
output

18 Ω

feedback

10 kΩ

V

18 Ω

P

gain
control

BFQ235

860 Ω

10 Ω

1 kΩ

10 Ω

BFQ256

10 kΩ

horizontal blanking

BFQ236

47 nF

V

= 65 V

CRT

BAV21

100 Ω

V

93
kΩ

CRT

10 kΩ

cut-off
control

MED910

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

PINNING

SYMBOL PIN DESCRIPTION

BR

C

V

I1

G

C1

GND 4 ground
V

I2

C

C

V

P

V

I3

HBL 9 horizontal blanking, switch-off
CL 10 input clamping, vertical blanking, test mode
G

C3

FB

3

V

O3

I

O3

FB

2

V

O2

I

O2

FB

1

V

O1

I

O1

1 brightness control
2 signal input Channel 1
3 gain control Channel 1

5 signal input Channel 2
6 contrast control, OSD switch
7 supply voltage
8 signal input Channel 3

11 gain control Channel 3
12 feedback Channel 3
13 voltage output Channel 3
14 current output Channel 3
15 feedback Channel 2
16 voltage output Channel 2
17 current output Channel 2
18 feedback Channel 1
19 voltage output Channel 1
20 current output Channel 1

BR

1

C

V

2

I1

G

3

C1

4

GND

V

5

I2

C

V

V

HBL

C

P

I3

CL

TDA4882

6

7

8

9

10 11

Fig.2 Pin configuration.

I

20

O1

V

19

O1

FB

18

1

I

17

O2

V

16

O2

FB

15

2

I

14

O3

V

13

O3

FB

12

3

G

C3

FUNCTIONAL DESCRIPTION

The RGB input signals 0.7 V (p-p) are
capacitively coupled into the
TDA4882 (pins 2, 5 and 8) from a low
ohmic source and are clamped to an
internal DC voltage (artificial black
level). Composite signals will not
disturb normal operations because an
internal clipping circuit cuts all signal
parts below black level. Channels 1
and 3 have a maximum total voltage
gain of 7 dB (maximum contrast and
maximum individual channel gain),
Channel 2 of 4.4 dB (maximum
contrast and nominal gain). With the
nominal channel gain of 1 dB and
nominal contrast setting the nominal
black-to-white output amplitude is

0.79 V (p-p).

DC voltages are used for brightness,
contrast and gain control.

Brightness control yields a
simultaneous signal black level shift
of the three channels relative to a
reference black level. For nominal
brightness (pin 1 open-circuit) the
signal black level is equal to the
reference black level. Contrast
control is achieved by a voltage at
pin 6 and affects the three channels
simultaneously. To provide the
correct white point, an individual gain
control (pins 3 and 11) adjusts the
signals of Channels 1 and 3
compared to the reference
Channel 2. Gain setting changes
contrast as well as brightness to
achieve correct grey scale tracking.

Eachoutput stage provides a current
output (pins 20, 17 and 14) and a
voltage output (pins 19, 16 and 13).
External cascode transistors reduce
power consumption of the IC and
prevent breakdown of the output
transistors. Signal output currents
and peaking characteristics are
determined by external components
at the voltage outputs and the video
supply. The channels have separate
internal feedback loops which ensure
large signal linearity and marginal
signal distortion in spite of output
transistor thermal V

variation.

BE

The clamping pulse (pin 10) is used
for input clamping only. The input
signals have to be at black level
during the clamping pulse and are

December 1994 4

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

clamped to an internal artificial black
level. The coupling capacitors are
used in this way for black level
storage. Because the threshold for
the clamping pulse is higher than that
for vertical blanking (pin 10) the rise
and fall times of the clamping pulse
have to be faster than 75 ns/V during
transition from 1 V to 3.5 V.

The vertical blanking pulse will be
detected if the input voltage (pin 10) is
higher than the threshold voltage for
approximately 320 ns but does not
exceed the threshold for the clamping
pulse in the time between. During the
vertical blanking pulse the input
clamping is disabled in order to avoid
misclamping in the event of
composite input signals. The input
signal is blanked and the artificial
black level is inserted instead.
Additionally the brightness is
internally set to its nominal value, thus
the output signal is at reference black

level. The DC value of the reference
black level will be adjusted by cut-off
stabilization (see below).

During horizontal blanking (pin 9)
the output signal is set to reference
black level as previously described
and output clamping is activated. If
the voltage at pin 9 exceeds the
switch-off threshold the signal is
blanked and switched to ultra black
level for screen protection and spot
suppression during V-flyback. Ultra
black level is the lowest possible
output voltage (at voltage outputs)
and does not depend on cut-off
stabilization.

For cut-off stabilization (DC
coupling to the CRT) respectively
black level stabilization (AC
coupling) the video signal at the
cathode or the coupling capacitor is
divided by an adjustable voltage
divider and fed to the feedback inputs

(pins 18, 15 and 12). During
horizontal blanking time this signal is
compared with an internal DC voltage
of approximately 5.8 V. Any
difference will lead to a reference
black level correction by charging or
discharging the integrated capacitor
which stores the reference black level
information between the horizontal
blanking pulses.

For OSD fast switching of control
pin 6 to less than 1 V (e.g. 0.7 V)
blanks the input signals. The OSD
signals can easily be inserted to the
external cascode transistor
(see Fig.3).

During test mode (pins 9 and 10
connected to VP) the black levels at
the voltage outputs (pins 19, 16 and

13) are internally set to typical 0.5 V
nominal brightness, 3 V DC at signal
inputs (pins 2, 5 and 8).

OSD

fast blanking

1 kΩ

4.7 kΩ

100 pF

contrast

PH2222

20

Channel 1

17

Channel 2

6

14

current
output

TDA4882

Fig.3 OSD application.

150 Ω

BFQ235

PH2222

Channel 3

220 Ω

depending on
channel gain
1 kΩ to 10 kΩ

OSD
signal input

December 1994 5

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

P

V

I

V

ext

I

O(AV)

I

OM

P

tot

T

stg

T

amb

T

j

V

ESD

supply voltage (pin 7) 0 8.8 V
input voltage (pins 2, 5 and 8) −0.1 V

P

V

external DC voltage

pins 20, 17 and 14 −0.1 V

P

V
pins 19, 16 and 13 no external voltages
pins 1, 3, 6 and 11 −0.1 V
pin 9 −0.1 V
pin 10 −0.1 V

P

+ 0.7 V

P

+ 0.7 V

P

V

average output current (pins 20, 17 and 14; note 1) 0 50 mA
peak output current (pins 20, 17 and 14) 0 100 mA
total power dissipation − 1200 mW
storage temperature −25 +150 °C
operating ambient temperature −20 +70 °C
junction temperature −25 +150 °C
electrostatic handling for all pins (note 2) −500 +500 V

Notes

1. Signal amplitude of 50 mA black-to-white is possible if the average current (including blanking times and signal
variation against time) does not exceed 50 mA. The maximum power dissipation of 1200 mW has to be considered.

2. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

thj-a

thermal resistance from junction to ambient in free air 65 K/W

December 1994 6

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

CHARACTERISTICS

= 8.0 V; T

V

P

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

P

I

P

Video signal inputs (Channel 1: pin 2, Channel 2: pin 5 and Channel 3: pin 8)

V

I(b-w)

V

I(cl)2, 5, 8

I

I2, 5, 8

Brightness control (pin 1); note 2; see Fig.5
V

1

R

1

V

1(nom)

∆V

bl

∆V

BT

= +25 °C; all voltages measured to GND (pin 4); note 1; see also Fig.4; unless otherwise specified.

amb

supply voltage (pin 7) 7.2 8.0 8.8 V
supply current (pin 7) 36 48 60 mA

input voltage

− 0.7 1.0 V
(black-to-white value;
pins 2, 5 and 8)

DC voltage during input

2.8 3.1 3.4 V
clamping (artificial black +
VBE)

DC input current no clamping;

V

I2, 5, 8=VI(cl)2, 5, 8

T

= −20 to +70 °C

amb

during clamping;
V

I2, 5, 8=VI(cl)2, 5, 8

;

± 0.7 V

−0.05 +0.05 +0.250 µA

±50 ±75 ±120 µA

input voltage 1.0 − 6.0 V
input resistance 40 50 60 kΩ
input voltage for nominal

pin 1 open-circuit 2.0 2.25 2.5 V

brightness
black level voltage change

at voltage outputs referred
to reference black level
during output clamping

V1= 1.0 V −13 −11 −9.5 %
V

=6.0V 303437%

1

pin 1 open-circuit −−0.8 %

(V9> 1.6 V) related to
output signal amplitude with
nominal 0.7 V (p-p) input
signal and nominal
contrast (V6= 4.3 V) for
any gain setting

difference of ∆Vbl between

− 0 ±1.2 %
any two channels

December 1994 7

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Contrast control (pin 6); note 3; see Fig.6

V

6

V

6(max)

V

6(nom)

I

6

C

c

V

6(min)

TR

O

t

dfC

t

drC

t

fC

t

rC

Gain control (pin 3 for Channel 1 and pin 11 for Channel 3); Fig.8; note 7
V

3, 11

V

3, 11(nom)

R

3, 11

∆G gain control difference

input voltage 1.0 − 6.0 V
maximum input voltage −−V
input voltage for nominal

note 4 − 4.3 − V

−1V

P

contrast
input current V6= 4.3 V −5 −1 −0.1 µA
contrast relative to nominal

contrast

V6= 6.0 V; pins 3 and 11
open-circuit

= 1.0 V; pins 3 and 11

V

6

2.4 3.4 − dB

−26 −22 −19 dB

open-circuit

input voltage for minimum

pins 3 and 11 open-circuit − 0.7 − V

contrast
tracking of output signals

1V<V6<6 V; note 5 − 0 0.5 dB

of Channels 1, 2 and 3
delay between leading

edges (falling) of step in
contrast voltage and output

V6= 4.3 V to 0.7 V; input
fall time at pin 6:
t

= 2 ns; Fig.7; note 6

fCC

− 720ns

signals at voltage outputs
(pins 19, 16 and 13)

delay between trailing
edges (rising) of step in
contrast voltage and output

V6= 0.7 V to 4.3 V; input
rise time at pin 6:
t

= 2 ns; Fig.7; note 6

rCC

− 15 25 ns

signals at voltage outputs
(pins 19, 16 and 13)

fall time of output signals at
voltage outputs (pins 19, 16
and 13)

rise time of output signals
at voltage outputs (pins 19,
16 and 13)

90% to 10% amplitude;
input fall time at pin 6:
t

= 2 ns; Fig.7; note 6

fCC

10% to 90% amplitude;
input rise time at pin 6:
t

= 2 ns; Fig.7; note 6

rCC

− 615ns

− 615ns

input voltage 1.0 − 6.0 V
input voltage for nominal

pins 3 and 11 open-circuit 3.6 3.75 3.95 V

gain
input resistance 44 55 66 kΩ

V
relative to nominal gain
(Channels 1 and 3 only)

= 4.3 V; V

6

V

= 4.3 V; V

6

= 6 V 2 2.6 3.3 dB

3, 11

=1V −5.5 −5 −4.5 dB

3, 11

December 1994 8

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Feedback input (Channel 1: pin 18, Channel 2: pin 15 and Channel 3: pin 12); Fig.9; note 8

V

ref

I

O18, 15, 12(max)

∆V

bl(CRT)

∆V

ref(T)

∆V

ref(VP)

Voltage outputs (Channel 1: pin 19, Channel 2: pin 16 and Channel 3: pin 13)

V

O(b-w)

V

blx(max)

V

bl(SO)

V

bl(TST)

S/N signal-to-noise ratio note 11 − 50 44 dB
d

O(th)

∆V

bl(fl)

V

off

∆V

O(b-w)(T)

Current outputs (Channel 1: pin 20, Channel 2: pin 17 and Channel 3: pin 14); note 14
I

O(b-w)

V

; V

20-19

V

14-13

I

bl(SO)

17-16

internal reference voltage 5.6 5.8 6.1 V
maximum output current during output clamping;

V

18, 15, 12

=3V

−500 −100 −60 nA

black level variation at CRT note 9 0 40 200 mV
variation of V

in the

ref

T

= −20 to +70 °C 0 20 50 mV

amb

temperature range
variation of V

with supply

ref

7.2 V ≤ VP≤ 8.8 V 0 60 100 mV

voltage

nominal signal output
voltage

pins 3 and 11 open-circuit;

V6= 4.3 V; V

I(b-w)

= 0.7 V

0.69 0.79 0.89 V

(black-to-white value)
maximum adjustable black

level voltage
black level voltage during

switch-off, equal to

during output clamping;

T

= −20 to +70 °C

amb

V9=VP; RO=33Ω;

T

= −20 to +70 °C

amb

1 1.2 1.4 V

30 45 100 mV

minimum adjustable black
level voltage

black level voltage during
test mode

output thermal distortion I
black level variation

V9=VP; V10=VP; pin 1

0.3 0.7 1.2 V
open-circuit;
V

I2, 5, 8=VI(cl)2, 5, 8

= 50 mA; note 12 − 0.6 1 %

O(b-w)

; note 10

line frequency 30 kHz − 0.5 4.5 mV

between clamping pulses
maximum offset during

sync clipping
variation of nominal output

signal (black-to-white
value) with temperature

output current
(black-to-white value)

;

start of HF-saturation
voltage of output transistors

output current during

V

I2, 5, 8

< V

I(cl)2, 5, 8

; Fig.10;

0 7 15 mV

note 13
pins 3 and 11 open-circuit;

V6= 4.3 V; V
T

= −20 to +70 °C

amb

I(b-w)

= 0.7 V;

0 2.5 10 %

− 50 − mA
with peaking −−100 mA
IO=50mA −−2.0 V
I

= 100 mA −−2.2 V

O

V9=VP; RO=33Ω 0 20 900 µA

switch-off

December 1994 9

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Frequency response at voltage outputs (Figs 11, 12 and 13; note 15)

∆G

(f)

gain decrease by frequency
response at pins 19, 16 and
13

t

r(O)

rise time at voltage output
(pins 19, 16 and 13)

dV

O

overshoot of output signal
pulse related to actual
output pulse amplitude

Crosstalk at voltage outputs with speed up circuit (Figs 14, 15 and 16; note 16)

α

cr(tr)

transient crosstalk −−0.1 −
Threshold voltages for clamping, blanking and switch-off (pins 9 and 10); note 17
V

9

threshold for horizontal

blanking (blanking, output

clamping)

threshold for switch-off

(blanking, minimum black

level, no output clamping)
R

9

t

d9

input resistance against ground 50 80 110 kΩ

delay between horizontal

blanking input and output

signal blanking
V

10

threshold for vertical

blanking (blanking, no

input clamping)

threshold for clamping

(input clamping, no

blanking)

threshold for test mode (no

clamping, no blanking, for

V

see above)

bl(TST)

I

10

t

r, f10

current V10< VP− 1V −3 −1 −µA

rise and fall time for

clamping pulse
t

w10

t

d10

width of clamping pulse 0.6 −−µs

delay between vertical

blanking input and internal

blanking

70 MHz; single channel − 1.3 3 dB

10% to 90% amplitude;

− 4.1 5.0 ns

input rise time = 1 ns
single channel; input rise

− 48%
time = 2.5 ns;
V

= 0.7 V; pins 3 and

I(b-w)

11 open-circuit; V6= 4.3 V

1.2 1.4 1.6 V

5.8 6.5 6.8 V

input rise time at

− 40 60 ns
pin 9 > 100 ns; Fig.17;
note 18

Fig.18; note 19 1.2 1.4 1.6 V

Fig.18; note 19 2.6 3.0 3.5 V

for test mode also

VP− 1 − V

P

V

V9> 6.8 V (switch-off)

V

≥ VP− 1V − 100 −µA

10

Fig.18; note 19 −−75 ns/V

Fig.18; note 19 260 320 380 ns

December 1994 10

Philips Semiconductors Preliminary specification









Advanced monitor video controller for OSD TDA4882

Notes to the characteristics

1. Definition of levels:
a) Artificial black level: internal signal level behind input emitter follower during input clamping and signal clipping.

This level is inserted instead of the input signal during blanking.

b) Reference black level: DC voltage during output clamping at voltage outputs, not influenced by brightness,

contrast or gain setting, adjustable by cut-off stabilization.
c) Cut-off level: corresponding DC voltage at CRT cathode in closed feedback loop.
d) Black level: actual signal black level at either voltage outputs or cathode, can be adjusted by (brightness × gain),

refers to reference black level or cut-off level respectively.
e) Ultra black level, switch-off level: lowest adjustable reference black level, lowest signal level at voltage outputs.
f) The minimum guaranteed control range for reference black level is 0.1 to 1 V.

The ultra black level is depending on the external resistor RO at voltage outputs (pins 13, 16 and 19) to ground.

R

V

g)

bl SO()

2. Linear control range is 1 to 6 V for V1, independent from supply voltage.

3. Linear control range is 1 to 6 V for V6, independent from supply voltage. Open pin 6 leads to absolute maximum
contrast setting. It is recommended to not exceed V6=VP−1 V in order to avoid saturation of internal circuitry. For
V6< V

≈ 0.7 V a small negative signal (≈ −40 dB) will appear. For frequency dependency of contrast control see

6(min)

note 15.

4. Definition for nominal output signals: input V
V6=V

5.

Tr 20 maximum of

: signal output amplitude in Channel x at any contrast setting between 1 and 6 V.

A

x

: signal output amplitude in Channel x at nominal contrast and same gain setting.

A

x0

6(nom)

× [dB]=

.

6. Typical step in contrast voltage and response at signal outputs for nominal input signal V
blanking input/output).

7. Linear control range is 1 to 6 V for V3 and V11, independent from supply voltage.

8. The internal reference voltage can be measured at pins 18, 15 and 12 during output clamping (V9= 2 V) in closed
feedback loop.

9. Slow variations of video supply voltage V
Change of V

CRT

10. The test mode allows testing without input and output clamping pulses. The signal inputs (pins 2, 5 and 8) have to
be biased via resistors to the previously measured clamp voltages of approximately 3 V (artificial black level + VBE).
Signal and brightness blanking is not possible during test mode. The output currents (pins 10, 17 and 14) should be
adjusted by resistors >> R0 from voltage outputs to a positive voltage (e.g. VP).

11. The signal-to-noise ratio is calculated by the formula (frequency range 1 to 70 MHz):

S

--- ­N

peak-to-peak value of the nominal signal output voltage

20

---------------------------------------------------------------------------------------------------------------------------------------------------

12. Large output swing e.g. I
VBE variation is compensated.

13. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below
black level.

O

--------------------------------

3.5 kΩ RO+

4.65 V×≈

= 0.7 V, gain pins 3 and 11 open-circuit, contrast control

I(b-w)

A

A

1





log

-------- ­A





20

×

-------- ­A

10

2



log



(see Fig.1) will be suppressed at CRT cathode by cut-off stabilization.

CRT

A

-------- ­A

A

1

30

×

-------- ­A

10

3

by 5 V leads to specified change of cut-off voltage.

RMS value of the noise output voltage

= 50 mA leeds to signal depending power dissipation in output transistors. Thermal

O(b-w)

A

A

2



log;;

-------- ­A



30

×

-------- ­A

20

3

[dB]log=

= 0.7 V (OSD fast

I(b-w)

December 1994 11

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

1

14. The output current approximately follows the equation for VO> V
= external resistor at voltage output to ground.

R

O

I

O



V

------- -

O



R

O

+

----------------- -

2.2 kΩ

1

500 µA–=

bl(SO)

and with

The external RC combination at pins 19, 16 and 13 (see Fig.1) enables peak currents during transients.

15. Frequency response, crosstalk and pulse response have been measured at voltage outputs in a special

printed-circuit board with 50 Ω line in/out connections and without peaking (see Chapter “Application information /
test”).

16. Crosstalk between any two output pins.

a) Input conditions: one channel (Channel A) with nominal input signal and minimum rise time. The inputs of the

other channels capacitively coupled to ground (Channel B). Gain pins 3 and 11 open-circuit.

b) Output conditions: output signal of Channel A controlled by contrast setting (pin 6) to V

rise time should be 5 ns. Output signal of Channel B then is V

V

c) Transient crosstalk:

α

cr tr()

B

=

------ ­V

A

O(b-w)=VB

.

O(b-w)=VA

= 0.7 V, the

d) Crosstalk as a function of frequency has been measured without peaking circuit, with nominal input signal and

nominal settings.

17. The internal threshold voltages are derived from a stabilized voltage. The internal pulses are generated while the

input pulses are higher than the thresholds. Voltages of less than −0.1 V at pins 9 and 10 can influence black level
control and should be avoided.

18. The delay between horizontal blanking input at pin 9 (HBL pulse) and output signal blanking as well as brightness

blanking (∆Vbl) at pins 19, 16 and 13 depends on the input rise time of the HBL pulse. The specified values for t

d9

are valid for HBL rise times greater than 100 ns only.

19. For 75 ns/V < t

< 240 ns/V generation of internal input clamping and blanking pulse is not defined. Any pulses not

rf10

exceeding the threshold of input clamping (typical 3 V) will be detected as blanking pulse.

December 1994 12

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

input signals

input signal at
pins 2, 5 and 8
with sync (on green)

input clamping pulse
at pin 10

horizontal blanking and
output clamping pulse
at pin 9

internal signal
behind input stage

sync clipping to

artificial black level

output signals

(pins 19, 16 and 13)

at nominal gain and
contrast setting
and

maximum/nominal/minimum
brightness setting

at nominal gain and
maximum brightness setting

and
maximum/nominal/minimum
contrast setting

at nominal contrast and
maximum brightness setting
and
maximum/nominal/minimum
gain setting

signal at CRT cathode

at nominal gain and
contrast setting
and maximum brightness setting

video portion

video signal

black level equal to
artificial black level + V
by input clamping (approximately 3 V)

horizontal flyback and output clamping

black level equal to artificial
black level by input clamping and
storage by coupling capacitor

inserted artificial black level

max.

nom.

min.

∆ black level
due to brightness setting

brightness is set to nominal value during horizontal blanking

max.

nom.

min.

max.
nom.

min.

reference black level

∆ black level for

maximum brightness

reference black level

grey scale

reference black level
ultra black level
ground

high tension supply
voltage (e.g. 90 V)

(raster) cut-off level

black level

grey scale

BE

Fig.4 Signal processing.

December 1994 13

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

∆V

(%)

50

bl

40

30

20

10

0

−10

−20

02

2.24

31

468

75

(V)

V

1

400

(mV)

300

200

100

0

−100

−200

Fig.5 Typical brightness characteristic.

signal
amplitude
(mV)

1400

1200

1000

800

600

400

200

−200

(dB)

4

3

2
1

0

−1

−3

−5

−10

−20

0

0

0.7

1

2

3

4

4.3

5

7

V

6

−40

86

(V)

Fig.6 Typical contrast characteristic.

December 1994 14

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

OSD pulse

at pin 6

(V)

4.3

t

fCC

t

rCC

90%

50%

signal
amplitude

(mV)

1200

1000

0.7

output signal

at pins 19, 16 and 13

(V)

bl + V

O(b-w)

= 1.5

bl = 0.7

Fig.7 Typical OSD fast blanking input/output waveforms.

O(b-w)

V

t

dfC

10%

t

t

drC

90%

50%
10%

t

fC

t

t

rC

3

(dB)

2

1

800

600

400

200

0

Fig.8 Typical gain characteristic.

December 1994 15

3.75

0

−1

−2

−3

−4

−5

−6

−8

54321

6

V

3

87

, V11 (V)

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

5.84

V

(V)

ref

5.83

5.82

5.81

5.8

5.79

5.78

5.77

5.76

5.75

V

P

V

P

V

P

= 8.8 V

= 8.0 V

= 7.2 V

100806040200−20

(°C)

T

amb

Conditions: 0.5 V reference black level, no signal.

Fig.9 Typical variation of V

with temperature and power supply voltage.

ref

input
signal

e.g. with sync on green

Fig.10 Typical sync clipping.

December 1994 16

output
signal

/user/v8860/v1/measurements/data/pic/feedback_100_p Re/Ko-Je/12.04.94

V

off

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

signal
amplitude
(dB)

0

−3

−6

−9

−12

−15

single channel

white signal

Fig.11 Typical frequency response.

100101

frequency (MHz)

200

December 1994 17

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

800

input pulse

(mV)

600

400

200

rise time
≈ 2.5 ns ≈ 2.5 ns

0

90%

fall time

10%

1000

output pulse
at voltage
outputs

(mV)

−200

800

600

400

200

90%

rise time

4.4 ns

10%

0

40200

white pattern

single channel

fall time

4.8 ns

60

80

100

t (ns)

Fig.12 Typical pulse responses.

December 1994 18

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

10

signal
amplitude
(dB)

−5

V6 =

5

0

7 V
6 V

5 V
4 V

3 V

signal
amplitude
(dB)

−10

−15

−20

−25

−30

2 V

1 V

single channel

white signal

10

frequency (MHz)

Fig.13 Typical characteristic of contrast control as a function of frequency.

5

0

−5

−10

= 0.7 V

V

6

= 0.7 V

V

6

channel

1

1001

12070

−15

−20

−25

−30

−35

−40

−45

1

10

Fig.14 Typical crosstalk: Channel 1→ 2 and 3.

December 1994 19

frequency (MHz)

2

3

100 200

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

signal
amplitude

(dB)

−10

−15

−20

−25

−30

−35

−40

−45

5

0

−5

1

10

frequency (MHz)

channel

2

3

1

100 200

Fig.15 Typical crosstalk: Channel 2 → 1 and 3.

signal
amplitude

(dB)

−10

−15

−20

−25

−30

−35

−40

−45

5

0

channel

−5

1

10

frequency (MHz)

3

1

2

100 200

Fig.16 Typical crosstalk: Channel 3 → 1 and 2.

December 1994 20

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

delay
(ns)

80

70

60

50

40

delay1 at
begin of
brightness blanking

HBL pulse

(V)

1.45

0.2

output

signal

(V)

rise time

delay1

(bl) 0.74

30

delay2 at end of brightness blanking

20

rise (fall) time for HBL from 0.2 V to 1.45 V (ns)

120

14010080604020

(rbl) 0.5

bl = black level

rbl = reference black level

Fig.17 Typical delay between HBL pulse and brightness blanking at voltage outputs.

bl

50%

∆V

of ∆V

bl

/user/v8860/v1/measurements/data/pic/hbl2_p Ko-Je/13.04.94

t

delay2

t

10

internal pulses

3 V

1.4 V

input
clamping

blanking

t

r,f10

≤ 75 ns/V

no
clamping

t

d10

V

Fig.18 Timing of pulses at pin 10.

December 1994 21

≈1/2t

d10

t

r,f10

> 240 ns/V

t

no
clamping

t

t

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

APPLICATION INFORMATION / TEST

For high frequency measurements a special application
and printed-circuit board with only a few external
components is built. Figure 19 shows the application
circuit and Fig.20 the layout of the double sided printed
board. All components on the rear (below) are of SMD type
as well as R13, R14 and R15 on the front. Short HF loops
and minimum crosstalk between the channels as well as
input and output are achieved by properly shaped ground
areas star connected to the IC ground pin.

The HF input signal can be fed to the subclick connectors
X1, X2 and X3 by a 50 Ω line. The line is then terminated
by a 51 Ω resistor on the board. With choice of jumper
connections (JA1, JA2 and JA3) it is possible to connect
channel inputs to its input connector, to connect all
channels to one input connector (white pattern) and to
ground each input via the coupling capacitor.

For operation without input clamping (e.g. test mode) the
DC bias can be provided by VIDC (connector X21) if a
short-circuit at JA4, JA5 and JA6 is made (solder short or
small SMD resistor).

The output signal can be monitored via 50 Ω terminated
lines at the voltage outputs (subclick connectors X4, X5
and X6). With 100 Ω in parallel to the 50 Ω terminated line
the effective load resistance at the voltage outputs is 33 Ω.

The mismatch seen from the line towards the IC has no
significant effect if the line is match terminated. A peaking
circuit (C15, R16 Channel 1) can be added for realistic
loading of the voltage outputs.

Black level adjustment is done by VIOS, UFBX (connector
X21) and resistors R19, R22 and R25 (Channel 1). If R19
is equal to the effective load resistor at the voltage output
the reference black level is approximately:

U

REF

VIO1()V
V

int

VIOS V IO1()–=

int

and

V

UFBX–()

int

×+=

R22

----------­R25

is the internal reference voltage at the feedback input

(typical 5.8 V). By this it is possible to adjust the reference
black level and the voltage at the current outputs
independently.

DC control for brightness, contrast and gain is prepared at
connectors X21 and X22. Contrast control can also be set
by the potentiometer P1 (jumper JA11). The series resistor
R11 is necessary if fast OSD switching is activated via
50 Ω line (X10), a line termination can be done at the
connector X9. Clamping and blanking pulses are fed to the
IC via connectors X7 and X8. Connector X23 is used for
power supply. The capacitors C7 and C8 should be
located as near as possible to the IC pins.

December 1994 22

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

subclick connector (50 Ω)

solder points for short-circuiting

or SMD 0 Ω resistor

connector pin

jumper

C4

100 nF

JA1

V

I1

X1

R1
51 Ω

JA2

V

I2

X2

R2
51 Ω

JA3

V

I3

X3

R3
51 Ω

R8 R9
1 kΩ 1 kΩ

X7 X8 X9 X10

C1
22 nF

C2
22 nF

C3
22 nF

BR

X21

100 nF 1 nF

JA6

R6

5.1 kΩ

22 nF

X23

C/GC2

C5

22 nF

JA4

R4

5.1 kΩ

C12
22 nF

JA5

R5

5.1 kΩ

C13
22 nF

C8 C7

C14

L1

100 µH

GND

G

C1

(sense) VIOSUFBX

R7

1

BR

/G

2

V

I1

3

G

C1

C6

22 nF

4

GND

5

V

I2

6

C

C

7

V

P

8

V

I3

9

HBL

CL

R10

1 kΩ

V

IDC

110 Ω

C
C2

E1

10 µF 100 nF

20

I

O1

19

V

O1

C15

47 pF

R16 33 Ω

18

FB

1

17

I

O2

16

V

O2

C16

47 pF

R17 33 Ω

15

FB

2

TDA4882

14

I

O3

13

V

O3

C17

47 pF

R18 33 Ω

12

FB

3

1110

G

C3

C9

C11

22 nF

R11 1 kΩ

R13

100 Ω

R14

100 Ω

R15

100 Ω

220 µF

(25 V)

X4

X5

X6

JA10 JA11

E2

R19 33 Ω

R22
3 kΩ

R25 9.1 kΩ

R20 33 Ω

R23
3 kΩ

R26 9.1 kΩ

R21 33 Ω

R24
3 kΩ

R27 9.1 kΩ

C29

(multi layer)

C21 C24

C22 C25

C23 C26

C10

100 nF

C28 C27

100 nF 22 nF2.2 µF

100 nF22 nF

C18

22 nF

100 nF22 nF

C19

22 nF

100 nF22 nF

C20
22 nF

R12 1 kΩ

P1
10 kΩ

X22

G

C3

C

C

VP (sense)

GND (sense)

HBL CL

GND

(power)

V

P

OSD

Fig.19 Application circuit for test PCB.

December 1994 23

v8860/pic/messplatine_p

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

C30

P4

R7

P21

J1 J2 J3

P1

R1 R2 R3

C29

P5

R14R13

IC1

P2 P3

R15

P6

P22

C31

J11
J10

L1

R8

R28

P10

P9

P23

P8

P7

R5R4

C2C1

C13

J5

C4

C6C5 C8 C7

R23R22

C16C15

R17

C25

C19

C27C28

R24

R21R26R20R25

C23C22

C26

R19

C21

C24

C12

J4

R16

C18

Fig.20 Double sided test PCB layout.

December 1994 24

R6C14

C3

J6

R9

C9

C17

C11

R18

C20

R10

R27

R11

R12

C10

MLC783

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

RECOMMENDATIONS FOR BUILDING THE
APPLICATION BOARD

General

• Double-sided board

• Short HF loops by large ground plane on the rear.

Voltage outputs

• Capacitive loads as small as possible

• Short interconnection via resistor to ground.

Supply voltage

• Capacitors as near as possible to the pins

• Use of high-frequency capacitors (low self inductance,

e.g. SMD).

Current outputs, emitter of cascode transistors

• The external interconnection inductivity can build a
resonance together with the internal substrate capacity,
a damping resistor of 10 to 30 Ω near to the IC pin can
suppress such oscillations.

TDA4882

+

pin pin

CLCL CL

+

65834 721

Fig.21 Internal circuits.

9

MED911

10

December 1994 25

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

PACKAGE OUTLINE

seating plane

3.60

3.05

2.0

max

Dimensions in mm.

26.92

26.54

3.2

4.2

max

max

0.51
min

2.54
(9x)

20

1

0.53
max

1.73 max

0.254

M

11

6.40

6.22

10

Fig.22 Plastic dual in-line package; 20 leads (300 mil); DIP20; SOT146-1.

0.38 max

8.25

7.80

7.62

10.0

8.3

MSA258

SOLDERING
Plastic dual in-line packages

Y DIP OR WAVE

B
The maximum permissible temperature of the solder is

260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.

EPAIRING SOLDERED JOINTS

R
Apply a low voltage soldering iron below the seating plane

(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.

December 1994 26

Philips Semiconductors Preliminary specification

Advanced monitor video controller for OSD TDA4882

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

December 1994 27

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

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th

floor, Suite 51,

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SCD35 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
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Philips Semiconductors