Datasheet TDA4882 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA4882

Advanced monitor video controller
for OSD

Product specification
Supersedes data of December 1994
File under Integrated Circuits, IC02

1997 Sep 04

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION

7.1 General

7.2 Brightness control

7.3 Contrast control

7.4 Output stages

7.5 Input clamping

7.6 Vertical blanking

7.7 Horizontal blanking

7.8 Cut-off and black-level stabilization

7.9 On Screen Display

7.10 Test mode
8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 CHARACTERISTICS
11 APPLICATION AND TEST INFORMATION

11.1 Recommendations for building the application
board

12 INTERNAL PIN CONFIGURATION
13 PACKAGE OUTLINE
14 SOLDERING

14.1 Introduction

14.2 Soldering by dipping or by wave

14.3 Repairing soldered joints

15 DEFINITIONS
16 LIFE SUPPORT APPLICATIONS

1997 Sep 04 2

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

1 FEATURES

• 85 MHz video controller

• Fully DC controllable

• 3 separate video channels

• Input black-level clamping

2 GENERAL DESCRIPTION

The TDA4882 is an RGB pre-amplifier for colour monitor
systems with SVGA performance, intended for DC or AC
coupling of the colour signals to the cathodes of the CRT.

With special advantages the circuit can be used in
conjunction with the TDA485x monitor deflection IC family.

• White level adjustment for 2 channels only

• Brightness control with correct grey scale tracking

• Contrast control for all 3 channels simultaneously

• Cathode feedback to internal reference for cut-off

control, which allows unstabilized video supply voltage

• Current outputs for RGB signal currents

• RGB voltage outputs to external peaking circuits

• Blanking and switch-off input for screen protection

• Sync on green operation possible

• On Screen Display (OSD) facility.

3 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

P

I

P

V

i(b-w)

V

o(b-w)

positive supply voltage 7.2 8.0 8.8 V
supply current 36 48 60 mA
input voltage, black-to-white − 0.7 1.0 V
output voltage, black-to-white nominal contrast;

− 0.79 − V
channels 1 and 3 gain
control pins open-circuit

I

o(b-w)

I

OM

output current, black-to-white − 50 − mA

peak output current −−100 mA
B bandwidth −3dB 70 85 − MHz
G

nom

nominal voltage gain nominal contrast;

− 1 − dB
channels 1 and 3 gain
control pins open-circuit

∆G gain control difference for 2 channels relative to G
CR

contrast

C

OSD(min)

∆V

bl

contrast control V
minimum contrast for OSD V
brightness control related to nominal

=1to6V −22 − +3.4 dB

i(CC)

= 0.7 V −−40 − dB

i(CC)

nom

−5 − +2.6 dB

−11 − +34 %

output signal amplitude

T

amb

operating ambient temperature −20 − +70 °C

4 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA4882 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

1997 Sep 04 3

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

5 BLOCK DIAGRAM

handbook, full pagewidth

V

P

10 kΩ

brightness

control

signal

22 nF

input

75 Ω

10 MΩ

V

P

10 kΩ

gain
control

signal

22 nF

input

75 Ω

10 MΩ

V

P

10 kΩ

contrast
control

VP = 8 V

VOLTAGE

1

CONVERTER

2

3

4

5

6

CLAMP

CLIPPING

VOLTAGE

CONVERTER

CLAMP

CLIPPING

REF

GAIN

VOLTAGE

CONVERTER

CHANNEL 1

CHANNEL 2

TDA4882

20

19

18

17

16

15

6.2 V

current
output

voltage
output

33 Ω 33 Ω

feedback

current
output

voltage
output

33 Ω 33 Ω

feedback

BFQ235

BFQ235

1.5 kΩ

68 kΩ

6.8 kΩ

1.5 kΩ

BFQ236

1 kΩ

BFQ256

10 Ω

15 kΩ

10 Ω

BAV21

V

= 90 V

CRT

220 Ω

8 V

10 kΩ

cut-off
control

V

= 90 V

CRT

BAV21

220 Ω

68 kΩ

15 kΩ

6.8 kΩ

40 MHz

8 V

10 kΩ
cut-off

control

25 MHz

CRT

60 MHz

P

22 nF

10 MΩ

7

8

9

10

input
clamping

blanking

+

CLAMP

CLIPPING

VOLTAGE

CONVERTER

PULSE

DECODER

CHANNEL 3

test mode
ultra black

output clamping

5.8 V

V

signal
input

75 Ω

horizontal blanking
switch off

clamping pulse
vertical blanking
test mode

Fig.1 Block diagram and basic application circuits for DC and AC coupling.

1997 Sep 04 4

14

13

12

11

current
output

voltage
output

18 Ω

feedback

10 kΩ

V

18 Ω

P

gain
control

BFQ235

860 Ω

10 Ω

1 kΩ

10 Ω

BFQ256

10 kΩ

horizontal blanking

BFQ236

47 nF

V

= 65 V

CRT

BAV21

100 Ω

V

93
kΩ

CRT

10 kΩ

cut-off
control

MED910

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

6 PINNING

SYMBOL PIN DESCRIPTION

BC 1 brightness control
VIN1 2 signal input channel 1
GC1 3 gain control channel 1
GND 4 ground
VIN2 5 signal input channel 2
CC 6 contrast control, OSD switch
V

P

7 supply voltage
VIN3 8 signal input channel 3
HBL 9 horizontal blanking, switch-off
CL 10 input clamping, vertical blanking,

test mode
GC3 11 gain control channel 3
FB3 12 feedback channel 3
VOUT3 13 voltage output channel 3
IOUT3 14 current output channel 3
FB2 15 feedback channel 2
VOUT2 16 voltage output channel 2
IOUT2 17 current output channel 2
FB1 18 feedback channel 1
VOUT1 19 voltage output channel 1
IOUT1 20 current output channel 1

handbook, halfpage

BC

VIN1

GC1
GND
VIN2

CC
V

VIN3

HBL

CL

1
2

3
4
5

TDA4882

6
7

P

8
9

10

20
19
18
17
16
15
14
13
12
11

MHA815

Fig.2 Pin configuration.

IOUT1
VOUT1
FB1
IOUT2
VOUT2
FB2
IOUT3
VOUT3
FB3
GC3

7 FUNCTIONAL DESCRIPTION

7.1 General

Figure 4 illustrates the signal processing. The RGB input
signals 0.7 V (p-p) are capacitively coupled into the
TDA4882 from a low ohmic source and are clamped to an
internal DC voltage (artificial black level). Composite
signals will not disturb normal operations because an
internal clipping circuit cuts all signal parts below black
level. Channels 1 and 3 have a maximum total voltage
gain of 7 dB (maximum contrast and maximum individual
channel gain), channel 2 having 4.4 dB (maximum
contrast and nominal gain). With the nominal channel gain
of 1 dB and nominal contrast setting the nominal
black-to-white output signal is 0.79 V (p-p). Brightness,
contrast and gain control is by DC voltage.

7.2 Brightness control

Brightness control (Fig.4) yields a simultaneous signal
black-level shift of the three channels relative to a
reference black level.

1997 Sep 04 5

For nominal brightness (pin 1 open-circuit) the signal black
level is equal to the reference black level.

7.3 Contrast control

Contrast is voltage controlled to affect the three channels
simultaneously (Fig.4). To provide the correct white point,
individual gain controls adjust the signals of channels 1
and 3 relative to the reference channel 2. Gain setting also
changes contrast to achieve correct grey scale tracking.

7.4 Output stages

The output stages provide both voltage and current
outputs. External cascode transistors reduce power
consumption of the IC and prevent breakdown of the
output transistors. Signal output currents and peaking
characteristics are determined by external components at
the voltage outputs and the video supply. The channels
have separate internal feedback loops which ensure large
signal linearity and marginal signal distortion irrespective
of output transistor thermal V

variation (Fig.8).

BE

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

7.5 Input clamping

The clamping pulse (Fig.17) is for input clamping only.
The input signals are at black level during the clamping
pulse and are clamped to an internal artificial black level.
The coupling capacitors provide black-level storage.
The threshold for the clamping pulse is higher than that for
vertical blanking, therefore, the rise and fall times of the
clamping pulse need to be faster than 75 ns/V during
transition from 1 to 3.5 V.

7.6 Vertical blanking

The vertical blanking pulse (Fig.17) will be detected if the
input voltage is higher than the threshold voltage for
approximately 320 ns but does not exceed the threshold
for the clamping pulse in the time between. During the
vertical blanking pulse the input clamping is disabled to
avoid misclamping in the event of composite input signals.
The input signal is blanked and the artificial black level is
inserted instead. Also the brightness is set internally to its
nominal value, thus the output signal is at reference black
level. The DC value of the reference black level will be
adjusted by cut-off stabilization.

7.7 Horizontal blanking

During horizontal blanking (Fig.18) the output signal is set
to reference black level and output clamping is activated.
If the voltage exceeds the switch-off threshold, the signal
is blanked and switched to ultra-black level for screen
protection and spot suppression during V-flyback.

Ultra-black level is the lowest possible channel output
voltage and is not dependent on cut-off stabilization.

7.8 Cut-off and black-level stabilization

For cut-off stabilization (DC coupling to the CRT) and
black-level stabilization (AC coupling) the video signal at
the cathode or the coupling capacitor is divided by an
adjustable voltage divider and fed to the channel feedback
inputs. During horizontal blanking time this signal is
compared with an internal DC voltage of approximately

5.8 V. Any difference will lead to a reference black-level
correction by charging or discharging the integrated
capacitor which stores the reference black-level
information between the horizontal blanking pulses.

7.9 On Screen Display

For OSD (Fig.3), fast switching of control pin 6 to less than
1 V (e.g. 0.7 V) blanks the input signals. The OSD signals
can easily be inserted to the external cascode transistor.

7.10 Test mode

During test mode (pins 9 and 10 connected to V

) the

P

black levels at the channel voltage outputs are set
internally to typical 0.7 V with nominal brightness and
3 V DC at channel signal inputs.

handbook, full pagewidth

OSD

fast blanking

1 kΩ

4.7 kΩ

100 pF

contrast

PH2222

TDA4882

6

20

17

14

Fig.3 OSD application.

1997 Sep 04 6

channel 1

channel 2

current

output

BFQ235

PH2222

150 Ω

channel 3

220 Ω

depending on
channel gain
1 kΩ to 10 kΩ

OSD
signal input

MHA816

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

I

o(av)

I

OM

P
T
T
T
V

ext

tot
stg
amb
j
ESD

external DC voltage applied to the following pins:

pin 7 (V
pins 2, 5 and 8 (signal inputs) −0.1 V
pins 20, 17 and 14 (current outputs) −0.1 V

) 0 8.8 V

P

P
P

V

V
pins 12, 15 and 18 (channel feedback inputs) −0.1 +0.7 V
pins 1, 6, 3 and 11 (brightness, contrast and gain control inputs) −0.1 V
pin 9 (horizontal blanking input) −0.1 V
pin 10 (input clamping input) −0.1 V

P

+ 0.7 V

P

+ 0.7 V

P

V

average output current (pins 20, 17 and 14); note 1 0 50 mA
peak output current (pins 20, 17 and 14) 0 100 mA
total power dissipation − 1200 mW
storage temperature −25 +150 °C
operating ambient temperature −20 +70 °C
junction temperature −25 +150 °C
electrostatic handling for all pins; note 2 −500 +500 V

Notes

1. Signal amplitude of 50 mA black-to-white is possible if the average current (including blanking times and signal
variation against time) does not exceed 50 mA. The maximum power dissipation of 1200 mW has to be considered.

2. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

9 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 65 K/W

1997 Sep 04 7

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

10 CHARACTERISTICS

V

= 8.0 V; T

P

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

P

I

P

Video signal inputs (channels 1, 2 and 3)

V

i(b-w)

V

I(clamp)

I

I

Brightness control; note 2; Fig.5
V

i(BC)

R

i(BC)

V

i(BC)(nom)

∆V

bl

∆V

BT

=25°C; all voltages measured to GND (pin 4); note 1; see Fig.4; unless otherwise specified.

amb

supply voltage 7.2 8.0 8.8 V
supply current 36 48 60 mA

input voltage, black-to-white − 0.7 1.0 V
DC voltage during input clamping

2.8 3.1 3.4 V

(artificial black + VBE)
DC input current no clamping; Vi=V

T

= −20 to +70 °C

amb

during clamping;
V

i=VI(clamp)

+ 0.7 V

during clamping;
V

i=VI(clamp)

− 0.7 V

I(clamp)

;

−0.05 +0.05 +0.250µA

50 75 120 µA

−120 −75 −50 µA

input voltage 1.0 − 6.0 V
input resistance 40 50 60 kΩ
input voltage for nominal brightness pin 1 open-circuit 2.0 2.25 2.5 V
black-level voltage change at

voltage outputs referred to
reference black level during output
clamping (V

> 1.6 V) related

i(HBL)

V

= 1.0 V −13 −11 −9.5 %

i(BC)

V

=6.0V 303437%

i(BC)

pin 1 open-circuit −−0.8 %

to output signal amplitude with
nominal 0.7 V (p-p) input signal and
nominal contrast (V

i(CC)

= 4.3 V) for

any gain setting
difference of ∆Vbl between any two

−1.2 0 +1.2 %

channels
Contrast control; note 3; Fig.6
V

i(CC)

V

i(CC)(max)

V

i(CC)(nom)

I

i(CC)

C/C

nom

input voltage 1.0 − 6.0 V

maximum input voltage −−V

input voltage for nominal contrast note 4 − 4.3 − V

input current V

contrast relative to nominal contrast V

i(CC)
i(CC)

pins 3 and 11 open-circuit
V

i(CC)

pins 3 and 11 open-circuit

V

i(CC)(min)

∆G

track

input voltage for minimum contrast pins 3 and 11 open-circuit − 0.7 − V

tracking of output signals of

1V<V

channels 1, 2 and 3
t

df(C)

delay between leading (falling)

edges of contrast voltage and

voltage output waveforms

V

i(CC)

input fall time at pin 6:
t

f(CC)

1997 Sep 04 8

−1V

P

= 4.3 V −5 −1 −0.1 µA
= 6.0 V;

= 1.0 V;

< 6 V; note 5 − 0 0.5 dB

i(CC)

= 4.3 V to 0.7 V;

2.4 3.4 − dB

−26 −22 −19 dB

− 720ns

= 2 ns; note 6; Fig.10

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

dr(C)

t

f(C)

t

r(C)

Gain control (channel 1 and channel 3); note 7; Fig.7
V

i(GC)

V

i(GC)(nom)

R

i(GC)

∆G gain control difference relative to

delay between trailing edges

(rising) of contrast voltage and

voltage output waveforms

fall time of voltage output waveform 90% to 10% amplitude; input

V

= 0.7 V to 4.3 V;

i(CC)

input rise time at pin 6:
t

= 2 ns; note 6; Fig.10

r(CC)

fall time at pin 6: t

f(CC

− 15 25 ns

− 615ns

) = 2 ns;

note 6; Fig.10

rise time of voltage output

waveform

10% to 90% amplitude; input
rise time at pin 6:
t

= 2 ns; note 6; Fig.10

r(CC)

− 615ns

input voltage 1.0 − 6.0 V

input voltage for nominal gain pins 3 and 11 open-circuit 3.6 3.75 3.95 V

input resistance 44 55 66 kΩ

V
nominal gain
(channels 1 and 3 only)

V

i(CC)
i(CC)

= 4.3 V; V
= 4.3 V; V

= 6 V 2 2.6 3.3 dB

i(GC)

=1V −5.5 −5 −4.5 dB

i(GC)

Feedback input (channels 1, 2 and 3); note 8; Fig.8
V

ref(int)

I

o(FB)(max)

∆V

bl(CRT)

∆V

ref(T)

internal reference voltage 5.6 5.8 6.1 V
maximum output current during output clamping;

V

=3V

i(FB)

−500 −100 −60 nA

black-level variation at CRT note 9 0 40 200 mV
variation of V

ref(int)

in the

T

= −20 to +70 °C 0 20 50 mV

amb

temperature range

∆V

ref(int)(VP)

variation of V

with supply

ref(int)

7.2 V ≤ VP≤ 8.8 V 0 60 100 mV

voltage

Voltage outputs (channels 1, 2 and 3)

V

o(b-w)(nom)

V

blx(max)

V

bl(SO)

nominal signal output voltage
(black-to-white value)

maximum adjustable black-level
voltage

black-level voltage during
switch-off, equal to minimum

pins 3 and 11 open-circuit;

V

i(CC)

= 4.3 V; V

i(b-w)

= 0.7 V

during output clamping;

T

= −20 to +70 °C

amb

V

i(HBL)=VP

T

amb

; RO=33Ω;

= −20 to +70 °C

0.69 0.79 0.89 V

1 1.2 1.4 V

30 45 100 mV

adjustable black-level voltage

V

bl(TST)

black-level voltage during test
mode

V

i(HBL)=VP

; V

i(CL)=VP

open-circuit; Vi=V

I(clamp)

; pin 1

;

0.3 0.7 1.2 V

note 10

S/N signal-to-noise ratio note 11 − 50 44 dB
d
∆V

O(th)

bl(fl)

output thermal distortion I
black-level variation between

= 50 mA; note 12 − 0.6 1 %

o(b-w)

line frequency 30 kHz − 0.5 4.5 mV
clamping pulses

V

offset(max)

maximum offset during sync
clipping

VI<V

I(clamp)

note 13; Fig.9

;

0715mV

1997 Sep 04 9

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆V

o(b-w)(T)

Current outputs (channels 1, 2 and 3); note 14
I

o(b-w)

V

; V

20-19

V

14-13

I

bl(SO)

Frequency response at voltage outputs; note 15; Figs 11, 12 and 13
∆G

(f)

t

r(O)

dV

O

Crosstalk at voltage outputs with speed up circuit; note 16; Figs 14, 15 and 16

α

ct(tr)

Threshold voltages for clamping, blanking and switch-off; note 17
V

i(HBL)

R

i(HBL)

t

d(Hblank)

V

i(CL)

I

i(CL)

variation of nominal output signal
(black-to-white value) with
temperature

output current
(black-to-white value)

;

start of HF-saturation voltage of

17-16

output transistors
output current during switch-off V

gain decrease by frequency

pins 3 and 11 open-circuit;

V

= 4.3 V; V

i(CC)

T

= −20 to +70 °C

amb

i(b-w)

= 0.7 V;

0 2.5 10 %

− 50 − mA
with peaking −−100 mA
Io=50mA −−2.0 V

= 100 mA −−2.2 V

I

o

i(HBL)=VP

; RO=33Ω 0 20 900 µA

70 MHz; single channel − 1.3 3 dB

response
rise time at voltage output 10% to 90% amplitude; input

− 4.1 5.0 ns
rise time = 1 ns

overshoot of output signal pulse
related to actual output pulse
amplitude

single channel;
input rise time = 2.5 ns;
V

= 0.7 V;

i(b-w)

− 48%

pins 3 and 11 open-circuit;
V

= 4.3 V

i(CC)

transient crosstalk −−−20 dB

threshold for horizontal blanking

1.2 1.4 1.6 V

(blanking, output clamping)
threshold for switch-off (blanking,

5.8 6.5 6.8 V

minimum black-level, no output
clamping)

input resistance against ground 50 80 110 kΩ
delay between horizontal blanking

input and output signal blanking

input rise time at
pin 9 > 100 ns;

− 40 60 ns

note 18; Fig.18

threshold for vertical blanking

note 19; Fig.17 1.2 1.4 1.6 V

(blanking, no input clamping)
threshold for clamping

note 19; Fig.17 2.6 3.0 3.5 V

(input clamping, no blanking)
threshold for test mode

(no clamping, no blanking, see
V

bl(TST)

above)

current V

for test mode also
V

> 6.8 V (switch-off)

i(HBL)

i(CL)<VP

V

i(CL)

−1V −3 −1 −µA

≥ VP− 1V − 100 −µA

VP− 1 − V

V

P

1997 Sep 04 10

Philips Semiconductors Product specification









Advanced monitor video controller for OSD TDA4882

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

, t

r(CL)

f(CL)

t

w(clamp)

t

d(Vblank)

Notes to the characteristics

1. Definition of levels:
a) Artificial black level: internal signal level behind input emitter follower during input clamping and signal clipping.

This level is inserted instead of the input signal during blanking.

b) Reference black level: DC voltage during output clamping at voltage outputs, not influenced by brightness,

contrast or gain setting, adjustable by cut-off stabilization.
c) Cut-off level: corresponding DC voltage at CRT cathode in closed feedback loop.
d) Black level: actual signal black level at either the voltage outputs or cathode, it can be adjusted by

(brightness × gain), it refers to reference black level or cut-off level.
e) Ultra-black level, switch-off level: lowest adjustable reference black level, lowest signal level at voltage outputs.
f) The minimum guaranteed control range for reference black level is 0.1 to 1 V. The ultra-black level is dependent

on the external resistor RO at pins 13, 16 and 19 (voltage outputs) to ground.

rise and fall time for clamping pulse note 19; Fig.17 −−75 ns/V
width of clamping pulse 0.6 −−µs
delay between vertical blanking

note 19; Fig.17 260 320 380 ns

input and internal blanking

R

V

g)

bl(SO)

2. Linear control range is 1 to 6 V for V

3. Linear control range is 1 to 6 V for V
setting. It is recommended not to exceed V
V

i(CC)<Vi(CC)(min)

o

-------------------------------

3.5 kΩ Ro+

4.65 V×≈

, independent of supply voltage.

i(BC)

, independent of supply voltage. Open pin 6 leads to maximum contrast

i(CC)

i(CC)=VP

−1 V to avoid saturation of internal circuitry. For

≈ 0.7 V a small negative signal (≈−40 dB) will appear. For frequency dependency of contrast

control see note 15.

4. Definition for nominal output signals: input V
V

i(CC)=Vi(CC)(nom)

5. dB

∆G

track

.

A

A

1



20 maximum of

×=



log



×

-------- -

-------- -

A



10

= 0.7 V, gain pins 3 and 11 open-circuit, contrast control

i(b-w)

A

20

A

2

A

1



log

-------- ­A



30

×

-------- ­A

10

3



log;;



A

-------- ­A

A

2

30

×

-------- ­A

20

3

Ax: signal output amplitude in channel x at any contrast setting between 1 and 6 V.
A

: signal output amplitude in channel x at nominal contrast and same gain setting.

x0

6. Typical step in contrast voltage and response at signal outputs for nominal input signal V

i(b-w)

= 0.7 V

(OSD fast blanking input/output).

7. Linear control range is 1 to 6 V for V

, independent of supply voltage.

i(GC)

8. The internal reference voltage can be measured at pins 18, 15 and 12 (channel feedback inputs) during output
clamping (V

9. Slow variations of video supply voltage V
Change of V

= 2 V) in closed feedback loop.

i(HBL)

(Fig.1) will be suppressed at CRT cathode by cut-off stabilization.

CRT

by 5 V leads to specified change of cut-off voltage.

CRT

10. The test mode allows testing without input and output clamping pulses. The signal inputs have to be biased via
resistors to the previously measured clamp voltages of approximately 3 V (artificial black level + VBE). Signal and
brightness blanking is not possible during test mode. The current outputs should be adjusted by resistors >> R0 from
voltage outputs to a positive voltage (e.g. VP).

1997 Sep 04 11

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

11. The signal-to-noise ratio is calculated by the formula (frequency range 1 to 70 MHz):

S

20

--- ­N

12. Large output swing e.g. I
Thermal VBE variation is compensated.

13. Composite signals will not disturb normal operation because an internal clipping circuit cuts all signal parts below
black level.

peak-to-peak value of the nominal signal output voltage

---------------------------------------------------------------------------------------------------------------------------------------------------log×=
RMS value of the noise output voltage

= 50 mA leads to signal-dependent power dissipation in output transistors.

o(b-w)

dB

14. The output current approximately follows the equation for V
R

= external resistor at voltage output to ground. The external RC combination (Fig.1) at pins 19, 16 and 13

O

I

o

------- -

o



R

1



V

O

+

----------------- -

2.2 kΩ

1

500 µA–=

o>Vbl(SO)

and with

(voltage outputs) enables peak currents during transients.

15. Frequency response, crosstalk and pulse response have been measured at voltage outputs on a special
printed-circuit board with 50 Ω line in/out connections and without peaking, see Chapter 11.

16. Crosstalk between any two voltage outputs (e.g. channels 1 and 2).
a) Input conditions: one channel (channel 1) with nominal input signal and minimum rise time. The inputs of the

other channels capacitively coupled to ground (channels 2 and 3). Gain pins 3 and 11 open-circuit.

b) Output conditions: output signal of channel 1 is set by contrast control voltage, to V

the rise time should be 5 ns. Output signal of channel 2 then is V

V

c) Transient crosstalk:dB

α

ct(tr)

20

o(VOUT2)

------------------------log×=
V

o(VOUT1)

o(b-w)=Vo(VOUT2)

.

o(b-w)=Vo(VOUT1)

= 0.7 V,

d) Crosstalk as a function of frequency has been measured without peaking circuit, with nominal input signal and

nominal settings.

17. The internal threshold voltages are derived from a stabilized voltage. The internal pulses are generated while the
input pulses are higher than the thresholds. Voltages less than −0.1 V at pins 9 and 10 can influence black-level
control and should be avoided.

18. The delay between HBL input pulse (horizontal blanking) and output signal blanking pulse and also brightness
blanking (∆Vbl), at the voltage outputs, depends on the input rise time of the HBL pulse. The specified values for
t

19. For 75 ns/V < t

are valid for HBL rise times greater than 100 ns only.

d(Hblank)

r(CL),tf(CL)

< 240 ns/V, generation of internal input clamping and blanking pulse is not defined. Pulses

not exceeding the threshold of input clamping (typical 3 V) will be detected as blanking pulses.

1997 Sep 04 12

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

input signals

input signal at
pins 2, 5 and 8
with sync (on green)

input clamping pulse
at pin 10

horizontal blanking and
output clamping pulse
at pin 9

internal signal
behind input stage

output signals
(pins 19, 16 and 13)

at nominal gain and
contrast setting
and
maximum/nominal/
minimum brightness setting

at nominal gain and
maximum brightness setting
and
maximum/nominal/
minimum contrast setting

sync clipping to

artificial black level

video portion

video signal

horizontal flyback and output clamping

inserted artificial black level

max.

nom.

min.

brightness is set to nominal value during horizontal blanking

max.

nom.

min.

max.

black level equal to
artificial black level + V
by input clamping (approximately 3 V)

black level equal to artificial
black level by input clamping and
storage by coupling capacitor

∆ black level
due to brightness setting

reference black level

∆ black level for
maximum brightness

reference black level

BE

at nominal contrast and
maximum brightness setting
and
maximum/nominal/
minimum gain setting

signal at CRT cathode

at nominal gain and
contrast setting
and
maximum brightness setting

Fig.4 Signal processing.

1997 Sep 04 13

nom.

min.

grey scale

reference black level
ultra black level

ground

high tension supply
voltage (e.g. 90 V)

(raster) cut-off level

black level

grey scale

MHA817

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

50

handbook, halfpage

40

∆V

bl

(%)

30

20

10

0

−10

−20

−30

02

2.24

48

Fig.5 Typical brightness characteristic.

MHA818

400

(mV)

300

200

100

0

−100

−200

6

V

i (BC)

1400

handbook, halfpage

signal

amplitude

(mV)

1000

800

600

400

200

0

−200
024

0.7

4.3

MHA819

4

(dB)

3
2

1
0

−1

−3

−5

−10

−20

−40

(V)

8

6

V

i(CC)

Fig.6 Typical contrast characteristic.

V

i(GC)

MHA821

(V)

3

(dB)

2
1

0

−1

−2

−3

−4

−5

−6

−8

86

1200

handbook, halfpage

signal

amplitude

(mV)

800

400

0

0

24

3.75

Fig.7 Typical gain characteristic.

1997 Sep 04 14

5.85

handbook, halfpage

5.84

V

ref(int)

5.83

(V)

5.82

5.81

5.80

5.79

5.78

5.77

5.76

5.75

−20 0 80

Conditions: 0.5 V reference black level, no signal.

Fig.8 Typical variation of V

VP = 8.8 V

8.0 V

7.2 V

4020 10060

ref(int)

and supply voltage.

MHA822

T

(°C)

amb

with temperature

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

input

signal

handbook, full pagewidth

OSD pulse

at pin 6

(V)

4.3

0.7

output signal

at pins 19, 16 and 13

(V)

output

signal

Fig.9 Typical sync clipping.

t

f(CC)

t

df(C)

t

r(CC)

t

dr(C)

V

MHA823

90%
50%
10%

t

offset(max)

Vbl + V

o(b-w)

Vbl = 0.7

= 1.5

V

o(b-w)

t

f(C)

Fig.10 Typical OSD fast blanking input/output waveforms.

1997 Sep 04 15

t

r(C)

90%
50%
10%

t

MHA820

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

input pulse

(mV)

output pulse

(mV)

800

600

400

200

1000

800

600

400

0

tr ≈ 2.5 ns

MHA825

90%

tf ≈ 2.5 ns

10%

90%

Solid line: single channel.
Dotted line: white pattern.

Fig.11 Typical pulse response: VIN1, VIN2 and VIN3 → VOUT1, VOUT2 and VOUT3.

200

−200

tr ≈ 4.4 ns

10%

0

0

20 40 60 80 100

tf ≈ 4.8 ns

t (ns)

1997 Sep 04 16

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

3

signal

(dB)

0

−3

−6

−9

−12

−15

11010

Solid line: single channel.
Dotted line: white signal.

Fig.12 Typical frequency response.

2

f (MHz)

MHA824

3

10

10

handbook, full pagewidth

V

signal

(dB)

Solid line: single channel.
Dotted line: white signal.

i(cc)

0

−10

−20

−30

110

=

7 V
6 V

5 V
4 V

3 V

2 V

V

= 0.7 V

i(cc)

1 V

V

= 0.7 V

i(cc)

2

10

70 120

Fig.13 Typical characteristic of contrast control as a function of frequency.

f (MHz)

MHA826

3

10

1997 Sep 04 17

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

0

signal

(dB)

−10

−20

−30

−40

11010

(1) Solid line: channel 1.

Dashed line: channel 2.
Dotted line: channel 3.

channel

1

2

3

2

Fig.14 Typical crosstalk: channel 1 → 2 and 3.

MHA827

(1)

3

f (MHz)

10

handbook, full pagewidth

0

signal

(dB)

−10

−20

−30

−40

11010

(1) Solid line: channel 1.

Dashed line: channel 2.
Dotted line: channel 3.

channel

2

3

1

2

Fig.15 Typical crosstalk: channel 2 → 1 and 3.

MHA828

(1)

3

f (MHz)

10

1997 Sep 04 18

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

0

signal

(dB)

−10

−20

−30

−40

11010

(1) Solid line: channel 1.

Dashed line: channel 2.
Dotted line: channel 3.

channel

3

1

2

2

Fig.16 Typical crosstalk: channel 3 → 1 and 2.

MHA829

(1)

3

f (MHz)

10

handbook, full pagewidth

3 V

V

i(CL)

1.4 V

internal pulses

input

clamping

blanking

t

r(CL)

t

f(CL)

no

clamping

t

d(Vblank)

Fig.17 Timing of pulses at CL (pin 10).

1997 Sep 04 19

≈ 1/2 t

d(Vblank)

no

clamping

MHA831

t

t

t

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

t

d

(ns)

80

70

60

50

40

30

20

20 40 60 80 100 120 140

(1) Black level: 0.74 V.
(2) Reference black level: 0.5 V.
(3) Rise and fall times for HBL between 0.2 and 1.45 V.
(4) td is the delay at the end of brightness blanking.

t

d(Hblank)

t

HBL pulse

(V)

1.45

0.2

t

r

t

∆V

bl

d(Hblank)

50%

of ∆V

bl

output

signal

(V)

(1)

0.74

(4)

d

(2)

0.5

(3)

(ns)

tr,t

f

t

d

t

(4)

t

MHA830

Fig.18 Typical delay between HBL pulse and brightness blanking at voltage outputs.

1997 Sep 04 20

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

11 APPLICATION AND TEST INFORMATION

For high frequency measurements and special application,
a printed-circuit board with only a few external
components is built. Figure 19 shows the application
circuit and Fig.20 the layout of the double sided printed
board. All components on the underside and R13, R14
and R15 on the top are SMD types. Short HF loops and
minimum crosstalk between the channels as well as input
and output are achieved by properly shaped ground areas
star connected to the IC ground pin.

The HF input signal can be fed to the subclick connectors
P1, P2 and P3 by a 50 Ω line. The line is then terminated
by a 51 Ω resistor on the board. With choice of jumper
connections (J1, J2 and J3) it is possible to connect
channel inputs to its input connector, to connect all
channels to one input connector (white pattern) and to
ground each input via the coupling capacitor.

For operation without input clamping, e.g. test mode, the
DC bias can be provided by VIDC (connector P21) if a
short-circuit at J4, J5 and J6 is made (solder short or
low-value SMD resistor).

The output signal can be monitored via 50 Ω terminated
lines at the voltage outputs (subclick connectors
P4, P5 and P6). With 100 Ω in parallel to the 50 Ω
terminated line the effective load resistance at the voltage
outputs is 33 Ω. The mismatch seen from the line towards
the IC has no significant effect if the line is match
terminated. A peaking circuit, C15, R16 for channel 1
(C16, R17 for channel 2 and C17, R18 for channel 3), can
be added for realistic loading of the voltage outputs.

DC control for brightness, contrast and gain is provided at
connectors P21 and P22. Contrast control can also be set
by the potentiometer R28 (jumper J11). The series
resistor R11 is necessary if fast OSD switching is activated
via 50 Ω line (P10), a line termination can be provided at
the connector P9. Clamping and blanking pulses are fed to
the IC via connectors P7 and P8. Connector P23 is used
for power supply. The capacitors C7 and C8 should be
located as near as possible to the IC pins.

11.1 Recommendations for building the application board

• General

– Double-sided board
– Short HF loops by large ground plane on the rear.

• Voltage outputs

– Capacitive loads as small as possible
– Short interconnection via resistor to ground.

• Supply voltage

– Capacitors as near as possible to the pins
– Use of high-frequency capacitors (low self

inductance, e.g. SMD).

• Resonance suppression. The external interconnection

inductance to the current outputs can build a resonance
together with the internal substrate capacitance.
A damping resistor of 10 to 30 Ω near to the IC pin can
suppress such oscillations.

Black-level adjustment is made by VIOS, VFBX (external
voltages at connector P21) and resistors R19, R22
and R25 for channel 1 (channel 2: R20, R23 and R26;
channel 3: R21, R24 and R27). If R19 is equal to the
effective load resistor at the voltage output the reference
black level (V

V

V

ref(int)

ref(bl)

VIOS V

is the internal reference voltage at the feedback

) is approximately:

ref(bl)

– V

ref(int)

ref(int)

VFBX–()–

×=

R22

----------­R25

input (typical 5.8 V). By this it is possible to adjust the
reference black level and the voltage at the current outputs
independently.

1997 Sep 04 21

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

subclick connector (50 Ω)

solder point for short-circuiting
or SMD 0 Ω resistor

jumper
connector

V

i(b-w)

P1

V

i(b-w)

P2

BC/GC2 GC1 V

P21

C4
100 nF

C5
22 nF

C1

J1

22 nF

R1

51

Ω

J2

22 nF

R2

51

Ω

J4

R4

5.1 kΩ

C12
22
nF

C2

J5

R5

5.1 kΩ

C13
22 nF

(sense)

BC/GC2

VIN1

GC1

C6
22 nF

GND

VIN2

CC

GND

R7

110 Ω

1

2

3

4

5

6

IDC

IC1

TDA4882

VFBX VIOS

20

19

18

17

16

15

IOUT1

VOUT1

C15
47 pF

FB1

IOUT2

VOUT2

C16
47 pF

FB2

R16
33 Ω

R17
33 Ω

C30
220 µF
(25 V)

(multi-layer)

R13
100

Ω

R14
100

Ω

C29

2.2 µF

R19

33 Ω

P4

R22
3 kΩ

R25

9.1 kΩ

R20

33 Ω

P5

R23

3 kΩ

R26

9.1 kΩ

100 nF

C22
22 nF

C21
22
nF

C18
22 nF

C19
22 nF

22 nF

C24
100

nF

C25
100 nF

C27

C28

V

HBL

P3

P7

V

i(b-w)

R8
1 kΩR91 kΩ

P8

CL

R3
51 Ω

J3

22 nF

P23

GND

(power)

P

C8
100

1 nF

nF

C3

J6

R6

5.1
kΩ

C14
22
nF

L1
100 µH

P9

V

P

7

C7

VIN3

8

HBL

9

CL

10

C31
R10
1 kΩ

OSD

10 µFC9100 nF

P10

14

13

12

11

Fig.19 Application circuit for test PCB.

1997 Sep 04 22

IOUT3

VOUT3

C17
47 pF

FB3

GC3

R11
1 kΩ

C11
22 nF

R18
33 Ω

J10

R15
100

Ω

J11

R21

C23
22 nF

C20
22 nF

C26
100 nF

P22

GC3

CC

VP (sense)

GND (sense)

MHA832

33 Ω

P6

R24
3 kΩ

R27

9.1 kΩ

C10
100 nF

R28

10 kΩ

R12

1 kΩ

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

handbook, full pagewidth

C30

P4

R7

P21

J1 J2 J3

P1

R1 R2 R3

C29

P5

R14R13

IC1

P2 P3

R15

P6

P22

C31

J11
J10

L1

R8

R28

P10

P9

P23

P8

P7

R5R4

C2C1

C13

J5

C4

C6C5 C8 C7

R23R22

C16C15

R17

C25

C19

C27C28

R24

R21R26R20R25

C23C22

C26

R19

C21

C24

C12

J4

R16

C18

Fig.20 Double sided test PCB layout.

1997 Sep 04 23

R6C14

C3

J6

C17

R18

C20

C11

R9

C9

R10

R27

R11

R12

C10

MHA833

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

12 INTERNAL PIN CONFIGURATION

handbook, full pagewidth

20 19 17 1618 14 1315 1112

pin pin

CL CL CL

TDA4882

CLCL CL

+

65834 721

+

9

MED911

10

diode protection
on all pins except
pins 4 and 7

zener diode protection
at pin 7

Fig.21 Internal pin configuration.

1997 Sep 04 24

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

13 PACKAGE OUTLINE

DIP20: plastic dual in-line package; 20 leads (300 mil)

D

seating plane

L

Z

20

pin 1 index

e

b

SOT146-1

M

E

A

2

A

A

1

w M

b

1

11

E

c

(e )

1

M

H

1

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE
VERSION

SOT146-1

1 2

min.

max.

1.73

1.30

0.068

0.051

IEC JEDEC EIAJ

b

b

1

0.53

0.38

0.021

0.015

0.014

0.009

REFERENCES

cD E e M

0.36

0.23

(1) (1)

26.92

26.54

1.060

1.045

SC603

1997 Sep 04 25

6.40

6.22

0.25

0.24

10

(1)

M

e

L

1

3.60

8.25

3.05

7.80

0.14

0.32

0.12

0.31

EUROPEAN

PROJECTION

H

E

10.0

0.2542.54 7.62

8.3

0.39

0.010.10 0.30

0.33

ISSUE DATE

w

92-11-17
95-05-24

Z

max.

2.04.2 0.51 3.2

0.0780.17 0.020 0.13

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

14 SOLDERING

14.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

14.2 Soldering by dipping or by wave

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

15 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

(order code 9398 652 90011).

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

14.3 Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

stg max

). If the

16 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1997 Sep 04 26

Philips Semiconductors Product specification

Advanced monitor video controller for OSD TDA4882

NOTES

1997 Sep 04 27

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 547047/1200/02/pp28 Date of release: 1997 Sep 04 Document order number: 9397 750 02268