Datasheet TDA4856-V2 Datasheet (Philips)

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Page 1

DATA SH EET

Product speciﬁcation Supersedes data of 1998 Oct 02 File under Integrated Circuits, IC02

1999 Jul 13

INTEGRATED CIRCUITS

TDA4856

C-bus autosync deflection

controller for PC monitors

Page 2

1999 Jul 13 2

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

FEATURES Concept features

• Full horizontal plus vertical autosync capability

• Extended horizontal frequency range from

15 to 130 kHz

• Comprehensive set of I2C-bus driven geometry adjustments and functions, including standby mode

• Very good vertical linearity

• Moire cancellation

• Start-up and switch-off sequence for safe operation of

all power components

• X-ray protection

• Power dip recognition

• Flexible switched mode B+ supply function block for

feedback and feed forward converter

• Internally stabilized voltage reference

• Drive signal for focus amplifiers with combined

horizontal and vertical parabola waveforms

• DC controllable inputs for Extremely High Tension (EHT) compensation

• SDIP32 package.

Synchronization

• Can handle all sync signals (horizontal, vertical, composite and sync-on-video)

• Output for video clamping (leading/trailing edge selectable by the I2C-bus), vertical blanking and protection blanking

• Output for fast unlock status of horizontal synchronization and blanking on grid 1 of picture tube.

Horizontal section

• I2C-bus controllable wide range linear picture position, pin unbalance and parallelogram correction via horizontal phase

• Frequency-lockedloopforsmoothcatchingofhorizontal frequency

• Simple frequency preset of f

min

and f

max

by external

resistors

• Low jitter

• Soft start for horizontal and B+ control drive signals.

Vertical section

• I2C-bus controllable vertical picture size, picture position, linearity (S-correction) and linearity balance

• Outputfor the I2C-buscontrollable vertical sawtooth and parabola (for pin unbalance and parallelogram)

• Vertical picture size independent of frequency

• Differential current outputs for DC coupling to vertical

booster

• 50 to 160 Hz vertical autosync range.

East-West (EW) section

• I2C-bus controllable output for horizontal pincushion, horizontal size, corner and trapezium correction

• Optional tracking of EW drive waveform with line frequency selectable by the I2C-bus.

Focus section

• I2C-bus controllable output for horizontal and vertical parabolas

• Verticalparabolaisindependentoffrequencyandtracks with vertical adjustments

• Horizontal parabola independent of frequency

• Adjustable pre-correction of delay in focus output stage.

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1999 Jul 13 3

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

GENERAL DESCRIPTION

The TDA4856 is a high performance and efficient solution for autosync monitors. All functions are controllable by the I2C-bus.

The TDA4856 provides synchronization processing, horizontal and vertical synchronization with full autosync capability and very short settling times after mode changes. External power components are given a great deal of protection. The IC generates the drive waveforms for DC-coupled vertical boosters such as the TDA486x and TDA835x.

The TDA4856 provides extended functions e.g. as a flexible B+ control, an extensive set of geometry control facilities, and a combined output for horizontal and vertical focus signals.

Together with the I2C-bus driven Philips TDA488x video processor family, a very advanced system solution is offered.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

supply voltage 9.2 − 16 V

supply current − 70 − mA

CC(stb)

supply current during standby mode − 9 − mA VSIZE vertical size 60 − 100 % VGA VGA overscan for vertical size − 16.8 − % VPOS vertical position −±11.5 − % VLIN vertical linearity (S-correction) −2 −−46 % VLINBAL vertical linearity balance −±1.25 − % V

HSIZE

horizontal size 0.13 − 3.6 V V

HPIN

horizontal pincushion (EW parabola) 0.04 − 1.42 V V

HEHT

horizontal size modulation 0.02 − 0.69 V V

HTRAP

horizontal trapezium correction −±0.5 − V V

HCORT

horizontal corner correction at top of picture −0.64 − +0.2 V V

HCORB

horizontal corner correction at bottom of picture −0.64 − +0.2 V HPOS horizontal position −±13 − % HPARAL horizontal parallelogram −±1.5 − % HPINBAL EW pin unbalance −±1.5 − % T

amb

operating ambient temperature −20 − +70 °C

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA4856 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1

Page 4

1999 Jul 13 4

Philips Semiconductors Product speciﬁcation

C-bus autosync deﬂection controller for

PC monitors

TDA4856

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BLOCK DIAGRAM

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VERTICAL

SYNC INPUT

AND POLARITY

CORRECTION

VERTICAL

SYNC

INTEGRATOR

VERTICAL

OSCILLATOR

AND AGC

EW OUTPUT

HORIZONTAL PINCUSHION HORIZONTAL CORNER HORIZONTAL TRAPEZIUM HORIZONTAL SIZE

VERTICAL LINEARITY VERTICAL LINEARITY

BALANCE

EHT COMPENSATION

HORIZONTAL AND

VERTICAL SIZE

ASYMMETRIC

EW-CORRECTION

OUTPUT

HORIZONTAL

AND VERTICAL

I2C-BUS

RECEIVER

HUNLOCK

OUTPUT

VERTICAL POSITION VERTICAL SIZE AND

VERTICAL OVERSCAN

VIDEO CLAMPING

AND

VERTICAL BLANK

SUPPLY

AND

REFERENCE

HORIZONTAL OSCILLATOR

PLL1 AND

HORIZONTAL

POSITION

PLL2, PARALLELOGRAM,

PIN UNBALANCE AND

SOFT START

COINCIDENCE DETECTOR

FREQUENCY DETECTOR

I2C-BUS REGISTERS

PROTECTION

AND SOFT START

X-RAY

PROTECTION

HORIZONTAL

OUTPUT

B+

CONTROL

22 kΩ

3.3 kΩ

100 nF

8.2 nF

150

(1%)

10 nF

HBUF

(2%)

HREF

(1%)

(1)

B+ CONTROL APPLICATION

(2)

(TTL level)

9.2 to 16 V

(video)

clamping blanking

23 22 21 31

100

(5%)

VOUT2

VOUT1

ASCOR

32 FOCUS

BDRV BSENS BOP BIN

HDRV

19 18

6 4 3 5

28 29

12 nF

30 1

TDA4856

H/C SYNC INPUT

AND POLARITY

CORRECTION

MGS272

VERTICAL OUTPUT

FOCUS

SDA SCL

HSYNC

SGND

PGND

CLBL

VSYNC

EWDRV

VSMODVAGCVCAPVREF HSMOD

7 V

1.2 V

EHT compensation

via horizontal size

EHT compensation

via vertical size

HFLB

HPLL2HCAPHREFHBUFHPLL1

XSEL XRAY

HUNLOCK

Fig.1 Block diagram and application circuit.

(1) For the calculation of fH range see Section“Calculation of line frequency range”. (2) See Figs 22 and23.

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1999 Jul 13 5

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

PINNING

SYMBOL PIN DESCRIPTION

HFLB 1 horizontal ﬂyback input XRAY 2 X-ray protection input BOP 3 B+ control OTA output BSENS 4 B+ control comparator input BIN 5 B+ control OTA input BDRV 6 B+ control driver output PGND 7 power ground HDRV 8 horizontal driver output XSEL 9 select input for X-ray reset V

10 supply voltage EWDRV 11 EW waveform output VOUT2 12 vertical output 2 (ascending sawtooth) VOUT1 13 vertical output 1 (descending sawtooth) VSYNC 14 vertical synchronization input HSYNC 15 horizontal/composite synchronization input CLBL 16 video clamping pulse/vertical blanking output HUNLOCK 17 horizontal synchronization unlock/protection/vertical blanking output SCL 18 I2C-bus clock input SDA 19 I2C-bus data input/output ASCOR 20 output for asymmetric EW corrections VSMOD 21 input for EHT compensation (via vertical size) VAGC 22 external capacitor for vertical amplitude control VREF 23 external resistor for vertical oscillator VCAP 24 external capacitor for vertical oscillator SGND 25 signal ground HPLL1 26 external ﬁlter for PLL1 HBUF 27 buffered f/v voltage output HREF 28 reference current for horizontal oscillator HCAP 29 external capacitor for horizontal oscillator HPLL2 30 external ﬁlter for PLL2/soft start HSMOD 31 input for EHT compensation (via horizontal size) FOCUS 32 output for horizontal and vertical focus

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1999 Jul 13 6

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction

HSYNC (pin 15) is the input for horizontal synchronization signals, which can be DC-coupled TTL signals (horizontal or composite sync) and AC-coupled negative-going video sync signals. Video syncs are clamped to 1.28 V and sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync.

For DC-coupled TTL signals the input clamping current is limited. The slicing level for TTL signals is 1.4 V.

The separated sync signal (either video or TTL) is integrated on an internalcapacitor to detect and normalize the sync polarity.

Normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the PLL1 phase detector and the frequency-locked loop.

Vertical sync integrator

Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to extract vertical sync pulses. The integration time is dependent on the horizontal oscillator reference current at HREF (pin 28). The integrator output directly triggers the vertical oscillator.

Vertical sync slicer and polarity correction

Vertical sync signals (TTL) applied to VSYNC (pin 14) are sliced at 1.4 V. The output signal of the sync slicer is integrated on an internalcapacitor to detect and normalize the sync polarity. The output signals of vertical sync integrator and sync normalizer are disjuncted before they are fed to the vertical oscillator.

Video clamping/vertical blanking generator

The video clamping/vertical blanking signal at CLBL (pin 16) is a two-level sandcastle pulse which is especially suitableforvideoICs such as the TDA488x family, but also for direct applications in video output stages.

The upper level is the video clamping pulse, which is triggeredbythehorizontalsyncpulse.Either the leading or trailing edge can be selected by setting control bit CLAMP via the I2C-bus. The width of the video clamping pulse is determined by an internal single-shot multivibrator.

The lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from the internal oscillator waveform. It is started by the vertical sync and stopped with the start of the vertical scan. This results in optimum vertical blanking. Two different vertical blanking times are accessible, by control bit VBLK, via the I2C-bus.

Blanking will be activated continuously if one of the following conditions is true:

Soft start of horizontal and B+ drive [voltage at HPLL2 (pin 30) pulled down externally or by the I2C-bus]

PLL1 is unlocked while frequency-locked loop is in search mode

No horizontal flyback pulses at HFLB (pin 1) X-ray protection is activated Supply voltage at VCC (pin 10) is low (see Fig.24).

Horizontal unlock blanking can be switched off, by control bit BLKDIS, via the I2C-bus while vertical blanking is maintained.

Fig.2 Pin configuration.

handbook, halfpage

TDA4856

MGS273

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

HFLB

XRAY

BOP

BSENS

BIN

BDRV PGND HDRV

XSEL

EWDRV

VOUT2 VOUT1 VSYNC

FOCUS HSMOD HPLL2 HCAP

HBUF HPLL1

HREF

SGND VCAP VREF VAGC VSMOD ASCOR SDA

HSYNC

CLBL

SCL HUNLOCK

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1999 Jul 13 7

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Frequency-locked loop

The frequency-locked loop can lock the horizontal oscillatorover a wide frequencyrange. This is achievedby a combined search and PLL operation. The frequency range is preset by two external resistors and the

recommended maximum ratio is

This can, for instance, be a range from 15.625 to 90 kHz with all tolerances included.

Without a horizontal sync signal the oscillator will be free-running at f

min

. Any change of sync conditions is detected by the internal coincidence detector. A deviation of more than 4% between horizontal sync and oscillator frequency switches the horizontal section into search mode.This means that PLL1control currents are switched off immediately. The internal frequency detector then starts tuning the oscillator. Very small DC currents at HPLL1 (pin 26) are used to perform this tuning with a well defined change rate. When coincidence between horizontal sync and oscillator frequency is detected, the search mode is first replaced by a soft-lock mode which lasts for the first part of the next vertical period. The soft-lock mode is then replaced by a normal PLL operation. This operation ensures smooth tuning and avoids fast changes of horizontal frequency during catching.

In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed internally to HBUF (pin 27) via a sample-and-hold and buffer stage. The sample-and-hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. An external resistorconnectedbetweenpins HBUFand HREF defines the frequency range.

Out-of-lock indication (pin HUNLOCK)

Pin HUNLOCK is floating during search mode, or if a protection condition is true. All this can be detected by the microcontroller if a pull-up resistor is connected to its own supply voltage.

For an additional fast vertical blanking at grid 1 of the picture tube a 1 V signal referenced to ground is available at this output. The continuous protection blanking (see Section“Videoclamping/verticalblankinggenerator”) is also available at this pin. Horizontal unlock blanking can be switched off, by control bit BLKDIS via the I2C-bus while vertical blanking is maintained.

Horizontal oscillator

The horizontal oscillator is of the relaxation type and requires a capacitor of 10 nF at HCAP (pin 29). For optimum jitter performance the value of 10 nF must not be changed.

The minimum oscillator frequency is determined by a resistor from HREF to ground. A resistor connected between pins HREF and HBUF defines the frequency range.

The reference current at pin HREF also defines the integration time constant of the vertical sync integration.

Calculation of line frequency range

The oscillator frequencies f

min

and f

max

must first be calculated. This is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies f

sync(min)

and f

sync(max)

. The oscillator is driven

by the currents in R

HREF

and R

HBUF

The following example is a 31.45 to 90 kHz application:

Table 1 Calculation of total spread

Thus the typical frequency range of the oscillator in this example is:

The resistors R

HREF

and R

HBUFpar

can be calculated using

the following formulae:

The resistor R

HBUFpar

is calculated as the value of R

HREF

and R

HBUF

in parallel.

max

min

----------

6.5 1

------- -

spread of for f

max

for f

min

IC ±3% ±5% C

HCAP

±2% ±2%

HREF

, R

HBUF

±2% ±2%

Total ±7% ±9%

maxfsync max()

1.07× 96.3 kHz==

min

sync min()

1.09

-----------------------

28.4 kHz==

HREF

78 kHz k××Ω

min

0.0012 f

min

×+ kHz[]

-----------------------------------------------------------------

2.61 kΩ==

HBUFpar

78 kHz k××Ω

max

0.0012 f

max

×+ kHz[]

--------------------------------------------------------------------

726 Ω==

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1999 Jul 13 8

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Theformulae for R

HBUF

alsotakesinto account the voltage

swing across this resistor:

PLL1 phase detector

The phase detector is a standard type using switched current sources, which are independent of horizontal frequency. It compares the middle of horizontal sync with a fixed point on the oscillator sawtooth voltage. The PLL1 loop filter is connected to HPLL1 (pin 26).

See also Section “Horizontal position adjustment and corrections”.

Horizontal position adjustment and corrections

A linear adjustment of the relative phase between the horizontal sync and the oscillator sawtooth (in PLL1 loop) is achieved via register HPOS.Once adjusted, the relative phase remains constant over the whole frequency range.

Correctionof pin unbalance and parallelogramis achieved by modulating the phase between oscillator sawtooth and horizontal flyback (in loop PLL2) via registers HPARAL and HPINBAL. If those asymmetric EW corrections are performed in the deflection stage, both registers can be disconnected from the horizontal phase via control bit ACD. This does not change the output at pin ASCOR.

Horizontal moire cancellation

To achieve a cancellation of horizontal moire (also known as ‘video moire’), the horizontal frequency is divided-by-two to achieve a modulation of the horizontal phase via PLL2. The amplitude is controlled by register HMOIRE. To avoid a visible structure on screen the polarity changes with half of the vertical frequency. Control bit MOD disables the moire cancellation function.

PLL2 phase detector

The PLL2 phase detector is similar to the PLL1 detector and compares the line flyback pulse at HFLB (pin 1) with the oscillator sawtooth voltage. The control currents are independent of the horizontal frequency. The PLL2 detector thus compensates for the delay in the external horizontal deflection circuit by adjusting the phase of the HDRV (pin 8) output pulse.

An external modulation of the PLL2 phase is not allowed, because this would disturb the pre-correction of the horizontal focus parabola.

Soft start and standby

If HPLL2 is pulled to ground, either by an external DC current or by resetting register SOFTST, the horizontal outputpulses and B+ control driver pulseswillbeinhibited. This means that HDRV (pin 8) and BDRV (pin 6) are floating in this state. In both cases PLL2 and the frequency-locked loop are disabled, and CLBL (pin 16) provides a continuous blanking signal and HUNLOCK (pin 17) is floating.

This option can be used for soft start, protection and power-down modes. When pin HPLL2 is released again, anautomatic soft start sequenceon the horizontal driveas well as on the B-drive output will be performed (see Fig.24).

A soft start can only be performed if the supply voltage for the IC is a minimum of 8.6 V.

The soft start timing is determined by the filter capacitor at HPLL2 (pin 30), which is charged with a constant current during soft start. In the beginning the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty cycle is reached. The voltage at HPLL2 increases further and performsa soft start at BDRV (pin 6) as well. After BDRV has reached full duty cycle, the voltage at HPLL2 continues to rise until HPLL2 enters its normaloperatingrange.Theinternalchargecurrentisnow disabled. Finally PLL2 and the frequency-locked loop are activated. If both functions reach normal operation, HUNLOCK (pin 17) switches from the floating status to normal vertical blanking, andcontinuous blanking at CLBL (pin 16) is removed.

Output stage for line drive pulses [HDRV (pin 8)]

An open-collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0.3 V at 20 mA. To protect the line deflection transistor, the output stage is disabled (floating) for a low supply voltage at V

(see Fig.23).

The duty cycle of line drive pulses is slightly dependent on the actual horizontal frequency. This ensures optimum drive conditions over the whole frequency range.

HBUF

HREFRHBUFpar

–

----------------------------------------------

0.8×= 805 Ω=

Page 9

1999 Jul 13 9

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

X-ray protection

TheX-rayprotectioninputXRAY(pin 2)providesavoltage detector with a precise threshold. If the input voltage at XRAY exceeds this threshold for a certain time, then control bit SOFTST is reset, which switches the IC into protection mode. In this mode several pins are forced into defined states:

HUNLOCK (pin 17) is floating The capacitor connected to HPLL2 (pin 30) is

discharged Horizontal output stage (HDRV) is floating B+ control driver stage (BDRV) is floating CLBL provides a continuous blanking signal.

There are two different methods of restarting ways the IC:

1. XSEL (pin 9) is open-circuit or connected to ground. The control bit SOFTST must be set to logic 1 via the I2C-bus. Then the IC returns to normal operation via soft start.

2. XSEL (pin 9) is connected to VCC via an external resistor.Thesupplyvoltage of the IC must be switched off for a certain period of time, before the IC can be restarted again using the standard power-on procedure.

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of vertical size after changes in sync frequency conditions. The free-running frequency f

fr(V)

is determined by the

resistor R

VREF

connected to pin 23 and the capacitor

VCAP

connected to pin 24. The value of R

VREF

is not only optimized for noise and linearity performance in the whole vertical and EW section, but also influences several internal references. Therefore the value of R

VREF

must not

be changed. Capacitor C

VCAP

should be used toselect the free-running frequency of the vertical oscillator in accordance with the following formula:

To achieve a stabilized amplitude the free-running frequencyf

fr(V)

,withoutadjustment,shouldbe at least 10% lower than the minimum trigger frequency. The contributions shown in Table 2 can be assumed.

Table 2 Calculation of f

fr(V)

total spread

Result for 50 to 160 Hz application:

The AGC of the vertical oscillator can be disabled by setting control bit AGCDIS via the I

C-bus. A precise external current has to be injected into VCAP (pin 24) to obtain the correct vertical size. This special application mode can be used when the vertical sync pulses are serrated (shifted); this condition is found in some display modes, e.g. when using a 100 Hz up converter for video signals.

Application hint: VAGC (pin 22) has a high input impedance during scan. Therefore, the pin must not be loaded externally otherwise non-linearities in the vertical output currents may occur due to the changing charge current during scan.

Adjustment of vertical size, VGA overscan and EHT compensation

There are four differentways to adjust the amplitude of the differential output currents at VOUT1 and VOUT2.

1. Register VGAIN changes the vertical size without

affecting any other output signal of the IC. This adjustment is meant for factory alignments.

2. Register VSIZE changes not only the vertical size, but

also provides the correct tracking of all other related waveforms (see Section “Tracking of vertical adjustments”). This register should be used for user adjustments.

3. For the VGA350 mode register VOVSCN can activate

a +17% step in vertical size.

4. VSMOD(pin 21) can be used for a DC controlled EHT

compensation of vertical size by correcting the differential output currents at VOUT1 and VOUT2. The EW waveforms, verticalfocus, pin unbalance and parallelogram corrections are not affected by VSMOD.

fr(V)

10.8 R

VREF

× C

VCAP

-----------------------------------------------------------

Contributing elements

Minimum frequency offset between f

fr(V)

and

lowest trigger frequency

10%

Spread of IC ±3% Spread of R

VREF

±1%

Spread of C

VCAP

±5%

Total 19%

fr(V)

50 Hz

1.19

---------------

42 Hz==

Page 10

1999 Jul 13 10

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Adjustment of vertical position, vertical linearity and vertical linearity balance

Register VOFFS provides a DC shift at the sawtooth outputs VOUT1 and VOUT2 (pins 13 and 12) without affecting any other output waveform. This adjustment is meant for factory alignments.

Register VPOS provides a DC shift at the sawtooth output VOUT1 and VOUT2 with correct tracking of all other related waveforms (see Section “Tracking of vertical adjustments”). This register should be used for user adjustments. Due to the tracking the whole picture moves vertically while maintaining the correct geometry.

Register VLIN is used to adjust the amount of the vertical S-correction in the output signal. This function can be switched off by control bit VSC.

Tracking of vertical adjustments

The adjustments via registers VSIZE, VOVSCN and VPOS also affect the waveforms of horizontal pincushion, vertical linearity (S-correction), vertical linearity balance, focus parabola, pin unbalance and parallelogram correction. The result of this interaction is that no readjustment of these parameters is necessary after an user adjustment of vertical picture size and vertical picture position.

Adjustment of vertical moire cancellation

To achieve a cancellation of vertical moire (also known as ‘scanmoire’)theverticalpicturepositioncanbemodulated by half the vertical frequency. The amplitude of the modulation is controlled by register VMOIRE and can be switched off via control bit MOD.

Horizontal pincushion (including horizontal size, corner correction and trapezium correction)

EWDRV(pin 11) provides a complete EW drive waveform. The components horizontal pincushion, horizontal size, corner correction and trapezium correction are controlled by the registers HPIN, HSIZE, HCORT, HCORB and HTRAP.

The corner correction can be adjusted separately for the top (HCORT) and bottom (HCORB) part of the picture.

The pincushion (EW parabola) amplitude, corner and trapezium correction track with the vertical picture size (VSIZE) and also with the adjustment for vertical picture position(VPOS). The corner correctiondoes not track with the horizontal pincushion (HPIN).

Further the horizontal pincushion amplitude, corner and trapezium correction track with the horizontal picture size, which is adjusted via register HSIZE and the analog modulation input HSMOD. If the DC component in the EWDRV output signal is increased via HSIZE or I

HSMOD

, the pincushion, corner and trapezium component of the EWDRV output will be reduced by a factor of

The value 14.4 V is a virtual voltage for calculation only. The output pin can not reach this value, but the gain (and DCbias)oftheexternalapplicationshouldbesuchthatthe horizontal deflection is reduced to zero when EWDRV reaches 14.4 V.

HSMOD (pin 31) can be used for a DC controlled EHT compensation by correcting horizontal size, horizontal pincushion, corner and trapezium. The control range at this pin tracks with the actual value of HSIZE. For an increasing DC component V

HSIZE

in the EWDRV output

signal, the DC component V

HEHT

caused by I

HSMOD

will be

reducedbyafactorof asshownintheequation above.

The whole EWDRV voltage is calculated as follows: V

EWDRV

= 1.2 V + [V

HSIZE+VHEHT

× f(HSIZE) + (V

HPIN

HCOR+VHTRAP

) × g(HSIZE, HSMOD)] × h(I

HREF

)

Where:

HSIZEVHEHT

HSIZE

14.4 V

-----------------

–





14.4 V

-------------------------------------------------------------------------

–

HSIZE

14.4 V

-----------------

–

HEHT

HSMOD

120 µA

------------------- -

0.69×=

f(HSIZE) 1

HSIZE

14.4 V

-----------------

–=

g(HSIZE, HSMOD) 1

HSIZEVHEHT

HSIZE

14.4 V

-----------------

–





14.4 V

--------------------------------------------------------------------------

–=

HREF

()

HREF

f70kHz=

--------------------------------

Page 11

1999 Jul 13 11

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Two different modes of operation can be chosen for the EW output waveform via control bit FHMULT:

1. Mode 1 Horizontal size is controlled via register HSIZE and

causesaDCshift at the EWDRV output. The complete waveform is also multiplied internally by a signal proportional to the line frequency [which is detected via the current at HREF (pin 28)]. This mode is to be used for driving EW diode modulator stages which require a voltage proportional to the line frequency.

2. Mode 2 The EW drive waveform does not track with the line

frequency. This mode is to be used for driving EW modulatorswhich require a voltage independent ofthe line frequency.

Output stage for asymmetric correction waveforms [ASCOR (pin 20)]

This output is designed as a voltage output for superimposed waveforms of vertical parabola and sawtooth. The amplitude and polarity of both signals can be changed by registers HPARAL and HPINBAL via the I2C-bus.

Application hint: The TDA4856 offers two possibilities to control registers HPINBAL and HPARAL.

1. Control bit ACD = 1 The two registers now control the horizontal phase by

means of internal modulation of the PLL2 horizontal phase control. The ASCOR output (pin 20) can be left unused, but it will always provide an output signal because the ASCOR output stage is not influenced by the control bit ACD.

2. Control bit ACD = 0 The internal modulation via PLL2 is disconnected.

In order to obtain the required effect on the screen, pin ASCORmust now be fedtothe DC amplifier which controls the DC shift of the horizontal deflection. This option is useful for applications which already use a DC shift transformer.

If the tube does not need HPINBAL and HPARAL, then pin ASCOR can be used for other purposes, i.e. for a simple dynamic convergence.

Dynamic focus section [FOCUS (pin 32)]

Thissectiongeneratesacompletedrivesignalfordynamic focus applications. The amplitude of the horizontal parabola is internally stabilized, thus it is independent of the horizontal frequency. The amplitude can be adjusted via register HFOCUS. Changing horizontal size may require a correction of HFOCUS. To compensate for the delay in external focus amplifiers a ‘pre-correction’ for the phase of the horizontal parabola has been implemented (see Fig.28). The amount of this pre-correction can be adjusted via register HFOCAD. The amplitude of the vertical parabola is independent of frequency and tracks with all vertical adjustments. The amplitude can be adjusted via register VFOCUS.

FOCUS (pin 32) is designed as a voltage output for the superimposed vertical and horizontal parabolas.

B+ control function block

The B+ control function block of the TDA4856 consists of an Operational Transconductance Amplifier (OTA), a voltagecomparator, a flip-flop and a dischargecircuit.This configuration allows easy applications for different B+ control concepts. See also Application Note AN96052:

“B+ converter Topologies for Horizontal Deflection and EHT with TDA4855/58”

GENERAL DESCRIPTION The non-inverting input of the OTA is connected internally

toa high precision referencevoltage. The inverting inputis connectedto BIN (pin 5). Aninternal clamping circuit limits the maximum positive output voltage of the OTA. The output itself is connected to BOP (pin 3) and to the inverting input of the voltage comparator. The non-inverting input of the voltage comparator can be accessed via BSENS (pin 4).

B+ drive pulses are generated by an internal flip-flop and fed to BDRV (pin 6) via an open-collector output stage. This flip-flop is set at the rising edge of the signal at HDRV (pin 8). The falling edge of the output signal at BDRV has a defined delay of t

d(BDRV)

to the rising edge of the HDRV pulse. When the voltage at BSENS exceeds the voltageat BOP, the voltage comparator output resets the flip-flop and, therefore, the open-collector stage at BDRV is floating again.

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I2C-bus autosync deﬂection controller for PC monitors

TDA4856

An internal discharge circuit allows a well defined discharge of capacitors at BSENS. BDRV is active at a LOW-level output voltage (see Figs 22 and 23), thus it requires an external inverting driver stage.

The B+ function block can be used for B+ deflection modulators in many different ways. Two popular application combinations are as follows:

• Boost converter in feedback mode (see Fig.22) In this application the OTA is used as an error amplifier

witha limited output voltagerange. The flip-flop isset on the rising edge of the signal at HDRV. A reset will be generated when the voltage at BSENS, taken from the current sense resistor, exceeds the voltage at BOP.

If no reset is generated within a line period, the rising edgeof the next HDRV pulseforces the flip-flop to reset. The flip-flop is set immediately after the voltage at BSENS has dropped below the threshold voltage V

RESTART(BSENS)

• Buck converter in feed forward mode (see Fig.23) This application uses an external RC combination at

BSENS to provide a pulse width which is independent from the horizontal frequency. The capacitor is charged via an external resistor and discharged by the internal discharge circuit. For normal operation the discharge circuit is activated when the flip-flop is reset by the internal voltage comparator. The capacitor will now be discharged with a constant current until the internally controlled stop level V

STOP(BSENS)

is reached. This level willbe maintained until therising edge of thenext HDRV pulse sets the flip-flop again and disables the discharge circuit.

If no reset is generated within a line period, the rising edge of the next HDRV pulse automatically starts the discharge sequence and resets the flip-flop. When the voltage at BSENS reaches the threshold voltage V

RESTART(BSENS)

, the discharge circuit will be disabled automatically and the flip-flop will be set immediately. This behaviour allows a definition of the maximum duty cycle of the B+ control drive pulse by the relationship of charge current to discharge current.

Supply voltage stabilizer, references, start-up procedures and protection functions

The TDA4856 provides an internal supply voltage stabilizer for excellent stabilization of all internal references.Aninternalgap reference, especially designed for low-noise, is the reference for the internal horizontal andverticalsupplyvoltages.Allinternalreference currents and drive current for the vertical output stage are derived from this voltage via external resistors.

If either the supply voltage is below 8.3 V or no data from the I2C-bus has been received after power-up, the internal softstart and protection functions do not allowanyof those outputs [HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK (see Fig.24)] to be active.

For supply voltages below 8.3 V the internal I2C-bus will not generate an acknowledge and the IC is in standby mode. This is because the internal protection circuit has generated a reset signal for the soft start register SOFTST. Above 8.3 V data is accepted and all registers can be loaded. If the register SOFTST has received a set from the I2C-bus, the internal soft start procedure is released, which activates all above mentioned outputs.

If during normal operation the supply voltage has dropped below 8.1 V, the protection mode is activated and HUNLOCK(pin 17)changesto the protection status and is floating. This can be detected by the microcontroller.

This protection mode has been implemented in order to protect the deflection stages and the picture tube during start-up, shut-down and fault conditions. This protection mode can be activated as shown in Table 3.

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Table 3 Activation of protection mode

When the protection mode is active, several pins of the TDA4856 are forced into a defined state:

HDRV (horizontal driver output) is floating BDRV (B+ control driver output) is floating HUNLOCK (indicates, that the frequency-to-voltage

converter is out of lock) is floating (HIGH-level via external pull-up resistor)

CLBL provides a continuous blanking signal The capacitor at HPLL2 is discharged.

If the soft start procedure is activated via the I2C-bus, all of these actions will beperformed in a well defined sequence (see Figs 24 and 25).

Power dip recognition

In standby mode the I2C-bus will only answer with an acknowledge, when data is sent to control register with subaddress 1AH. This register contains the standby and soft start control bit.

If the I2C-bus master transmits data to another register, an aknowledge is given after the chip address and the subaddress; an acknowledge is not given after the data. This indicates that only in soft start mode data can be stored into normal registers.

If the supply voltage dips under 8.1 V the TDA4856leaves normal operation mode and changes into standby mode. The microcontroller can check this state by sending data intoaregister with the subaddress 0XH. The acknowledge will only be given on the data if the TDA4856 is active.

Due to this behaviour the start-up of the TDA4856 is defined as follows. The first data that is transferred to the TDA4856 must be sent to the control register with subaddress 1AH. Any other subaddress will not lead to an acknowledge. This is a limitation in checking the I2C-busses of the monitor during start-up.

ACTIVATION RESET

Low supply voltage at pin 10 increase supply voltage;

reload registers; soft start via I2C-bus

Power dip, below 8.1 V reload registers;

soft start via I2C-bus or via supply voltage

X-ray protection XRAY (pin 2) triggered

reload registers; soft start via I2C-bus

HPLL2 (pin 30) externally pulled to ground

release pin 30

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); all voltages measured with respect to ground.

Notes

1. Machine model: 200 pF; 0.75 µH; 10 Ω.

2. Human body model: 100 pF; 7.5 µH; 1500 Ω.

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

In accordance with

“URF-4-2-59/601”

; EMC emission/immunity test in accordance with

“DIS 1000 4.6”

(IEC 801.6).

Note

1. Tests are performed with application reference board. Tests with other boards will have different results.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

supply voltage −0.5 +16 V

i(n)

input voltage on pins:

BIN −0.5 +6.0 V HSYNC, VSYNC, VREF, HREF, VSMOD and HSMOD −0.5 +6.5 V SDA and SCL −0.5 +8.0 V XRAY −0.5 +8.0 V

o(n)

output voltage on pins:

VOUT2, VOUT1 and HUNLOCK −0.5 +6.5 V BDRV and HDRV −0.5 +16 V

I/O(n)

input/output voltages at pins BOP and BSENS −0.5 +6.0 V

o(HDRV)

horizontal driver output current − 100 mA

i(HFLB)

horizontal ﬂyback input current −10 +10 mA

o(CLBL)

video clamping pulse/vertical blanking output current −−10 mA

o(BOP)

B+ control OTA output current − 1mA

o(BDRV)

B+ control driver output current − 50 mA

o(EWDRV)

EW driver output current −−5mA

o(FOCUS)

focus driver output current −−5mA

amb

operating ambient temperature −20 +70 °C

junction temperature − 150 °C

stg

storage temperature −55 +150 °C

ESD

electrostatic discharge for all pins note 1 −150 +150 V

note 2 −2000 +2000 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 55 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

EMC

emission test note 1 − 1.5 − mV immunity test note 1 − 2.0 − V

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

CHARACTERISTICS

VCC= 12 V; T

amb

=25°C; peripheral components in accordance with Fig.1; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Horizontal sync separator

NPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS: PIN HSYNC

i(HSYNC)

sync input signal voltage 1.7 −−V

HSYNC(sl)

slicing voltage level 1.2 1.4 1.6 V

r(HSYNC)

rise time of sync pulse 10 − 500 ns

f(HSYNC)

fall time of sync pulse 10 − 500 ns

W(HSYNC)(min)

minimum width of sync pulse 0.7 −−µs

i(HSYNC)

input current V

HSYNC

= 0.8 V −−−200 µA

HSYNC

= 5.5 V −−10 µA INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY) V

HSYNC

sync amplitude of video input signal voltage

source

=50Ω−300 − mV

HSYNC(sl)

slicing voltage level (measured from top sync)

source

=50Ω 90 120 150 mV

clamp(HSYNC)

top sync clamping voltage level

source

=50Ω 1.1 1.28 1.5 V

ch(HSYNC)

charge current for coupling capacitor

HSYNC>Vclamp(HSYNC)

1.7 2.4 3.4 µA

W(HSYNC)(min)

minimum width of sync pulse 0.7 −−µs

source(max)

maximum source resistance duty cycle = 7% −−1500 Ω

i(diff)(HSYNC)

differential input resistance during sync − 80 −Ω

Automatic polarity correction for horizontal sync

horizontal sync pulse width related to line period

−−25 %

d(HPOL)

delay time for changing polarity

0.3 − 1.8 ms

Vertical sync integrator

int(V)

integration time for generation of a vertical trigger pulse

fH= 15.625 kHz; I

HREF

= 0.52 mA

14 20 26 µs

fH= 31.45 kHz; I

HREF

= 1.052 mA

71013µs

fH= 64 kHz; I

HREF

= 2.141 mA

3.9 5.7 6.5 µs

fH= 100 kHz; I

HREF

= 3.345 mA

2.5 3.8 4.5 µs

Vertical sync slicer (DC-coupled, TTL compatible): pin VSYNC

i(VSYNC)

sync input signal voltage 1.7 −−V

VSYNC(sl)

slicing voltage level 1.2 1.4 1.6 V

i(VSYNC)

input current 0 V < V

SYNC

< 5.5 V −−±10 µA

P(H)

---------- -

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Automatic polarity correction for vertical sync

W(VSYNC)(max)

maximum width of vertical sync pulse

−−400 µs

d(VPOL)

delay for changing polarity 0.45 − 1.8 ms

Video clamping/vertical blanking output: pin CLBL

clamp(CLBL)

width of video clamping pulse measured at V

CLBL

= 3 V 0.6 0.7 0.8 µs

clamp(CLBL)

top voltage level of video clamping pulse

4.32 4.75 5.23 V

clamp

temperature coefﬁcient of V

clamp(CLBL)

− 4 − mV/K

STPS

clamp

steepness of slopes for clamping pulse

RL=1MΩ; CL=20pF − 50 − ns/V

d(HSYNCt-CLBL)

delay between trailing edge of horizontal sync and start of video clamping pulse

clamping pulse triggered on trailing edge of horizontal sync; control bit CLAMP = 0; measured at V

CLBL

=3V

− 130 − ns

clamp1(max)

maximum duration of video clamping pulse referenced to end of horizontal sync

−−1.0 µs

d(HSYNCl-CLBL)

delay between leading edge of horizontal sync and start of video clamping pulse

clamping pulse triggered on leading edge of horizontal sync; control bit CLAMP = 1; measured at V

CLBL

=3V

− 300 − ns

clamp2(max)

maximum duration of video clamping pulse referenced to end of horizontal sync

−−0.15 µs

blank(CLBL)

top voltage level of vertical blanking pulse

notes 1 and 2 1.7 1.9 2.1 V

blank(CLBL)

width of vertical blanking pulse at pins CLBL and HUNLOCK

control bit VBLK = 0 220 260 300 µs control bit VBLK = 1 305 350 395 µs

blank

temperature coefﬁcient of V

blank(CLBL)

− 2 − mV/K

scan(CLBL)

output voltage during vertical scan

CLBL

= 0 0.59 0.63 0.67 V

scan

temperature coefﬁcient of V

scan(CLBL)

−−2 − mV/K

sink(CLBL)

internal sink current 2.4 −−mA

L(CLBL)

external load current −−−3.0 mA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Horizontal oscillator: pins HCAP and HREF

fr(H)

free-running frequency without PLL1 action (for testing only)

HBUF

= ∞;

HREF

= 2.4 kΩ;

HCAP

= 10 nF; note 3

30.53 31.45 32.39 kHz

∆f

fr(H)

spread of free-running frequency(excludingspreadof external components)

−−±3.0 %

temperature coefﬁcient of free-running frequency

−100 0 +100 10−6/K

H(max)

maximum oscillator frequency −−130 kHz

HREF

voltage at input for reference current

2.43 2.55 2.68 V

Unlock blanking detection: pin HUNLOCK

scan(HUNLOCK)

low level of HUNLOCK saturation voltage in case

of locked PLL1; internal sink current = 1 mA

−−250 mV

blank(HUNLOCK)

blanking level of HUNLOCK external load current = 0 0.9 1 1.1 V

blank

temperature coefﬁcient of V

blank(HUNLOCK)

−−0.9 − mV/K

sink

temperature coefﬁcient of I

sink(HUNLOCK)

− 0.15 − %/K

sink(int)

internal sink current for blanking pulses;

PLL1 locked

1.4 2.0 2.6 mA

L(HUNLOCK)

maximum external load current

HUNLOCK

=1V −−−2mA

leakage current V

HUNLOCK

= 5 V in case of unlocked PLL1 and/or protection active

−−±5 µA

PLL1 phase comparator and frequency-locked loop: pins HPLL1 and HBUF

W(HSYNC)(max)

maximum width of horizontal sync pulse (referenced to line period)

−−25 %

lock(HPLL1)

total lock-in time of PLL1 − 40 80 ms

ctrl(HPLL1)

control currents notes 4 and 5

locked mode; level 1 − 15 −µA locked mode; level 2 − 145 −µA

HBUF

buffered f/v voltage at HBUF (pin 27)

minimum horizontal frequency

− 2.55 − V

maximum horizontal frequency

− 0.5 − V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Phase adjustments and corrections via PLL1 and PLL2

HPOS horizontal position (referenced

to horizontal period)

HPINBAL horizontal pin unbalance

correction via HPLL2 (referenced to horizontal period)

−−1.2 − %

− 1.2 − %

− 0.02 − %

HPARAL horizontal parallelogram

correction (referenced to horizontal period)

−−1.2 − %

− 1.2 − %

− 0.02 − %

HMOIRE relative modulation of

horizontal position by 0.5fH; phase alternates with 0.5f

− 0 − %

− 0.07 − %

HMOIRE

off

moire cancellation off control bit MOD = 1 − 0 − %

PLL2 phase detector: pins HFLB and HPLL2

PLL2

PLL2 control (advance of horizontal drive with respect to middle of horizontal ﬂyback)

maximum advance; register HPINBAL = 32; register HPARAL = 32

36 −−%

minimum advance; register HPINBAL = 32; register HPARAL = 32

− 7 − %

ctrl(PLL2)

PLL2 control current − 75 −µA

PLL2

relative sensitivity of PLL2 phase shift related to horizontal period

− 28 − mV/%

PROT(HPLL2)(max)

maximum voltage for PLL2 protection mode/soft start

− 4.6 − V

ch(HPLL2)

charge current for external capacitor during soft start

HPLL2

< 3.7 V − 1 −µA

dch(HPLL2)

discharge current for external capacitor during soft down

HPLL2

< 3.7 V −−1 −µA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

HORIZONTAL FLYBACK INPUT: PIN HFLB V

pos(HFLB)

positive clamping level I

HFLB

=5mA − 5.5 − V

neg(HFLB)

negative clamping level I

HFLB

= −1mA −−0.75 − V

pos(HFLB)

positive clamping current −−6mA

neg(HFLB)

negative clamping current −−−2mA

sl(HFLB)

slicing level − 2.8 − V

Output stage for line driver pulses: pin HDRV

OPEN-COLLECTOR OUTPUT STAGE V

sat(HDRV)

saturation voltage I

HDRV

=20mA −−0.3 V

HDRV

=60mA −−0.8 V

LO(HDRV)

output leakage current V

HDRV

=16V −−10 µA AUTOMATIC VARIATION OF DUTY CYCLE t

HDRV(OFF)/tH

relative t

OFF

time of HDRV output; measured at V

HDRV

= 3 V; HDRV duty cycle is modulated by the relation I

HREF/IVREF

HDRV

=20mA;

fH= 31.45 kHz; see Fig.16

42 45 48 %

HDRV

=20mA;

fH= 58 kHz; see Fig.16

45.5 48.5 51.5 %

HDRV

=20mA;

fH= 110 kHz; see Fig.16

49 52 55 %

X-ray protection: pin XRAY

XRAY(sl)

slicing voltage level for latch 6.22 6.39 6.56 V

W(XRAY)(min)

minimum width of trigger pulse −−30 µs

i(XRAY)

input resistance at XRAY (pin 2)

XRAY

<6.38V+V

500 −−kΩ

XRAY

>6.38V+V

− 5 − kΩ

standby mode − 5 − kΩ

XRAY

rst

reset of X-ray latch pin 9 open-circuit or

connected to GND

set control bit SOFTST via I2C-bus

pin 9 connected to VCCvia R

XSEL

switch off VCC, then re-apply V

CC(XRAY)(min)

minimum supply voltage for correct function of the X-ray latch

pin 9 connected to VCCvia R

XSEL

−−4V

CC(XRAY)(max)

maximum supply voltage for reset of the X-ray latch

pin 9 connected to VCCvia R

XSEL

2 −−V

XSEL

external resistor at pin 9 no reset via I2C-bus 56 − 130 kΩ

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Vertical oscillator [oscillator frequency in application without adjustment of free-running frequency f

fr(V)

]

fr(V)

free-running frequency R

VREF

=22kΩ;

VCAP

= 100 nF

40 42 43.3 Hz

cr(V)

vertical frequency catching range

constant amplitude; note 7 50 − 160 Hz

VREF

voltage at reference input for vertical oscillator

− 3.0 − V

d(scan)

delay between trigger pulse and start of ramp at VCAP (pin 24) (width of vertical blanking pulse)

control bit VBLK = 0 220 260 300 µs control bit VBLK = 1 305 350 395 µs

VAGC

currents of amplitude control control bit AGCDIS = 0 ±120 ±200 ±300 µA

control bit AGCDIS = 1 − 0 −µA

VAGC

external capacitor at VAGC (pin 22)

150 − 220 nF

Differential vertical current outputs

ADJUSTMENT OF VERTICAL SIZE INCLUDING VGA AND EHT COMPENSATION; see Figs 3 and 4 VGAIN vertical size (gain) without

VGA overscan (referenced to nominal vertical size)

− 70 − %

− 100 − %

VSIZE vertical size (size) without VGA

overscan (referenced to nominal vertical size)

− 60 − %

− 100 − %

VSIZE

VGA

vertical size with VGA overscan (referenced to nominal vertical size)

− 70 − %

115.9 116.8 117.7 %

VSMOD

EHT

EHT compensation on vertical size via VSMOD (pin 21) (referenced to 100% vertical size)

VSMOD

=0 − 0 − %

VSMOD

= −120 µA −−7 − %

i(VSMOD)

input current (pin 21) VSMOD = 0 − 0 −µA

VSMOD = −7% −−120 −µA

i(VSMOD)

input resistance 300 − 500 Ω

ref(VSMOD)

reference voltage at input − 5.0 − V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

ro(VSMOD)

roll-off frequency (−3 dB) I

VSMOD

= −60 µA

+15µA (RMS value)

1 −−MHz

ADJUSTMENT OF VERTICAL POSITION (see Fig.5) VOFFS vertical position (referenced to

100% vertical size)

VPOS vertical position (referenced to

100% vertical size)

register VPOS = 64 − 0.09 − % ADJUSTMENT OF VERTICAL LINEARITY; see Fig.6 VLIN vertical linearity (S-correction) register VLIN = 0; control

bit VSC = 0; note 8

− 2 − %

bit VSC = 0; note 8

− 46 − %

bit VSC = 1; note 8

− 0 − %

δVLIN symmetry error of S-correction maximum VLIN −−±0.7 %

ADJUSTMENT OF VERTICAL LINEARITY BALANCE; see Fig.7 VLINBAL vertical linearity balance

(referenced to 100% vertical size)

note 8

−1.85 −1.40 −0.95 %

note 8

0.95 1.40 1.85 %

note 8

− 0.08 − %

VMOIRE modulation of vertical picture

position by1⁄2vertical frequency (related to 100% vertical size)

control bit MOD = 0

− 0 − %

control bit MOD = 0

− 0.08 − %

moire cancellation off control bit MOD = 1 − 0 − % Vertical output stage: pins VOUT1 and VOUT2; see Fig.27 ∆I

VOUT(nom)(p-p)

nominal differential output

current (peak-to-peak value)

∆I

VOUT=IVOUT1

− I

VOUT2

;

nominal settings; note 8

0.76 0.85 0.94 mA

o(VOUT)(max)

maximum output current at

pins VOUT1 and VOUT2

control bit VOVSCN = 1 0.54 0.6 0.66 mA

VOUT

allowed voltage at outputs 0 − 4.2 V δI

os(vert)(max)

maximum offset error of

vertical output currents

nominal settings; note 8 −−±2.5 %

δI

lin(vert)(max)

maximum linearity error of

vertical output currents

nominal settings; note 8 −−±1.5 %

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

EW drive output

EW DRIVE OUTPUT STAGE: pin EWDRV; see Figs 8 to 11 V

const(EWDRV)

bottom output voltage at

pin EWDRV

(internally stabilized)

1.05 1.2 1.35 V

o(EWDRV)(max)

maximum output voltage note 9 7.0 −−V I

L(EWDRV)

load current −−±2mA TC

EWDRV

temperature coefﬁcient of

output signal

−−600 10−6/K

HPIN(EWDRV)

horizontal pincushion register HPIN = 0; control

bit VSC = 1; note 8

− 0.04 − V

− 1.42 − V

HCORT(EWDRV)

horizontal corner correction at

top of picture

− 0.2 − V

−−0.64 − V

− 0 − V

HCORB(EWDRV)

horizontal corner correction at

bottom of picture

− 0.2 − V

−−0.64 − V

− 0 − V

HTRAP(EWDRV)

horizontal trapezium correction register HTRAP = 63;

note 8

−−0.5 − V

− 0.5 − V

−−0.01 − V

HSIZE(EWDRV)

horizontal size register HSIZE = 255;

note 8

− 0.13 − V

HEHT(EWDRV)

EHT compensation on

horizontal size via HSMOD

(pin 31)

HSMOD

= 0; note 8 − 0.02 − V

HSMOD

= −120 µA; note 8 − 0.69 − V

i(HSMOD)

input current (pin 31) V

HEHT

= 0.02 V − 0 −µA

HEHT

= 0.69 V −−120 −µA

i(HSMOD)

input resistance 300 − 500 Ω V

ref(HSMOD)

reference voltage at input I

HSMOD

=0 − 5.0 − V

ro(HSMOD)

roll-off frequency (−3 dB) I

HSMOD

= −60 µA

+15µA (RMS)

1 −−MHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

TRACKING OF EWDRV OUTPUT SIGNAL WITH HORIZONTAL FREQUENCY PROPORTIONAL VOLTAGE f

H(MULTI)

horizontal frequency range for

tracking

15 − 80 kHz

PAR(EWDRV)

parabola amplitude at EWDRV

(pin 11)

HREF

= 1.052 mA; fH= 31.45 kHz; control bit FHMULT = 1; note 10

− 0.72 − V

HREF

= 2.341 mA; fH= 70 kHz; control bit FHMULT = 1; note 10

− 1.42 − V

function disabled; control bit FHMULT = 0; note 10

− 1.42 − V

EWDRV

linearity error of horizontal frequency tracking

−−8%

Output for asymmetric EW corrections: pin ASCOR

HPARAL(ASCOR)

vertical sawtooth voltage for EW parallelogram correction

−−0.825 − V

− 0.825 − V

− 0.05 − V

HPINBAL(ASCOR)

vertical parabola for pin unbalance correction

−−1.0 − V

− 1.0 − V

− 0.05 − V

o(ASCOR)(max)(p-p)

maximumoutputvoltageswing (peak-to-peak value)

− 4 − V

o(ASCOR)(max)

maximum output voltage − 6.5 − V

c(ASCOR)

centre voltage − 4.0 − V

o(ASCOR)(min)

minimum output voltage − 1.9 − V

o(ASCOR)(max)

maximum output current V

ASCOR

≥ 1.9 V −−1.5 − mA

o(sink)(ASCOR)(max)

maximum output sink current V

ASCOR

≥ 1.9 V − 50 −µA Focus section: pin FOCUS; see Figs 15 and 28 t

precor

pre-correction of phase for horizontal focus parabola

register HFOCAD = 0 − 300 − ns register HFOCAD = 1 − 350 − ns register HFOCAD = 2 − 400 − ns register HFOCAD = 3 − 450 − ns

W(hfb)(min)

minimum horizontal ﬂyback pulse width

1.9 −−µs

W(hfb)(max)

maximum horizontal ﬂyback pulse width

−−5.5 µs

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Page 24

1999 Jul 13 24

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

W(hfb)(off)

minimum width of horizontal ﬂyback pulse for operation without pre-correction

− 7.5 −µs

HFOCUS(p-p)

amplitude of horizontal focus parabola (peak-to-peak value)

VFOCUS(p-p)

amplitude of vertical parabola (peak-to-peak value)

− 0.02 − V

− 1.1 − V

o(FOCUS)(max)

maximum output voltage I

FOCUS

= 0 6.15 6.4 6.65 V

o(FOCUS)(min)

minimum output voltage I

FOCUS

= 0 1.0 1.3 1.6 V

o(FOCUS)(max)

maximum output current ±1.5 −−mA

L(FOCUS)(max)

maximum capacitive load −−20 pF

B+ control section; see Figs 22 and 23 TRANSCONDUCTANCE AMPLIFIER: PINS BIN AND BOP

i(BIN)

input voltage 0 − 5.25 V

i(BIN)(max)

maximum input current −−±1 µA

ref(int)

reference voltage at internal non-inverting input of OTA

2.37 2.5 2.58 V

o(BOP)(min)

minimum output voltage −−0.5 V

o(BOP)(max)

maximum output voltage I

BOP

< 1 mA 5.0 5.3 5.6 V

o(BOP)(max)

maximum output current −±500 −µA

m(OTA)

transconductance of OTA note 11 30 50 70 mS

v(ol)

open-loop voltage gain note 12 − 86 − dB

BOP(min)

minimum value of capacitor at BOP

10 −−nF

VOLTAGE COMPARATOR: PIN BSENS V

i(BSENS)

voltage range of positive comparator input

0 − 5V

i(BOP)

voltage range of negative comparator input

0 − 5V

L(BSENS)(max)

maximum leakage current discharge disabled −−−2 µA OPEN-COLLECTOR OUTPUT STAGE: PIN BDRV I

o(BDRV)(max)

maximum output current note 13 20 −−mA I

LO(BDRV)

output leakage current V

BDRV

=16V −−3 µA

sat(BDRV)

saturation voltage I

BDRV

<20mA −−300 mV

off(BDRV)(min)

minimum off-time − 250 − ns t

d(BDRV-HDRV)

delay between BDRV pulse

and HDRV pulse

measured at V

HDRV=VBDRV

=3V

− 500 − ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Page 25

1999 Jul 13 25

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

BSENS DISCHARGE CIRCUIT: PIN BSENS V

STOP(BSENS)

discharge stop level capacitive load;

BSENS

= 0.5 mA

0.85 1.0 1.15 V

dch(BSENS)

discharge current V

BSENS

> 2.5 V 4.5 6.0 7.5 mA

th(BSENS)(restart)

threshold voltage for restart fault condition 1.2 1.3 1.4 V C

BSENS(min)

minimum value of capacitor at

BSENS (pin 4)

2 −−nF

Internal reference, supply voltage, soft start and protection

CC(stab)

external supply voltage for

complete stabilization of all

internal references

9.2 − 16 V

supply current − 70 − mA I

CC(stb)

standby supply current STDBY = 1; V

PLL2

<1V;

3.5V<VCC<16V

− 9 − mA

PSRR power supply rejection ratio of

internal supply voltage

f = 1 kHz 50 −−dB

CC(blank)

supply voltage level for

activation of continuous

blanking

VCC decreasing from 12 V 8.2 8.6 9.0 V

CC(blank)(min)

minimum supply voltage level

for function of continuous

blanking

VCC decreasing from 12 V 2.5 3.5 4.0 V

on(VCC)

supply voltage level for

activation of HDRV, BDRV,

VOUT1, VOUT2 and

HUNLOCK

VCCincreasing from below typical 8.1 V

7.9 8.3 8.7 V

off(VCC)

supply voltage level for

deactivation of BDRV, VOUT1,

VOUT2 and HUNLOCK; also

sets register SOFTST

VCC decreasing from above typical 8.3 V

7.7 8.1 8.5 V

THRESHOLDS DERIVED FROM HPLL2 VOLTAGE V

HPLL2(blank)(ul)

upper limit voltage for

continuous blanking

− 4.6 − V

HPLL2(bduty)(ul)

upper limit voltage for variation

of BDRV duty cycle

− 4.0 − V

HPLL2(bduty)(ll)

lower limit voltage for variation

of BDRV duty cycle

− 3.2 − V

HPLL2(hduty)(ul)

upper limit voltage for variation

of HDRV duty cycle

− 3.2 − V

HPLL2(hduty)(ll)

lower limit voltage for variation

of HDRV duty cycle

− 1.8 − V

HPLL2(stb)(ul)

upper limit voltage for standby

voltage

− 1 − V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Page 26

1999 Jul 13 26

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Notes

1. For duration of vertical blanking pulse see subheading ‘Vertical oscillator [oscillator frequency in application without adjustment of free-running frequency f

fr(V)

]’.

2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true: a) No horizontal flyback pulses at HFLB (pin 1) within a line b) X-ray protection is triggered c) Voltage at HPLL2 (pin 30) is low during soft start d) Supply voltage at VCC (pin 10) is low e) PLL1 unlocked while frequency-locked loop is in search mode.

3. Oscillator frequency is f

min

when no sync input signal is present (continuous blanking at pins 16 and 17).

4. Loading of HPLL1 (pin 26) is not allowed.

5. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed by an internal sample-and-hold circuit.

6. All vertical and EW adjustments according note 8, but VSIZE = 80% (register VSIZE = 63, VGAIN = 63 and control bit VOVSCN = 0).

7. Value of resistor at VREF (pin 23) may not be changed.

8. All vertical and EW adjustments are specified at nominal vertical settings; unless otherwise specified, which means: a) VSIZE = 100% (register VSIZE = 127, VGAIN = 63 and control bit VOVSCN = 0) b) VSMOD = 0 (no EHT compensation) c) VPOS centred (register VPOS = 64) d) VLIN = 0 (register VLIN = X and control bit VSC = 1) e) VLINBAL = 0 (register VLINBAL = 8) f) FHMULT = 0 g) HPARAL = 0 (register HPARAL = 32) h) HPINBAL = 0 (register HPINBAL = 32) i) Vertical oscillator synchronized.

9. The output signal at EWDRV (pin 11) may consist of horizontal pincushion + corner correction + DC shift + trapezium correction. If the control bit VOVSCN is set, and the VPOS adjustment is set to an extreme value, the tip of the parabola may be clipped at the upper limit of the EWDRV output voltage range. The waveform of corner correction will clip if the vertical sawtooth adjustment exceeds 110% of the nominal setting.

10. If fH tracking is enabled, the amplitude of the complete EWDRV output signal (horizontal pincushion + corner correction + DC shift + trapezium) will be changed proportional to I

HREF

. The EWDRV low level of 1.2 V remains fixed.

11. First pole of transconductance amplifier is5 MHz without external capacitor (will become the second pole, if the OTA operates as an integrator).

12. Open-loop gain is at f = 0 with no resistive load and C

BOP

= 10 nF [from BOP (pin 3) to GND].

13. The recommended value for the pull-up resistor BDRV (pin 6) is 1 kΩ.

BOP

BIN

--------------

Page 27

1999 Jul 13 27

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Vertical and EW adjustments

handbook, halfpage

VOUT1

VOUT2

∆l

(1)

MBG590

Fig.3 Adjustment of vertical size (VSIZE).

(1) ∆I1 is the maximum amplitude setting at register VSIZE = 127,

,VSIZE

I∆

------- -

100%×= VSMOD

I∆

------- -

100%×=

Fig.4 Adjustment of vertical size (VGAIN).

(1) ∆I1 is the maximum amplitude setting at register VSIZE = 127,

VGAIN

I∆

------- -

100%×=

handbook, halfpage

MGS274

VOUT1

VOUT2

∆I

(1)

Fig.5 Adjustment of vertical position.

handbook, halfpage

VOUT1

VOUT2

∆l

(1)

MBG592

(1) ∆I1 is the maximum amplitude setting at register VSIZE = 127

and register VGAIN = 63.

,VPOS

∆ I1∆–

∆×

--------------------- -

100%×= VOFFS

∆ I1∆–

∆×

--------------------- -

100%×=

Fig.6 Adjustment of vertical linearity (vertical

S-correction).

(1) ∆I1 is the maximum amplitude setting at register VSIZE = 127

and VLIN = 0%.

VLIN

I∆

1I∆2

–

∆

--------------------- -

100%×=

handbook, halfpage

VOUT1

VOUT2

∆l2/∆t

∆l

(1)

/∆t

MBG594

Page 28

1999 Jul 13 28

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Fig.7 Adjustment of vertical linearity balance.

(1) ∆I1 is the maximum amplitude setting at register VSIZE = 127

and register VOVSCN = 0.

VLINBAL

I∆

1I∆2

–

∆×

--------------------- -

100%×=

handbook, halfpage

VOUT1

VOUT2

∆I

(1)

∆I

MGM068

Fig.8 Adjustment of parabola amplitude at

pin EWDRV.

handbook, halfpage

EWDRV

HPIN(EWDRV)

MGM069

Fig.9 Influence of corner correction at pin EWDRV.

handbook, halfpage

EWDRV

HCOR(EWDRV)

MGM070

Fig.10 Influence of trapezium at pin EWDRV.

handbook, halfpage

EWDRV

HTRAP(EWDRV)

MGM071

Page 29

1999 Jul 13 29

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Fig.11 Influence of HSIZE and EHT compensation

at pin EWDRV.

handbook, halfpage

EWDRV

HSIZE(EWDRV)

HEHT(EWDRV)

MGM072

Fig.12 Adjustment of parallelogram at pin ASCOR.

handbook, halfpage

HPARAL(ASCOR)

MGM073

ASCOR

c(ASCOR)

Fig.13 Adjustment of pin balance at pin ASCOR.

handbook, halfpage

ASCOR

HPINBAL(ASCOR)

MGM074

c(ASCOR)

Page 30

1999 Jul 13 30

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Pulse diagrams

Fig.14 Pulse diagram for vertical part.

handbook, full pagewidth

internal trigger

inhibit window

(typical 4 ms)

1.4 V

3.8 V

automatic trigger level

vertical sync pulse

4.0 V

differential output currents

VOUT1 (pin 13) and

VOUT2 (pin 12)

inhibited

vertical oscillator sawtooth

at VCAP (pin 24)

vertical blanking pulse

at CLBL (pin 16)

vertical blanking pulse

at HUNLOCK (pin 17)

synchronized trigger level

EW drive waveform

at EWDRV (pin 11)

DC shift 3.6 V maximum

7.0 V maximum

low-level 1.2 V fixed

VOUT1

VOUT2

MGM075

Page 31

1999 Jul 13 31

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Fig.15 Pulse diagram for horizontal part.

handbook, full pagewidth

–

horizontal sync pulse

PLL2 control current

at HPLL2 (pin 30)

PLL1 control current

at HPLL1 (pin 26)

line flyback pulse

at HFLB (pin 1)

horizontal oscillator sawtooth

at HCAP (pin 29)

line drive pulse

at HDRV (pin 8)

triggered on trailing edge

of horizontal sync

video clamping pulse

at CLBL (pin 16)

vertical blanking level

horizontal focus parabola

at FOCUS (pin 32)

PLL2

control range

45 to 52% of line period

MGS275

Page 32

1999 Jul 13 32

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Fig.16 Relative t

OFF

time of HDRV versus H-frequency.

handbook, full pagewidth

relative t

HDRV(OFF)/tH

(%)

MGM077

15 30 110 130

fH (kHz)

Fig.17 Pulse diagrams for composite sync applications.

a. Reduced influence of vertical sync on horizontal phase.

b. Generation of video clamping pulses during vertical sync with serration pulses.

handbook, full pagewidth

composite sync (TTL)

internal integration of

composite sync

internal vertical

trigger pulse

PLL1 control voltage

at HPLL1 (pin 26)

at HSYNC (pin 15)

pulses at CLBL (pin 16)

clamping and blanking

MGC947

handbook, full pagewidth

composite sync (TTL)

at HSYNC (pin 15)

clamping and blanking

pulses at CLBL (pin 16)

MBG596

Page 33

1999 Jul 13 33

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

I2C-BUS PROTOCOL Data format Table 4 Data format

Notes

1. S = START condition.

2. SLAVE ADDRESS (MAD) = 1000 1100.

3. A = acknowledge, generatedbythe slave. No acknowledge, ifthesupply voltage is below 8.2 V forstart-upand 8.0 V for shut-down procedure.

4. SUBADDRESS (SAD).

5. DATA byte. If more than 1 byte of DATA is transmitted, then no auto-increment of the significant subaddress is performed.

6. P = STOP condition.

(1)

SLAVE ADDRESS

(2)

(3)

SUB-ADDRESS

(4)

(3)

DA TA

(5)

(3)

(6)

It should be noted that clock pulses according to the 400 kHz specification are accepted for 3.3 and 5 V applications (reference level = 1.8 V).

Default register values after power-up are random. All registers have to be preset via software before the soft start is enabled.

Important: If register contents are changed during the vertical scan, this might result in a visible interference on the screen. The cause for this interference is the abrupt change of picture geometry which takes effect at random locations within the visible picture. To avoid this kind of interference, at least the adjustment of some critical geometry parameters should be synchronized with the vertical flyback. The TDA4856 offers a feature to synchronize any I2C-bus adjustment with the internal vertical flyback pulse. For this purpose the IC offers two different modes for the handling of I2C-bus data:

• Direct mode

• Buffered mode.

Direct mode

The direct mode is selected by setting the MSB of the I2C-bus register subaddress to logic 0.

Any I2C-bus command is executed immediately after it was received, so the adjustment takes effect immediately after the end of I2C-bus transmission.

This mode should be used if many register values have to be changed subsequently, i.e. during start-up, mode change, etc., and while there is no picture visible on the screen (blanked). The number of transmissions per V-period is not limited.

Buffered mode

The buffered mode is selected by setting the MSB of the I2C-bus register subaddress to logic 1.

Thismode is designed to avoidvisibleinterferences on the screen during the I2C-bus adjustments. This mode should be used, if a single register has to be changed while the picture is visible, so i.e. for user adjustments.

One received I2C-bus data byte is stored in an internal 8-bit buffer before itis passed tothe DAC section. The first internal vertical blanking pulse (VBL) after end of transmission is used to synchronize the adjustment change with the vertical flyback. So the actual change of the picture size, position, geometry, etc. will take place during the vertical flyback period, and will thus be invisible.

The IC gives acknowledge for chip address, subaddress and data of a buffered transmission. Only one I2C-bus transmission is accepted after each vertical blank. After one buffered transmission, the IC gives no acknowledge for further transmissions until next VBL pulse has occurred. The buffered mode is disabled while the IC is in standby mode.

Page 34

1999 Jul 13 34

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

List of I2C-bus controlled switches

I2C-bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress:

• SAD1 is the register subaddress to be used for transmissions in direct mode

• SAD2 is the register subaddress to be used for transmissions in buffered mode.

Table 5 Controlled switches; notes 1 and 2

Notes

1. X = don’t care.

2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be transferred.

3. Bits STDBY and SOFTST can be reset by the internal protection circuit.

CONTROL

BIT

FUNCTION

SAD1 (HEX)

SAD2 (HEX)

D7 D6 D5 D4 D3 D2 D1 D0

BLKDIS 0: vertical, protection and horizontal unlock

blanking available on pins CLBL and HUNLOCK

0A 8A XD6######

1: only vertical and protection blanking available on pins CLBL and HUNLOCK

AGCDIS 0: AGC in vertical oscillator active 0B 8B # D6 ######

1: AGC in vertical oscillator inhibited

FHMULT 0: EW output independent of horizontal frequency 0B 8B D7 #######

1: EW output tracks with horizontal frequency

VSC 0: VLIN, HCORT and HCORB adjustments

enabled

02 82 XD6######

1: VLIN, HCORT and HCORB adjustments forced to centre value

MOD 0: horizontal and vertical moire cancellation

enabled

08 88D7#######

1: horizontal and vertical moire cancellation disabled

VOVSCN 0: vertical size 100% 0F 8F X D6 ######

1: vertical size 116.8% for VGA350

CLAMP 0: trailing edge for horizontal clamp 09 89 # D6 ######

1: leading edge for horizontal clamp

VBLK 0: vertical blanking = 260 µs 09 89D7#######

1: vertical blanking = 340 µs

ACD 0: ASCOR disconnected from PLL2 04 84 X D6 ######

1: ASCOR internally connected with PLL2

STDBY

(3)

0: internal power supply enabled 1A 9A # XXXXX#D0 1: internal power supply disabled

SOFTST

(3)

0: soft start not released (pin HPLL2 pulled to ground)

1A 9A #XXXXXD1#

1: soft start is released (power-up via pin HPLL2)

Page 35

1999 Jul 13 35

Philips Semiconductors Product speciﬁcation

C-bus autosync deﬂection controller for

PC monitors

TDA4856

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List of I

C-bus controlled functions

I2C-bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress:

• SAD1 is the register subaddress to be used for transmissions in direct mode

• SAD2 is the register subaddress to be used for transmissions in buffered mode.

Table 6 Controlled functions; notes 1 and 2

FUNCTION NAME BITS

SAD1 (HEX)

SAD2 (HEX)

CONTROL

BIT

RANGE

FUNCTION

TRACKS WITH

D7 D6 D5 D4 D3 D2 D1 D0

Horizontal size HSIZE 8 01 81 D7 D6 D5 D4 D3 D2 D1 D0 − 0.1 to 3.6 V − Horizontal

position

HPOS 8 07 87 D7 D6 D5 D4 D3 D2 D1 D0 −±13% of horizontal

period

−

Horizontal pincushion

HPIN 6 0F 8F X # D5 D4 D3 D2 D1 D0 − 0 to 1.42 V VSIZE, VOVSCN,

VPOS, HSIZE and HSMOD

Horizontal trapezium correction

HTRAP 6 03 83 X X D5 D4 D3 D2 D1 D0 −±500 mV (p-p) VSIZE, VOVSCN,

VPOS, HSIZE and HSMOD

Horizontal cornercorrection at top of picture

HCORT 6 04 84 X # D5 D4 D3 D2 D1 D0 VSC +15 to −46% of

parabola amplitude

VSIZE, VOVSCN, VPOS, HSIZE and HSMOD

Horizontal cornercorrection at bottom of picture

HCORB 6 02 82 X # D5 D4 D3 D2 D1 D0 VSC +15 to −46% of

parabola amplitude

VSIZE, VOVSCN, VPOS, HSIZE and HSMOD

Horizontal parallelogram

HPARAL 6 09 89 # # D5 D4 D3 D2 D1 D0 ACD ±1.2% of horizontal

period

VSIZE, VOVSCN and VPOS

EW pin balance HPINBAL 6 0B 8B # # D5 D4 D3 D2 D1 D0 ACD ±1.2% of horizontal

period

VSIZE, VOVSCN

and VPOS Vertical size VSIZE 7 08 88 # D6 D5 D4 D3 D2 D1 D0 − 60 to 100% VSMOD Vertical position VPOS 7 0D 8D X D6 D5 D4 D3 D2 D1 D0 −±11.5% VSMOD Vertical gain VGAIN 6 0A 8A X # D5 D4 D3 D2 D1 D0 − 70 to 100% − Vertical offset VOFFS 4 0E 8E ####D3D2D1D0 −±4% − Vertical linearity VLIN 4 05 85 D7 D6 D5 D4 #### VSC −2to−46% VSIZE, VOVSCN,

VPOS and VSMOD Vertical linearity

balance

VLINBAL 4 05 85 ####D3D2D1D0 −±1.4% of 100%

vertical size

VSIZE, VOVSCN,

VPOS and VSMOD

Page 36

1999 Jul 13 36

Philips Semiconductors Product speciﬁcation

C-bus autosync deﬂection controller for

PC monitors

TDA4856

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Notes

1. X = don’t care.

2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be transferred.

Moire cancellation via vertical position

VMOIRE 6 00 80 X X D5 D4 D3 D2 D1 D0 MOD 0 to 0.08% of

vertical amplitude

−

Moire cancellation via horizontal position

HMOIRE 6 06 86 X X D5 D4 D3 D2 D1 D0 MOD 0.07% of horizontal

period

−

Vertical focus VFOCUS 4 0E 8E D7 D6 D5 D4 #### − 0 to 1.1 V VSIZE, VOVSCN

and VPOS Horizontal focus HFOCUS 5 0C 8C # # X D4 D3 D2 D1 D0 − 0 to 3.3 V − Horizontal focus

pre-correction

HFOCAD 2 0C 8C D7 D6 X ##### − 300 to 450 ns −

FUNCTION NAME BITS

SAD1 (HEX)

SAD2 (HEX)

CONTROL

BIT

RANGE

FUNCTION

TRACKS WITH

D7 D6 D5 D4 D3 D2 D1 D0

Page 37

1999 Jul 13 37

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Start-up procedure

VCC< 8.3 V:

• As long as the supply voltage is too low for correct operation, the IC will give no acknowledge due to internal Power-on reset (POR)

• Supply current is 9 mA or less.

VCC> 8.3 V:

• The internal POR has ended and the IC is in standby mode

• Control bits STDBY and SOFTST are reset to their start values

• All other register contents are random

• Pin HUNLOCK is at HIGH-level.

Setting control bit STDBY = 0:

• Enables internal power supply

• Supply current increases from 9 to 70 mA

• When VCC< 8.6 V register SOFTST cannot be set by

the I2C-bus

• Output stages are disabled, except the vertical output

• Pin HUNLOCK is at HIGH-level.

Setting all registers to defined values:

• Due to the hardware configuration of the IC (no auto-increment) any register setting needs a complete 3-byte I2C-bus data transfer as follows: START - IC address - subaddress - data - STOP.

Setting control bit SOFTST = 1:

• Before starting the soft-start sequence a delay of minimum 80 ms is necessary to obtain correct function of the horizontal drive

• HDRV duty cycle increases

• BDRV duty cycle increases

• PLL1 and PLL2 are enabled.

IC in full operation:

• Pin HUNLOCK is at LOW-level when PLL1 is locked

• Any change of the register content will result in

immediate change of the output behaviour

• Setting control bit SOFTST = 0 is the only way (except power-down via pin VCC) to leave the operating mode.

Soft-down sequence:

• See L4 of Fig.19 for starting the soft-down sequence.

Fig.18 I2C-bus flow for start-up.

(1) See Fig.19.

MGL791

START

Standby mode (XXXX XX01)

STDBY = 1

SOFTST = 0

all other register contents are random

Protection mode (XXXX XX00)

STDBY = 0

SOFTST = 0

all other register contents are random

Protection mode (XXXX XX00)

STDBY = 0

SOFTST = 0

registers are pre-set

change/refresh of data?

S 8CH A 1AH A 00H A P

S 8CH A 1AH A 02H A P

S 8CH A SAD A DATA A P

Operating mode (XXXX XX10)

STDBY = 0

SOFTST = 1

Soft-start sequence (XXXX XX10)

STDBY = 0

SOFTST = 1

Power-down mode (XXXX XXXX)

no acknowledge is given by IC

all register contents are random

(1)

VCC > 8.3 V

yes

SOFTST = 0?

yes

all registers defined?

yes

Page 38

1999 Jul 13 38

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Protection and standby mode

Soft-down sequence:

• Start the sequence by setting control bit SOFTST = 0

• BDRV duty cycle decreases

• HDRV duty cycle decreases.

Protection mode:

• Pins HDRV and BDRV are floating

• Continuous blanking at pin CLBL is active

• Pin HUNLOCK is floating

• PLL1 and PLL2 are disabled

• Register contents are kept in internal memory.

Protection mode can be left by 3 ways:

1. Entering standby mode by setting control

bit SOFTST = 0 and control bit STDBY = 1

2. Starting the soft-start sequence by setting control

bit SOFTST = 1 (bit STDBY = don’t care); see L3 of Fig.18 for continuation

3. Decreasing the supply voltage below 8.1 V.

Standby mode:

• Set control bit STDBY = 1

• Driver outputs are floating (same as protection mode)

• Supply current is 9 mA

• Only the I2C-bus section and protection circuits are

operative

• Contents of all registers except the value of bit STDBY and bit SOFTST are lost

• See L2 of Fig.18 for continuation.

Fig.19 I2C-bus flow for protection and standby

mode.

(1) See Fig.18.

MGL790

Standby mode (XXXX XX01)

STDBY = 1

SOFTST = 0

all other register contents are random

Soft-down sequence (XXXX XX00)

STDBY = 0

SOFTST = 0

(1)

yes

SOFTST = 1?

yes

(1)

Protection mode (XXXX XX00)

STDBY = 0

SOFTST = 0

registers are set

STDBY = 1?

S 8CH A 1AH A 00H A P

S 8CH A 1AH A 01H A P

Page 39

1999 Jul 13 39

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Fig.20 I2C-bus flow for any mode.

(1) See Fig.18.

handbook, full pagewidth

MGM079

(ANY Mode)

Power-Down Mode

no acknowledge is given by IC

all register contents are random

(1)

VCC < 8.1 V

a soft-down sequency followed by a soft start sequence is generated internally.

8.6 V

8.1 V V

IC enters standby mode.

8.6 V

8.1 V

Power-down mode

Power dip of VCC< 8.6 V:

• The soft-down sequence is started first.

• Then the soft-start sequence is generated internally.

Power dip of VCC< 8.1 V or VCC shut-down:

• This function is independent from the operating mode, so it works under any condition.

• All driver outputs are immediately disabled

• IC enters standby mode.

Standby mode detection

Execute data transmission twice to assure that there was no data transfer error.

MGS276

yes

chip address

8CHS 0XHAAAPXXH

subaddress data

C-bus transmission

Normal operation

acknowledge was

given on data?

yes

chip address

8CHS 0XHAAAPXXH

subaddress data

C-bus transmission

acknowledge was

given on data?

Standby mode

Fig.21 Possible standby mode detection.

Page 40

1999 Jul 13 40

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

APPLICATION INFORMATION

Fig.22 Application and timing for feedback mode.

For f < 50 kHz and C2 < 47 nF calculation formulas and behaviour of the OTA are the same as for an OP. An exception is the limited output current at BOP (pin 3). See Chapter “Characteristics”, Row Head “B+ control section; see Figs 22 and 23”.

(1) The recommended value for R6 is 1 kΩ.

a. Feedback mode application.

b. Waveforms for normal operation. c. Waveforms for fault condition.

handbook, full pagewidth

HDRV

BSENS

= V

BOP

BDRV

off(min)

horizontal flyback pulse

RESTART(BSENS)

STOP(BSENS)

MBG600

d(BDRV)

handbook, full pagewidth

SOFT START

SRQ

HORIZONTAL

OUTPUT

STAGE

HDRV

TR1

(1)

OTA

2.5 V

HPLL2

5 V

BIN

BOP

BSENS

BDRV

BOP

EWDRV

>10 nF

horizontal flyback pulse

INVERTING

BUFFER

MGM080

DISCHARGE

Page 41

1999 Jul 13 41

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Fig.23 Application and timing for feed forward mode.

a. Forward mode application.

b. Waveforms for normal operation. c. Waveforms for fault condition.

handbook, full pagewidth

BOP

STOP(BSENS)

off

RESTART(BSENS)

HDRV

BSENS

BDRV

horizontal flyback pulse

MOSFET

(discharge time of C

BSENS

)

MBG602

d(BDRV)

SOFT START

SRQ

HDRV

(1)

OTA

2.5 V

HPLL2

BOP

BSENS

BDRV

INVERTING

BUFFER

DISCHARGE

HORIZONTAL

OUTPUT

STAGE

TR1

BIN

BSENS

BOP

R1 R2

TR2

> 10 nF

>2 nF

horizontal

flyback pulse

MOSFET

EHT

transformer

EHT adjustment

power-down

MGM081

(1) The recommended value for R4 is 1 kΩ.

Page 42

1999 Jul 13 42

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Start-up sequence and shut-down sequence

Fig.24 Activation of start-up sequence and shut-down sequence via supply voltage.

a. Start-up sequence.

b. Shut-down sequence.

(1) See Fig.25a. (2) See Fig.25b.

handbook, full pagewidth

MGS278

continuous blanking activated on pins CLBL and HUNLOCK PLL2 soft-down sequence is triggered

(2)

8.6 V

8.1 V

3.5 V continuous blanking disappears

time

no data accepted from I

C-bus

video clamping pulse and vertical outputs disabled

handbook, full pagewidth

continuous blanking off PLL2 soft start/soft-down enabled

(1)

8.6 V

3.5 V continuous blanking activated on pins CLBL and HUNLOCK

time

8.3 V data accepted from I

C-bus video clamping pulse and vertical outputs enabled if control bit STDBY = 0

MGS277

Page 43

1999 Jul 13 43

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

PLL2 soft start sequence and PLL2 soft-down sequence

Fig.25 Activation of PLL2 soft-start sequence and PLL2 soft-down sequence via the I2C-bus.

a. PLL2 soft start sequence, if VCC> 8.6 V.

b. PLL2 soft-down sequence, if VCC> 8.6 V.

(1) HDRV and BDRV are floating for VCC< 8.6 V.

handbook, full pagewidth

HPLL2

continuous blanking off PLL2 enabled frequency detector enabled HDRV/HFLB protection enabled

4.6 V

4.0 V

1.8 V

time

HDRV duty cycle begins to increase

BDRV duty cycle begins to increase HDRV duty cycle has reached nominal value

3.2 V

BDRV duty cycle has reached nominal value

duty cycle increases

MGS279

handbook, full pagewidth

HPLL2

continuous blanking activated on pins CLBL and HUNLOCK PLL2 disabled frequency detector disabled HDRV/HFLB protection disabled

4.6 V

4.0 V

1.8 V

time

HDRV floating

BDRV duty cycle begins to decrease

(1)

2.8 V BDRV floating HDRV duty cycle begins to decrease

(1)

duty cycle decreases

MGS280

Page 44

1999 Jul 13 44

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Fig.26 Activation of soft-down sequence via pin XRAY.

handbook, full pagewidth

MGS281

floating

X-ray latch triggered

XRAY

HUNLOCK

BDRV duty cycle

HDRV duty cycle

Vertical linearity error Horizontal focus pre-correction

Fig.27 Definition of vertical linearity error.

(1) I

VOUT=IVOUT1

− I

VOUT2

(2) I1=I

VOUT

at V

VCAP

= 1.9 V.

(3) I2=I

VOUT

at V

VCAP

= 2.6 V.

(4) I3=I

VOUT

at V

VCAP

= 3.3 V.

Which means:

Vertical linearity error =

I1I3–

--------------

1 max

1I2

–

--------------

2I3

–

--------------





–

handbook, halfpage

(2)

(3)

(4)

VOUT

(1)

(µA)

+415

−415

VCAP

MBG551

Fig.28 Definition of horizontal focus pre-correction.

handbook, halfpage

MGS282

(1)

(2)

precor

= 450 ns

precor

= 300 ns

(1) Line flyback pulse at HFLB (pin 1). (2) Horizontal focus parabola at FOCUS (pin 32).

Page 45

1999 Jul 13 45

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Printed-circuit board layout

Fig.29 Hints for printed-circuit board (PCB) layout.

handbook, full pagewidth

TDA4856

external components of horizontal section

B-drive line in parallel to ground

47 pF

2.2 nF47 nF

100 µF

12 V

external components of vertical section

further connections to other components

or ground paths are not allowed

only this path may be connected

to general ground of PCB

external components of driver stages

For optimum performance of the TDA4856 the ground paths must be routed as shown. Only one connection to other grounds on the PCB is allowed. Note: The tracks for HDRV and BDRV should be kept separate.

pin 25 should be the 'star point' for all small signal components

no external ground tracks connected here

MGS283

SMD

Page 46

1999 Jul 13 46

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

INTERNAL PIN CONFIGURATION

PIN SYMBOL INTERNAL CIRCUIT

1 HFLB

2 XRAY

3 BOP

4 BSENS

1.5 kΩ

7 x

MBG561

5 kΩ

6.25 V

MBG562

5.3 V

MBG563

MBG564

Page 47

1999 Jul 13 47

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

5 BIN

6 BDRV

7 PGND power ground, connected to substrate 8 HDRV

9 XSEL

10 V

11 EWDRV

PIN SYMBOL INTERNAL CIRCUIT

MBG565

MBG566

MGM089

MBK381

4 kΩ

MGM090

108 Ω

MBG570

Page 48

1999 Jul 13 48

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

12 VOUT2

13 VOUT1

14 VSYNC

15 HSYNC

16 CLBL

PIN SYMBOL INTERNAL CIRCUIT

MBG571

MBG572

100 Ω

2 kΩ

7.3 V

1.4 V

MBG573

85 Ω

1.4 V

1.28 V

7.3 V

MBG574

MBG575

Page 49

1999 Jul 13 49

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

17 HUNLOCK

18 SCL

19 SDA

20 ASCOR

21 VSMOD

PIN SYMBOL INTERNAL CIRCUIT

MGM091

MGM092

MGM093

480 Ω

MGM094

250 Ω

5 V

MGM095

Page 50

1999 Jul 13 50

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

22 VAGC

23 VREF

24 VCAP

25 SGND signal ground 26 HPLL1

PIN SYMBOL INTERNAL CIRCUIT

MBG581

3 V

MBG582

MBG583

4.3 V

MGM096

Page 51

1999 Jul 13 51

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

27 HBUF

28 HREF 29 HCAP

30 HPLL2

PIN SYMBOL INTERNAL CIRCUIT

MGM097

5 V

76 Ω

2.525 V

7.7 V

MBG585

7.7 V

6.25 V

HFLB

MGM098

Page 52

1999 Jul 13 52

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

31 HSMOD

32 FOCUS

PIN SYMBOL INTERNAL CIRCUIT

250 Ω

5 V

MGM099

200 Ω

120 Ω

MGM100

Electrostatic discharge (ESD) protection

Fig.30 ESD protection for pins 4, 11 to 13,

16 and 17.

MBG559

Fig.31 ESD protection for pins 2, 3, 5, 18 to 24

and 26 to 32.

7.3 V

MBG560

Page 53

1999 Jul 13 53

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

PACKAGE OUTLINE

UNIT b

cEe M

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

DIMENSIONS (mm are the original dimensions)

SOT232-1

92-11-17 95-02-04

max.

1.3

0.8

0.53

0.40

0.32

0.23

29.4

28.5

9.1

8.7

3.2

2.8

0.181.778 10.16

10.7

10.2

12.2

10.5

1.6

4.7 0.51 3.8

(e )

seating plane

w M

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1) (1)

(1)

max.

min.

max.

SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)

SOT232-1

Page 54

1999 Jul 13 54

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

SOLDERING Introduction to soldering through-hole mount

packages

This text gives a brief insight to wave, dip and manual soldering.Amore in-depth account of soldering ICs canbe found in our

“Data Handbook IC26; Integrated Circuit

Packages”

(document order number 9398 652 90011).

Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds.

Thetotalcontacttimeofsuccessive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T

stg(max)

). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

PACKAGE

SOLDERING METHOD

DIPPING WAVE

DBS, DIP, HDIP, SDIP, SIL suitable suitable

(1)

Page 55

1999 Jul 13 55

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

Purchase of Philips I

C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

Page 56

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors – a w orldwide compan y

For all other countries apply to: Philips Semiconductors,

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Printed in The Netherlands 545004/02/pp56 Date of release: 1999 Jul 13 Document order number: 9397 750 04963

Datasheet TDA4856-V2 Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual